blk_box_bc.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000b8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00006144 080000b8 080000b8 000010b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000100 080061fc 080061fc 000071fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080062fc 080062fc 00008068 2**0 CONTENTS 4 .ARM 00000000 080062fc 080062fc 00008068 2**0 CONTENTS 5 .preinit_array 00000000 080062fc 080062fc 00008068 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080062fc 080062fc 000072fc 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08006300 08006300 00007300 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000068 20000000 08006304 00008000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 000002c0 20000068 0800636c 00008068 2**2 ALLOC 10 ._user_heap_stack 00000600 20000328 0800636c 00008328 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00008068 2**0 CONTENTS, READONLY 12 .debug_info 00011938 00000000 00000000 00008090 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002a98 00000000 00000000 000199c8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000ec8 00000000 00000000 0001c460 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000b85 00000000 00000000 0001d328 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000175a0 00000000 00000000 0001dead 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000142e2 00000000 00000000 0003544d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 0008bf65 00000000 00000000 0004972f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000d5694 2**0 CONTENTS, READONLY 20 .debug_frame 00003c38 00000000 00000000 000d56d8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000066 00000000 00000000 000d9310 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000b8 <__do_global_dtors_aux>: 80000b8: b510 push {r4, lr} 80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>) 80000bc: 7823 ldrb r3, [r4, #0] 80000be: 2b00 cmp r3, #0 80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a> 80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>) 80000c4: 2b00 cmp r3, #0 80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16> 80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>) 80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16> 80000cc: bf00 nop 80000ce: 2301 movs r3, #1 80000d0: 7023 strb r3, [r4, #0] 80000d2: bd10 pop {r4, pc} 80000d4: 20000068 .word 0x20000068 80000d8: 00000000 .word 0x00000000 80000dc: 080061e4 .word 0x080061e4 080000e0 : 80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 ) 80000e2: b510 push {r4, lr} 80000e4: 2b00 cmp r3, #0 80000e6: d003 beq.n 80000f0 80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 ) 80000ea: 4804 ldr r0, [pc, #16] @ (80000fc ) 80000ec: e000 b.n 80000f0 80000ee: bf00 nop 80000f0: bd10 pop {r4, pc} 80000f2: 46c0 nop @ (mov r8, r8) 80000f4: 00000000 .word 0x00000000 80000f8: 2000006c .word 0x2000006c 80000fc: 080061e4 .word 0x080061e4 08000100 <__gnu_thumb1_case_shi>: 8000100: b403 push {r0, r1} 8000102: 4671 mov r1, lr 8000104: 0849 lsrs r1, r1, #1 8000106: 0040 lsls r0, r0, #1 8000108: 0049 lsls r1, r1, #1 800010a: 5e09 ldrsh r1, [r1, r0] 800010c: 0049 lsls r1, r1, #1 800010e: 448e add lr, r1 8000110: bc03 pop {r0, r1} 8000112: 4770 bx lr 08000114 <__udivsi3>: 8000114: 2200 movs r2, #0 8000116: 0843 lsrs r3, r0, #1 8000118: 428b cmp r3, r1 800011a: d374 bcc.n 8000206 <__udivsi3+0xf2> 800011c: 0903 lsrs r3, r0, #4 800011e: 428b cmp r3, r1 8000120: d35f bcc.n 80001e2 <__udivsi3+0xce> 8000122: 0a03 lsrs r3, r0, #8 8000124: 428b cmp r3, r1 8000126: d344 bcc.n 80001b2 <__udivsi3+0x9e> 8000128: 0b03 lsrs r3, r0, #12 800012a: 428b cmp r3, r1 800012c: d328 bcc.n 8000180 <__udivsi3+0x6c> 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d30d bcc.n 8000150 <__udivsi3+0x3c> 8000134: 22ff movs r2, #255 @ 0xff 8000136: 0209 lsls r1, r1, #8 8000138: ba12 rev r2, r2 800013a: 0c03 lsrs r3, r0, #16 800013c: 428b cmp r3, r1 800013e: d302 bcc.n 8000146 <__udivsi3+0x32> 8000140: 1212 asrs r2, r2, #8 8000142: 0209 lsls r1, r1, #8 8000144: d065 beq.n 8000212 <__udivsi3+0xfe> 8000146: 0b03 lsrs r3, r0, #12 8000148: 428b cmp r3, r1 800014a: d319 bcc.n 8000180 <__udivsi3+0x6c> 800014c: e000 b.n 8000150 <__udivsi3+0x3c> 800014e: 0a09 lsrs r1, r1, #8 8000150: 0bc3 lsrs r3, r0, #15 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x46> 8000156: 03cb lsls r3, r1, #15 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b83 lsrs r3, r0, #14 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x52> 8000162: 038b lsls r3, r1, #14 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b43 lsrs r3, r0, #13 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x5e> 800016e: 034b lsls r3, r1, #13 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0b03 lsrs r3, r0, #12 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x6a> 800017a: 030b lsls r3, r1, #12 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0ac3 lsrs r3, r0, #11 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x76> 8000186: 02cb lsls r3, r1, #11 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a83 lsrs r3, r0, #10 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x82> 8000192: 028b lsls r3, r1, #10 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a43 lsrs r3, r0, #9 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x8e> 800019e: 024b lsls r3, r1, #9 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: 0a03 lsrs r3, r0, #8 80001a6: 428b cmp r3, r1 80001a8: d301 bcc.n 80001ae <__udivsi3+0x9a> 80001aa: 020b lsls r3, r1, #8 80001ac: 1ac0 subs r0, r0, r3 80001ae: 4152 adcs r2, r2 80001b0: d2cd bcs.n 800014e <__udivsi3+0x3a> 80001b2: 09c3 lsrs r3, r0, #7 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xa8> 80001b8: 01cb lsls r3, r1, #7 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0983 lsrs r3, r0, #6 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xb4> 80001c4: 018b lsls r3, r1, #6 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0943 lsrs r3, r0, #5 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xc0> 80001d0: 014b lsls r3, r1, #5 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 0903 lsrs r3, r0, #4 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xcc> 80001dc: 010b lsls r3, r1, #4 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 08c3 lsrs r3, r0, #3 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xd8> 80001e8: 00cb lsls r3, r1, #3 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0883 lsrs r3, r0, #2 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xe4> 80001f4: 008b lsls r3, r1, #2 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 0843 lsrs r3, r0, #1 80001fc: 428b cmp r3, r1 80001fe: d301 bcc.n 8000204 <__udivsi3+0xf0> 8000200: 004b lsls r3, r1, #1 8000202: 1ac0 subs r0, r0, r3 8000204: 4152 adcs r2, r2 8000206: 1a41 subs r1, r0, r1 8000208: d200 bcs.n 800020c <__udivsi3+0xf8> 800020a: 4601 mov r1, r0 800020c: 4152 adcs r2, r2 800020e: 4610 mov r0, r2 8000210: 4770 bx lr 8000212: e7ff b.n 8000214 <__udivsi3+0x100> 8000214: b501 push {r0, lr} 8000216: 2000 movs r0, #0 8000218: f000 f8f0 bl 80003fc <__aeabi_idiv0> 800021c: bd02 pop {r1, pc} 800021e: 46c0 nop @ (mov r8, r8) 08000220 <__aeabi_uidivmod>: 8000220: 2900 cmp r1, #0 8000222: d0f7 beq.n 8000214 <__udivsi3+0x100> 8000224: e776 b.n 8000114 <__udivsi3> 8000226: 4770 bx lr 08000228 <__divsi3>: 8000228: 4603 mov r3, r0 800022a: 430b orrs r3, r1 800022c: d47f bmi.n 800032e <__divsi3+0x106> 800022e: 2200 movs r2, #0 8000230: 0843 lsrs r3, r0, #1 8000232: 428b cmp r3, r1 8000234: d374 bcc.n 8000320 <__divsi3+0xf8> 8000236: 0903 lsrs r3, r0, #4 8000238: 428b cmp r3, r1 800023a: d35f bcc.n 80002fc <__divsi3+0xd4> 800023c: 0a03 lsrs r3, r0, #8 800023e: 428b cmp r3, r1 8000240: d344 bcc.n 80002cc <__divsi3+0xa4> 8000242: 0b03 lsrs r3, r0, #12 8000244: 428b cmp r3, r1 8000246: d328 bcc.n 800029a <__divsi3+0x72> 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d30d bcc.n 800026a <__divsi3+0x42> 800024e: 22ff movs r2, #255 @ 0xff 8000250: 0209 lsls r1, r1, #8 8000252: ba12 rev r2, r2 8000254: 0c03 lsrs r3, r0, #16 8000256: 428b cmp r3, r1 8000258: d302 bcc.n 8000260 <__divsi3+0x38> 800025a: 1212 asrs r2, r2, #8 800025c: 0209 lsls r1, r1, #8 800025e: d065 beq.n 800032c <__divsi3+0x104> 8000260: 0b03 lsrs r3, r0, #12 8000262: 428b cmp r3, r1 8000264: d319 bcc.n 800029a <__divsi3+0x72> 8000266: e000 b.n 800026a <__divsi3+0x42> 8000268: 0a09 lsrs r1, r1, #8 800026a: 0bc3 lsrs r3, r0, #15 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x4c> 8000270: 03cb lsls r3, r1, #15 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b83 lsrs r3, r0, #14 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x58> 800027c: 038b lsls r3, r1, #14 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b43 lsrs r3, r0, #13 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x64> 8000288: 034b lsls r3, r1, #13 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0b03 lsrs r3, r0, #12 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x70> 8000294: 030b lsls r3, r1, #12 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0ac3 lsrs r3, r0, #11 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x7c> 80002a0: 02cb lsls r3, r1, #11 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a83 lsrs r3, r0, #10 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x88> 80002ac: 028b lsls r3, r1, #10 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a43 lsrs r3, r0, #9 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0x94> 80002b8: 024b lsls r3, r1, #9 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: 0a03 lsrs r3, r0, #8 80002c0: 428b cmp r3, r1 80002c2: d301 bcc.n 80002c8 <__divsi3+0xa0> 80002c4: 020b lsls r3, r1, #8 80002c6: 1ac0 subs r0, r0, r3 80002c8: 4152 adcs r2, r2 80002ca: d2cd bcs.n 8000268 <__divsi3+0x40> 80002cc: 09c3 lsrs r3, r0, #7 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xae> 80002d2: 01cb lsls r3, r1, #7 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0983 lsrs r3, r0, #6 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xba> 80002de: 018b lsls r3, r1, #6 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0943 lsrs r3, r0, #5 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xc6> 80002ea: 014b lsls r3, r1, #5 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 0903 lsrs r3, r0, #4 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xd2> 80002f6: 010b lsls r3, r1, #4 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 08c3 lsrs r3, r0, #3 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xde> 8000302: 00cb lsls r3, r1, #3 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0883 lsrs r3, r0, #2 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xea> 800030e: 008b lsls r3, r1, #2 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 0843 lsrs r3, r0, #1 8000316: 428b cmp r3, r1 8000318: d301 bcc.n 800031e <__divsi3+0xf6> 800031a: 004b lsls r3, r1, #1 800031c: 1ac0 subs r0, r0, r3 800031e: 4152 adcs r2, r2 8000320: 1a41 subs r1, r0, r1 8000322: d200 bcs.n 8000326 <__divsi3+0xfe> 8000324: 4601 mov r1, r0 8000326: 4152 adcs r2, r2 8000328: 4610 mov r0, r2 800032a: 4770 bx lr 800032c: e05d b.n 80003ea <__divsi3+0x1c2> 800032e: 0fca lsrs r2, r1, #31 8000330: d000 beq.n 8000334 <__divsi3+0x10c> 8000332: 4249 negs r1, r1 8000334: 1003 asrs r3, r0, #32 8000336: d300 bcc.n 800033a <__divsi3+0x112> 8000338: 4240 negs r0, r0 800033a: 4053 eors r3, r2 800033c: 2200 movs r2, #0 800033e: 469c mov ip, r3 8000340: 0903 lsrs r3, r0, #4 8000342: 428b cmp r3, r1 8000344: d32d bcc.n 80003a2 <__divsi3+0x17a> 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d312 bcc.n 8000372 <__divsi3+0x14a> 800034c: 22fc movs r2, #252 @ 0xfc 800034e: 0189 lsls r1, r1, #6 8000350: ba12 rev r2, r2 8000352: 0a03 lsrs r3, r0, #8 8000354: 428b cmp r3, r1 8000356: d30c bcc.n 8000372 <__divsi3+0x14a> 8000358: 0189 lsls r1, r1, #6 800035a: 1192 asrs r2, r2, #6 800035c: 428b cmp r3, r1 800035e: d308 bcc.n 8000372 <__divsi3+0x14a> 8000360: 0189 lsls r1, r1, #6 8000362: 1192 asrs r2, r2, #6 8000364: 428b cmp r3, r1 8000366: d304 bcc.n 8000372 <__divsi3+0x14a> 8000368: 0189 lsls r1, r1, #6 800036a: d03a beq.n 80003e2 <__divsi3+0x1ba> 800036c: 1192 asrs r2, r2, #6 800036e: e000 b.n 8000372 <__divsi3+0x14a> 8000370: 0989 lsrs r1, r1, #6 8000372: 09c3 lsrs r3, r0, #7 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x154> 8000378: 01cb lsls r3, r1, #7 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0983 lsrs r3, r0, #6 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x160> 8000384: 018b lsls r3, r1, #6 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0943 lsrs r3, r0, #5 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x16c> 8000390: 014b lsls r3, r1, #5 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 0903 lsrs r3, r0, #4 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x178> 800039c: 010b lsls r3, r1, #4 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 08c3 lsrs r3, r0, #3 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x184> 80003a8: 00cb lsls r3, r1, #3 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: 0883 lsrs r3, r0, #2 80003b0: 428b cmp r3, r1 80003b2: d301 bcc.n 80003b8 <__divsi3+0x190> 80003b4: 008b lsls r3, r1, #2 80003b6: 1ac0 subs r0, r0, r3 80003b8: 4152 adcs r2, r2 80003ba: d2d9 bcs.n 8000370 <__divsi3+0x148> 80003bc: 0843 lsrs r3, r0, #1 80003be: 428b cmp r3, r1 80003c0: d301 bcc.n 80003c6 <__divsi3+0x19e> 80003c2: 004b lsls r3, r1, #1 80003c4: 1ac0 subs r0, r0, r3 80003c6: 4152 adcs r2, r2 80003c8: 1a41 subs r1, r0, r1 80003ca: d200 bcs.n 80003ce <__divsi3+0x1a6> 80003cc: 4601 mov r1, r0 80003ce: 4663 mov r3, ip 80003d0: 4152 adcs r2, r2 80003d2: 105b asrs r3, r3, #1 80003d4: 4610 mov r0, r2 80003d6: d301 bcc.n 80003dc <__divsi3+0x1b4> 80003d8: 4240 negs r0, r0 80003da: 2b00 cmp r3, #0 80003dc: d500 bpl.n 80003e0 <__divsi3+0x1b8> 80003de: 4249 negs r1, r1 80003e0: 4770 bx lr 80003e2: 4663 mov r3, ip 80003e4: 105b asrs r3, r3, #1 80003e6: d300 bcc.n 80003ea <__divsi3+0x1c2> 80003e8: 4240 negs r0, r0 80003ea: b501 push {r0, lr} 80003ec: 2000 movs r0, #0 80003ee: f000 f805 bl 80003fc <__aeabi_idiv0> 80003f2: bd02 pop {r1, pc} 080003f4 <__aeabi_idivmod>: 80003f4: 2900 cmp r1, #0 80003f6: d0f8 beq.n 80003ea <__divsi3+0x1c2> 80003f8: e716 b.n 8000228 <__divsi3> 80003fa: 4770 bx lr 080003fc <__aeabi_idiv0>: 80003fc: 4770 bx lr 80003fe: 46c0 nop @ (mov r8, r8) 08000400 : bool rc522_request(uint8_t reqMode, uint8_t *tagType); bool rc522_antiColl(uint8_t* serNum); void spi_cs_rfid_write(bool state) { 8000400: b580 push {r7, lr} 8000402: b082 sub sp, #8 8000404: af00 add r7, sp, #0 8000406: 0002 movs r2, r0 8000408: 1dfb adds r3, r7, #7 800040a: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(RFID_CS_GPIO_Port, RFID_CS_Pin, state); 800040c: 1dfb adds r3, r7, #7 800040e: 781a ldrb r2, [r3, #0] 8000410: 23a0 movs r3, #160 @ 0xa0 8000412: 05db lsls r3, r3, #23 8000414: 2110 movs r1, #16 8000416: 0018 movs r0, r3 8000418: f001 fc24 bl 8001c64 } 800041c: 46c0 nop @ (mov r8, r8) 800041e: 46bd mov sp, r7 8000420: b002 add sp, #8 8000422: bd80 pop {r7, pc} 08000424 : uint8_t rc522_regRead8(uint8_t reg) { 8000424: b590 push {r4, r7, lr} 8000426: b085 sub sp, #20 8000428: af00 add r7, sp, #0 800042a: 0002 movs r2, r0 800042c: 1dfb adds r3, r7, #7 800042e: 701a strb r2, [r3, #0] spi_cs_rfid_write(0); 8000430: 2000 movs r0, #0 8000432: f7ff ffe5 bl 8000400 reg = ((reg << 1) & 0x7E) | 0x80; 8000436: 1dfb adds r3, r7, #7 8000438: 781b ldrb r3, [r3, #0] 800043a: 005b lsls r3, r3, #1 800043c: b25b sxtb r3, r3 800043e: 227e movs r2, #126 @ 0x7e 8000440: 4013 ands r3, r2 8000442: b25b sxtb r3, r3 8000444: 2280 movs r2, #128 @ 0x80 8000446: 4252 negs r2, r2 8000448: 4313 orrs r3, r2 800044a: b25b sxtb r3, r3 800044c: b2da uxtb r2, r3 800044e: 1dfb adds r3, r7, #7 8000450: 701a strb r2, [r3, #0] // spi1_transmit(®, 1); // TODO: change to interrupting or something. HAL_SPI_Transmit(&hspi1, ®, 1, 1000); 8000452: 23fa movs r3, #250 @ 0xfa 8000454: 009b lsls r3, r3, #2 8000456: 1df9 adds r1, r7, #7 8000458: 480c ldr r0, [pc, #48] @ (800048c ) 800045a: 2201 movs r2, #1 800045c: f003 faac bl 80039b8 uint8_t dataRd=0; 8000460: 210f movs r1, #15 8000462: 187b adds r3, r7, r1 8000464: 2200 movs r2, #0 8000466: 701a strb r2, [r3, #0] HAL_SPI_Receive(&hspi1, &dataRd, 1, 1000); 8000468: 23fa movs r3, #250 @ 0xfa 800046a: 009b lsls r3, r3, #2 800046c: 000c movs r4, r1 800046e: 1879 adds r1, r7, r1 8000470: 4806 ldr r0, [pc, #24] @ (800048c ) 8000472: 2201 movs r2, #1 8000474: f003 fc00 bl 8003c78 // spi1_receive(&dataRd, 1); spi_cs_rfid_write(1); 8000478: 2001 movs r0, #1 800047a: f7ff ffc1 bl 8000400 return dataRd; 800047e: 193b adds r3, r7, r4 8000480: 781b ldrb r3, [r3, #0] } 8000482: 0018 movs r0, r3 8000484: 46bd mov sp, r7 8000486: b005 add sp, #20 8000488: bd90 pop {r4, r7, pc} 800048a: 46c0 nop @ (mov r8, r8) 800048c: 200000d8 .word 0x200000d8 08000490 : /** * @brief write register */ void rc522_regWrite8(uint8_t reg, uint8_t data8) { 8000490: b580 push {r7, lr} 8000492: b084 sub sp, #16 8000494: af00 add r7, sp, #0 8000496: 0002 movs r2, r0 8000498: 1dfb adds r3, r7, #7 800049a: 701a strb r2, [r3, #0] 800049c: 1dbb adds r3, r7, #6 800049e: 1c0a adds r2, r1, #0 80004a0: 701a strb r2, [r3, #0] spi_cs_rfid_write(0); 80004a2: 2000 movs r0, #0 80004a4: f7ff ffac bl 8000400 uint8_t txData[2] = {0x7E&(reg << 1), data8}; 80004a8: 1dfb adds r3, r7, #7 80004aa: 781b ldrb r3, [r3, #0] 80004ac: 005b lsls r3, r3, #1 80004ae: b2db uxtb r3, r3 80004b0: 227e movs r2, #126 @ 0x7e 80004b2: 4013 ands r3, r2 80004b4: b2da uxtb r2, r3 80004b6: 210c movs r1, #12 80004b8: 187b adds r3, r7, r1 80004ba: 701a strb r2, [r3, #0] 80004bc: 187b adds r3, r7, r1 80004be: 1dba adds r2, r7, #6 80004c0: 7812 ldrb r2, [r2, #0] 80004c2: 705a strb r2, [r3, #1] // spi1_transmit(txData, 2); HAL_SPI_Transmit(&hspi1, (uint8_t*)&txData, 2, 1000); 80004c4: 23fa movs r3, #250 @ 0xfa 80004c6: 009b lsls r3, r3, #2 80004c8: 1879 adds r1, r7, r1 80004ca: 4805 ldr r0, [pc, #20] @ (80004e0 ) 80004cc: 2202 movs r2, #2 80004ce: f003 fa73 bl 80039b8 spi_cs_rfid_write(1); 80004d2: 2001 movs r0, #1 80004d4: f7ff ff94 bl 8000400 } 80004d8: 46c0 nop @ (mov r8, r8) 80004da: 46bd mov sp, r7 80004dc: b004 add sp, #16 80004de: bd80 pop {r7, pc} 80004e0: 200000d8 .word 0x200000d8 080004e4 : /** * @brief set bit */ void rc522_setBit(uint8_t reg, uint8_t mask) { 80004e4: b580 push {r7, lr} 80004e6: b082 sub sp, #8 80004e8: af00 add r7, sp, #0 80004ea: 0002 movs r2, r0 80004ec: 1dfb adds r3, r7, #7 80004ee: 701a strb r2, [r3, #0] 80004f0: 1dbb adds r3, r7, #6 80004f2: 1c0a adds r2, r1, #0 80004f4: 701a strb r2, [r3, #0] rc522_regWrite8(reg, rc522_regRead8(reg)|mask); 80004f6: 1dfb adds r3, r7, #7 80004f8: 781b ldrb r3, [r3, #0] 80004fa: 0018 movs r0, r3 80004fc: f7ff ff92 bl 8000424 8000500: 0003 movs r3, r0 8000502: 001a movs r2, r3 8000504: 1dbb adds r3, r7, #6 8000506: 781b ldrb r3, [r3, #0] 8000508: 4313 orrs r3, r2 800050a: b2da uxtb r2, r3 800050c: 1dfb adds r3, r7, #7 800050e: 781b ldrb r3, [r3, #0] 8000510: 0011 movs r1, r2 8000512: 0018 movs r0, r3 8000514: f7ff ffbc bl 8000490 } 8000518: 46c0 nop @ (mov r8, r8) 800051a: 46bd mov sp, r7 800051c: b002 add sp, #8 800051e: bd80 pop {r7, pc} 08000520 : /** * @brief clear bit */ void rc522_clearBit(uint8_t reg, uint8_t mask) { 8000520: b580 push {r7, lr} 8000522: b082 sub sp, #8 8000524: af00 add r7, sp, #0 8000526: 0002 movs r2, r0 8000528: 1dfb adds r3, r7, #7 800052a: 701a strb r2, [r3, #0] 800052c: 1dbb adds r3, r7, #6 800052e: 1c0a adds r2, r1, #0 8000530: 701a strb r2, [r3, #0] rc522_regWrite8(reg, rc522_regRead8(reg)&(~mask)); 8000532: 1dfb adds r3, r7, #7 8000534: 781b ldrb r3, [r3, #0] 8000536: 0018 movs r0, r3 8000538: f7ff ff74 bl 8000424 800053c: 0003 movs r3, r0 800053e: b25b sxtb r3, r3 8000540: 1dba adds r2, r7, #6 8000542: 7812 ldrb r2, [r2, #0] 8000544: b252 sxtb r2, r2 8000546: 43d2 mvns r2, r2 8000548: b252 sxtb r2, r2 800054a: 4013 ands r3, r2 800054c: b25b sxtb r3, r3 800054e: b2da uxtb r2, r3 8000550: 1dfb adds r3, r7, #7 8000552: 781b ldrb r3, [r3, #0] 8000554: 0011 movs r1, r2 8000556: 0018 movs r0, r3 8000558: f7ff ff9a bl 8000490 } 800055c: 46c0 nop @ (mov r8, r8) 800055e: 46bd mov sp, r7 8000560: b002 add sp, #8 8000562: bd80 pop {r7, pc} 08000564 : /** * @brief reset function */ void rc522_reset(void) { 8000564: b580 push {r7, lr} 8000566: af00 add r7, sp, #0 rc522_regWrite8(0x01, 0x0F); 8000568: 210f movs r1, #15 800056a: 2001 movs r0, #1 800056c: f7ff ff90 bl 8000490 } 8000570: 46c0 nop @ (mov r8, r8) 8000572: 46bd mov sp, r7 8000574: bd80 pop {r7, pc} 08000576 : /** * @brief Antenna ON */ void rc522_antennaON(void) { 8000576: b590 push {r4, r7, lr} 8000578: b083 sub sp, #12 800057a: af00 add r7, sp, #0 uint8_t temp; temp = rc522_regRead8(MFRC522_REG_TX_CONTROL); 800057c: 1dfc adds r4, r7, #7 800057e: 2014 movs r0, #20 8000580: f7ff ff50 bl 8000424 8000584: 0003 movs r3, r0 8000586: 7023 strb r3, [r4, #0] if (!(temp & 0x03)) { 8000588: 1dfb adds r3, r7, #7 800058a: 781b ldrb r3, [r3, #0] 800058c: 2203 movs r2, #3 800058e: 4013 ands r3, r2 8000590: d103 bne.n 800059a rc522_setBit(MFRC522_REG_TX_CONTROL, 0x03); 8000592: 2103 movs r1, #3 8000594: 2014 movs r0, #20 8000596: f7ff ffa5 bl 80004e4 } } 800059a: 46c0 nop @ (mov r8, r8) 800059c: 46bd mov sp, r7 800059e: b003 add sp, #12 80005a0: bd90 pop {r4, r7, pc} 080005a2 : /** * @brief Check card */ bool rc522_checkCard(uint8_t *id) { 80005a2: b5b0 push {r4, r5, r7, lr} 80005a4: b084 sub sp, #16 80005a6: af00 add r7, sp, #0 80005a8: 6078 str r0, [r7, #4] bool status=false; 80005aa: 250f movs r5, #15 80005ac: 197b adds r3, r7, r5 80005ae: 2200 movs r2, #0 80005b0: 701a strb r2, [r3, #0] //Find cards, return card type status = rc522_request(PICC_REQIDL, id); 80005b2: 197c adds r4, r7, r5 80005b4: 687b ldr r3, [r7, #4] 80005b6: 0019 movs r1, r3 80005b8: 2026 movs r0, #38 @ 0x26 80005ba: f000 f816 bl 80005ea 80005be: 0003 movs r3, r0 80005c0: 7023 strb r3, [r4, #0] if (status == true) { 80005c2: 197b adds r3, r7, r5 80005c4: 781b ldrb r3, [r3, #0] 80005c6: 2b00 cmp r3, #0 80005c8: d006 beq.n 80005d8 //Card detected //Anti-collision, return card serial number 4 bytes status = rc522_antiColl(id); 80005ca: 197c adds r4, r7, r5 80005cc: 687b ldr r3, [r7, #4] 80005ce: 0018 movs r0, r3 80005d0: f000 f998 bl 8000904 80005d4: 0003 movs r3, r0 80005d6: 7023 strb r3, [r4, #0] } rc522_halt(); //Command card into hibernation 80005d8: f000 f9e9 bl 80009ae return status; 80005dc: 230f movs r3, #15 80005de: 18fb adds r3, r7, r3 80005e0: 781b ldrb r3, [r3, #0] } 80005e2: 0018 movs r0, r3 80005e4: 46bd mov sp, r7 80005e6: b004 add sp, #16 80005e8: bdb0 pop {r4, r5, r7, pc} 080005ea : /** * @brief Request function */ bool rc522_request(uint8_t reqMode, uint8_t *tagType) { 80005ea: b5f0 push {r4, r5, r6, r7, lr} 80005ec: b087 sub sp, #28 80005ee: af02 add r7, sp, #8 80005f0: 0002 movs r2, r0 80005f2: 6039 str r1, [r7, #0] 80005f4: 1dfb adds r3, r7, #7 80005f6: 701a strb r2, [r3, #0] bool status=false; 80005f8: 250f movs r5, #15 80005fa: 197b adds r3, r7, r5 80005fc: 2200 movs r2, #0 80005fe: 701a strb r2, [r3, #0] uint16_t backBits; rc522_regWrite8(MFRC522_REG_BIT_FRAMING, 0x07); 8000600: 2107 movs r1, #7 8000602: 200d movs r0, #13 8000604: f7ff ff44 bl 8000490 tagType[0] = reqMode; 8000608: 683b ldr r3, [r7, #0] 800060a: 1dfa adds r2, r7, #7 800060c: 7812 ldrb r2, [r2, #0] 800060e: 701a strb r2, [r3, #0] status = rc522_toCard(PCD_TRANSCEIVE, tagType, 1, tagType, &backBits); 8000610: 197c adds r4, r7, r5 8000612: 683a ldr r2, [r7, #0] 8000614: 6839 ldr r1, [r7, #0] 8000616: 260c movs r6, #12 8000618: 19bb adds r3, r7, r6 800061a: 9300 str r3, [sp, #0] 800061c: 0013 movs r3, r2 800061e: 2201 movs r2, #1 8000620: 200c movs r0, #12 8000622: f000 f819 bl 8000658 8000626: 0003 movs r3, r0 8000628: 7023 strb r3, [r4, #0] if ((status != true) || (backBits != 0x10)) { 800062a: 197b adds r3, r7, r5 800062c: 781b ldrb r3, [r3, #0] 800062e: 2201 movs r2, #1 8000630: 4053 eors r3, r2 8000632: b2db uxtb r3, r3 8000634: 2b00 cmp r3, #0 8000636: d103 bne.n 8000640 8000638: 19bb adds r3, r7, r6 800063a: 881b ldrh r3, [r3, #0] 800063c: 2b10 cmp r3, #16 800063e: d003 beq.n 8000648 status = false; 8000640: 230f movs r3, #15 8000642: 18fb adds r3, r7, r3 8000644: 2200 movs r2, #0 8000646: 701a strb r2, [r3, #0] } return status; 8000648: 230f movs r3, #15 800064a: 18fb adds r3, r7, r3 800064c: 781b ldrb r3, [r3, #0] } 800064e: 0018 movs r0, r3 8000650: 46bd mov sp, r7 8000652: b005 add sp, #20 8000654: bdf0 pop {r4, r5, r6, r7, pc} ... 08000658 : uint8_t command, uint8_t* sendData, uint8_t sendLen, uint8_t* backData, uint16_t* backLen) { 8000658: b5b0 push {r4, r5, r7, lr} 800065a: b088 sub sp, #32 800065c: af00 add r7, sp, #0 800065e: 60b9 str r1, [r7, #8] 8000660: 0011 movs r1, r2 8000662: 607b str r3, [r7, #4] 8000664: 240f movs r4, #15 8000666: 193b adds r3, r7, r4 8000668: 1c02 adds r2, r0, #0 800066a: 701a strb r2, [r3, #0] 800066c: 230e movs r3, #14 800066e: 18fb adds r3, r7, r3 8000670: 1c0a adds r2, r1, #0 8000672: 701a strb r2, [r3, #0] bool status = false; 8000674: 231f movs r3, #31 8000676: 18fb adds r3, r7, r3 8000678: 2200 movs r2, #0 800067a: 701a strb r2, [r3, #0] uint8_t irqEn = 0x00; 800067c: 211e movs r1, #30 800067e: 187b adds r3, r7, r1 8000680: 2200 movs r2, #0 8000682: 701a strb r2, [r3, #0] uint8_t waitIRq = 0x00; 8000684: 201d movs r0, #29 8000686: 183b adds r3, r7, r0 8000688: 2200 movs r2, #0 800068a: 701a strb r2, [r3, #0] uint8_t lastBits; uint8_t n; uint16_t i; switch (command) { 800068c: 193b adds r3, r7, r4 800068e: 781b ldrb r3, [r3, #0] 8000690: 2b0c cmp r3, #12 8000692: d008 beq.n 80006a6 8000694: 2b0e cmp r3, #14 8000696: d10f bne.n 80006b8 case PCD_AUTHENT: { irqEn = 0x12; 8000698: 187b adds r3, r7, r1 800069a: 2212 movs r2, #18 800069c: 701a strb r2, [r3, #0] waitIRq = 0x10; 800069e: 183b adds r3, r7, r0 80006a0: 2210 movs r2, #16 80006a2: 701a strb r2, [r3, #0] break; 80006a4: e009 b.n 80006ba } case PCD_TRANSCEIVE: { irqEn = 0x77; 80006a6: 231e movs r3, #30 80006a8: 18fb adds r3, r7, r3 80006aa: 2277 movs r2, #119 @ 0x77 80006ac: 701a strb r2, [r3, #0] waitIRq = 0x30; 80006ae: 231d movs r3, #29 80006b0: 18fb adds r3, r7, r3 80006b2: 2230 movs r2, #48 @ 0x30 80006b4: 701a strb r2, [r3, #0] break; 80006b6: e000 b.n 80006ba } default: break; 80006b8: 46c0 nop @ (mov r8, r8) } rc522_regWrite8(MFRC522_REG_COMM_IE_N, irqEn | 0x80); 80006ba: 231e movs r3, #30 80006bc: 18fb adds r3, r7, r3 80006be: 781b ldrb r3, [r3, #0] 80006c0: 2280 movs r2, #128 @ 0x80 80006c2: 4252 negs r2, r2 80006c4: 4313 orrs r3, r2 80006c6: b2db uxtb r3, r3 80006c8: 0019 movs r1, r3 80006ca: 2002 movs r0, #2 80006cc: f7ff fee0 bl 8000490 rc522_clearBit(MFRC522_REG_COMM_IRQ, 0x80); 80006d0: 2180 movs r1, #128 @ 0x80 80006d2: 2004 movs r0, #4 80006d4: f7ff ff24 bl 8000520 rc522_setBit(MFRC522_REG_FIFO_LEVEL, 0x80); 80006d8: 2180 movs r1, #128 @ 0x80 80006da: 200a movs r0, #10 80006dc: f7ff ff02 bl 80004e4 rc522_regWrite8(MFRC522_REG_COMMAND, PCD_IDLE); 80006e0: 2100 movs r1, #0 80006e2: 2001 movs r0, #1 80006e4: f7ff fed4 bl 8000490 //Writing data to the FIFO for (i = 0; i < sendLen; i++) { 80006e8: 231a movs r3, #26 80006ea: 18fb adds r3, r7, r3 80006ec: 2200 movs r2, #0 80006ee: 801a strh r2, [r3, #0] 80006f0: e00e b.n 8000710 rc522_regWrite8(MFRC522_REG_FIFO_DATA, sendData[i]); 80006f2: 241a movs r4, #26 80006f4: 193b adds r3, r7, r4 80006f6: 881b ldrh r3, [r3, #0] 80006f8: 68ba ldr r2, [r7, #8] 80006fa: 18d3 adds r3, r2, r3 80006fc: 781b ldrb r3, [r3, #0] 80006fe: 0019 movs r1, r3 8000700: 2009 movs r0, #9 8000702: f7ff fec5 bl 8000490 for (i = 0; i < sendLen; i++) { 8000706: 193b adds r3, r7, r4 8000708: 881a ldrh r2, [r3, #0] 800070a: 193b adds r3, r7, r4 800070c: 3201 adds r2, #1 800070e: 801a strh r2, [r3, #0] 8000710: 230e movs r3, #14 8000712: 18fb adds r3, r7, r3 8000714: 781b ldrb r3, [r3, #0] 8000716: b29b uxth r3, r3 8000718: 221a movs r2, #26 800071a: 18ba adds r2, r7, r2 800071c: 8812 ldrh r2, [r2, #0] 800071e: 429a cmp r2, r3 8000720: d3e7 bcc.n 80006f2 } //Execute the command rc522_regWrite8(MFRC522_REG_COMMAND, command); 8000722: 240f movs r4, #15 8000724: 193b adds r3, r7, r4 8000726: 781b ldrb r3, [r3, #0] 8000728: 0019 movs r1, r3 800072a: 2001 movs r0, #1 800072c: f7ff feb0 bl 8000490 if (command == PCD_TRANSCEIVE) { 8000730: 193b adds r3, r7, r4 8000732: 781b ldrb r3, [r3, #0] 8000734: 2b0c cmp r3, #12 8000736: d103 bne.n 8000740 rc522_setBit(MFRC522_REG_BIT_FRAMING, 0x80); //StartSend=1,transmission of data starts 8000738: 2180 movs r1, #128 @ 0x80 800073a: 200d movs r0, #13 800073c: f7ff fed2 bl 80004e4 } //Waiting to receive data to complete i = 100; //i according to the clock frequency adjustment, the operator M1 card maximum waiting time 25ms??? 8000740: 231a movs r3, #26 8000742: 18fb adds r3, r7, r3 8000744: 2264 movs r2, #100 @ 0x64 8000746: 801a strh r2, [r3, #0] do { //CommIrqReg[7..0] //Set1 TxIRq RxIRq IdleIRq HiAlerIRq LoAlertIRq ErrIRq TimerIRq n = rc522_regRead8(MFRC522_REG_COMM_IRQ); 8000748: 251c movs r5, #28 800074a: 197c adds r4, r7, r5 800074c: 2004 movs r0, #4 800074e: f7ff fe69 bl 8000424 8000752: 0003 movs r3, r0 8000754: 7023 strb r3, [r4, #0] i--; 8000756: 211a movs r1, #26 8000758: 187b adds r3, r7, r1 800075a: 881a ldrh r2, [r3, #0] 800075c: 187b adds r3, r7, r1 800075e: 3a01 subs r2, #1 8000760: 801a strh r2, [r3, #0] } while ((i!=0) && !(n&0x01) && !(n&waitIRq)); 8000762: 187b adds r3, r7, r1 8000764: 881b ldrh r3, [r3, #0] 8000766: 2b00 cmp r3, #0 8000768: d00d beq.n 8000786 800076a: 197b adds r3, r7, r5 800076c: 781b ldrb r3, [r3, #0] 800076e: 2201 movs r2, #1 8000770: 4013 ands r3, r2 8000772: d108 bne.n 8000786 8000774: 197b adds r3, r7, r5 8000776: 221d movs r2, #29 8000778: 18ba adds r2, r7, r2 800077a: 781b ldrb r3, [r3, #0] 800077c: 7812 ldrb r2, [r2, #0] 800077e: 4013 ands r3, r2 8000780: b2db uxtb r3, r3 8000782: 2b00 cmp r3, #0 8000784: d0e0 beq.n 8000748 rc522_clearBit(MFRC522_REG_BIT_FRAMING, 0x80); //StartSend=0 8000786: 2180 movs r1, #128 @ 0x80 8000788: 200d movs r0, #13 800078a: f7ff fec9 bl 8000520 if (i != 0) { 800078e: 231a movs r3, #26 8000790: 18fb adds r3, r7, r3 8000792: 881b ldrh r3, [r3, #0] 8000794: 2b00 cmp r3, #0 8000796: d100 bne.n 800079a 8000798: e0a7 b.n 80008ea if (!(rc522_regRead8(MFRC522_REG_ERROR) & 0x1B)) { 800079a: 2006 movs r0, #6 800079c: f7ff fe42 bl 8000424 80007a0: 0003 movs r3, r0 80007a2: 001a movs r2, r3 80007a4: 231b movs r3, #27 80007a6: 4013 ands r3, r2 80007a8: d000 beq.n 80007ac 80007aa: e096 b.n 80008da status = true; 80007ac: 211f movs r1, #31 80007ae: 187b adds r3, r7, r1 80007b0: 2201 movs r2, #1 80007b2: 701a strb r2, [r3, #0] if (n & irqEn & 0x01) { 80007b4: 231c movs r3, #28 80007b6: 18fb adds r3, r7, r3 80007b8: 221e movs r2, #30 80007ba: 18ba adds r2, r7, r2 80007bc: 781b ldrb r3, [r3, #0] 80007be: 7812 ldrb r2, [r2, #0] 80007c0: 4013 ands r3, r2 80007c2: b2db uxtb r3, r3 80007c4: 001a movs r2, r3 80007c6: 2301 movs r3, #1 80007c8: 4013 ands r3, r2 80007ca: d002 beq.n 80007d2 status = false; 80007cc: 187b adds r3, r7, r1 80007ce: 2200 movs r2, #0 80007d0: 701a strb r2, [r3, #0] } if (command == PCD_TRANSCEIVE) { 80007d2: 230f movs r3, #15 80007d4: 18fb adds r3, r7, r3 80007d6: 781b ldrb r3, [r3, #0] 80007d8: 2b0c cmp r3, #12 80007da: d000 beq.n 80007de 80007dc: e085 b.n 80008ea n = rc522_regRead8(MFRC522_REG_FIFO_LEVEL); 80007de: 251c movs r5, #28 80007e0: 197c adds r4, r7, r5 80007e2: 200a movs r0, #10 80007e4: f7ff fe1e bl 8000424 80007e8: 0003 movs r3, r0 80007ea: 7023 strb r3, [r4, #0] uint8_t l = n; 80007ec: 2319 movs r3, #25 80007ee: 18fb adds r3, r7, r3 80007f0: 002c movs r4, r5 80007f2: 193a adds r2, r7, r4 80007f4: 7812 ldrb r2, [r2, #0] 80007f6: 701a strb r2, [r3, #0] lastBits = rc522_regRead8(MFRC522_REG_CONTROL) & 0x07; 80007f8: 200c movs r0, #12 80007fa: f7ff fe13 bl 8000424 80007fe: 0003 movs r3, r0 8000800: 0019 movs r1, r3 8000802: 2018 movs r0, #24 8000804: 183b adds r3, r7, r0 8000806: 2207 movs r2, #7 8000808: 400a ands r2, r1 800080a: 701a strb r2, [r3, #0] if (lastBits) { 800080c: 0001 movs r1, r0 800080e: 187b adds r3, r7, r1 8000810: 781b ldrb r3, [r3, #0] 8000812: 2b00 cmp r3, #0 8000814: d00d beq.n 8000832 *backLen = (n - 1) * 8 + lastBits; 8000816: 193b adds r3, r7, r4 8000818: 781b ldrb r3, [r3, #0] 800081a: 3b01 subs r3, #1 800081c: b29b uxth r3, r3 800081e: 00db lsls r3, r3, #3 8000820: b29a uxth r2, r3 8000822: 187b adds r3, r7, r1 8000824: 781b ldrb r3, [r3, #0] 8000826: b29b uxth r3, r3 8000828: 18d3 adds r3, r2, r3 800082a: b29a uxth r2, r3 800082c: 6b3b ldr r3, [r7, #48] @ 0x30 800082e: 801a strh r2, [r3, #0] 8000830: e007 b.n 8000842 } else { *backLen = n * 8; 8000832: 231c movs r3, #28 8000834: 18fb adds r3, r7, r3 8000836: 781b ldrb r3, [r3, #0] 8000838: b29b uxth r3, r3 800083a: 00db lsls r3, r3, #3 800083c: b29a uxth r2, r3 800083e: 6b3b ldr r3, [r7, #48] @ 0x30 8000840: 801a strh r2, [r3, #0] } if (n == 0) { 8000842: 221c movs r2, #28 8000844: 18bb adds r3, r7, r2 8000846: 781b ldrb r3, [r3, #0] 8000848: 2b00 cmp r3, #0 800084a: d102 bne.n 8000852 n = 1; 800084c: 18bb adds r3, r7, r2 800084e: 2201 movs r2, #1 8000850: 701a strb r2, [r3, #0] } if (n > MFRC522_MAX_LEN) { 8000852: 221c movs r2, #28 8000854: 18bb adds r3, r7, r2 8000856: 781b ldrb r3, [r3, #0] 8000858: 2b10 cmp r3, #16 800085a: d902 bls.n 8000862 n = MFRC522_MAX_LEN; 800085c: 18bb adds r3, r7, r2 800085e: 2210 movs r2, #16 8000860: 701a strb r2, [r3, #0] } //Reading the received data in FIFO for (i = 0; i < n; i++) { 8000862: 231a movs r3, #26 8000864: 18fb adds r3, r7, r3 8000866: 2200 movs r2, #0 8000868: 801a strh r2, [r3, #0] 800086a: e020 b.n 80008ae uint8_t d = rc522_regRead8(MFRC522_REG_FIFO_DATA); 800086c: 2517 movs r5, #23 800086e: 197c adds r4, r7, r5 8000870: 2009 movs r0, #9 8000872: f7ff fdd7 bl 8000424 8000876: 0003 movs r3, r0 8000878: 7023 strb r3, [r4, #0] if (l == 4) 800087a: 2319 movs r3, #25 800087c: 18fb adds r3, r7, r3 800087e: 781b ldrb r3, [r3, #0] 8000880: 2b04 cmp r3, #4 8000882: d106 bne.n 8000892 printf("%02x ", d); 8000884: 197b adds r3, r7, r5 8000886: 781a ldrb r2, [r3, #0] 8000888: 4b1b ldr r3, [pc, #108] @ (80008f8 ) 800088a: 0011 movs r1, r2 800088c: 0018 movs r0, r3 800088e: f004 fdab bl 80053e8 backData[i] = d; 8000892: 211a movs r1, #26 8000894: 187b adds r3, r7, r1 8000896: 881b ldrh r3, [r3, #0] 8000898: 687a ldr r2, [r7, #4] 800089a: 18d3 adds r3, r2, r3 800089c: 2217 movs r2, #23 800089e: 18ba adds r2, r7, r2 80008a0: 7812 ldrb r2, [r2, #0] 80008a2: 701a strb r2, [r3, #0] for (i = 0; i < n; i++) { 80008a4: 187b adds r3, r7, r1 80008a6: 881a ldrh r2, [r3, #0] 80008a8: 187b adds r3, r7, r1 80008aa: 3201 adds r2, #1 80008ac: 801a strh r2, [r3, #0] 80008ae: 231c movs r3, #28 80008b0: 18fb adds r3, r7, r3 80008b2: 781b ldrb r3, [r3, #0] 80008b4: b29b uxth r3, r3 80008b6: 221a movs r2, #26 80008b8: 18ba adds r2, r7, r2 80008ba: 8812 ldrh r2, [r2, #0] 80008bc: 429a cmp r2, r3 80008be: d3d5 bcc.n 800086c } if (l==4) 80008c0: 2319 movs r3, #25 80008c2: 18fb adds r3, r7, r3 80008c4: 781b ldrb r3, [r3, #0] 80008c6: 2b04 cmp r3, #4 80008c8: d103 bne.n 80008d2 printf("\r\n"); 80008ca: 4b0c ldr r3, [pc, #48] @ (80008fc ) 80008cc: 0018 movs r0, r3 80008ce: f004 fdf1 bl 80054b4 return status; 80008d2: 231f movs r3, #31 80008d4: 18fb adds r3, r7, r3 80008d6: 781b ldrb r3, [r3, #0] 80008d8: e00a b.n 80008f0 } } else { printf("error\r\n"); 80008da: 4b09 ldr r3, [pc, #36] @ (8000900 ) 80008dc: 0018 movs r0, r3 80008de: f004 fde9 bl 80054b4 status = false; 80008e2: 231f movs r3, #31 80008e4: 18fb adds r3, r7, r3 80008e6: 2200 movs r2, #0 80008e8: 701a strb r2, [r3, #0] } } return status; 80008ea: 231f movs r3, #31 80008ec: 18fb adds r3, r7, r3 80008ee: 781b ldrb r3, [r3, #0] } 80008f0: 0018 movs r0, r3 80008f2: 46bd mov sp, r7 80008f4: b008 add sp, #32 80008f6: bdb0 pop {r4, r5, r7, pc} 80008f8: 080061fc .word 0x080061fc 80008fc: 08006204 .word 0x08006204 8000900: 08006208 .word 0x08006208 08000904 : bool rc522_antiColl(uint8_t* serNum) { 8000904: b5b0 push {r4, r5, r7, lr} 8000906: b086 sub sp, #24 8000908: af02 add r7, sp, #8 800090a: 6078 str r0, [r7, #4] bool status; uint8_t i; uint8_t serNumCheck = 0; 800090c: 230d movs r3, #13 800090e: 18fb adds r3, r7, r3 8000910: 2200 movs r2, #0 8000912: 701a strb r2, [r3, #0] uint16_t unLen; //for (i = 0; i < 4; i++) // printf("Anticoll In %d: 0x%02x\r\n", i, serNum[i]); rc522_regWrite8(MFRC522_REG_BIT_FRAMING, 0x00); //TxLastBists = BitFramingReg[2..0] 8000914: 2100 movs r1, #0 8000916: 200d movs r0, #13 8000918: f7ff fdba bl 8000490 serNum[0] = PICC_ANTICOLL; 800091c: 687b ldr r3, [r7, #4] 800091e: 2293 movs r2, #147 @ 0x93 8000920: 701a strb r2, [r3, #0] serNum[1] = 0x20; 8000922: 687b ldr r3, [r7, #4] 8000924: 3301 adds r3, #1 8000926: 2220 movs r2, #32 8000928: 701a strb r2, [r3, #0] status = rc522_toCard(PCD_TRANSCEIVE, serNum, 2, serNum, &unLen); 800092a: 250f movs r5, #15 800092c: 197c adds r4, r7, r5 800092e: 687a ldr r2, [r7, #4] 8000930: 6879 ldr r1, [r7, #4] 8000932: 230a movs r3, #10 8000934: 18fb adds r3, r7, r3 8000936: 9300 str r3, [sp, #0] 8000938: 0013 movs r3, r2 800093a: 2202 movs r2, #2 800093c: 200c movs r0, #12 800093e: f7ff fe8b bl 8000658 8000942: 0003 movs r3, r0 8000944: 7023 strb r3, [r4, #0] //for (i = 0; i < 4; i++) // printf("Anticoll ToCard %d: 0x%02x\r\n", i, serNum[i]); if (status == true) { 8000946: 197b adds r3, r7, r5 8000948: 781b ldrb r3, [r3, #0] 800094a: 2b00 cmp r3, #0 800094c: d028 beq.n 80009a0 //Check card serial number for (i = 0; i < 4; i++) { 800094e: 230e movs r3, #14 8000950: 18fb adds r3, r7, r3 8000952: 2200 movs r2, #0 8000954: 701a strb r2, [r3, #0] 8000956: e010 b.n 800097a serNumCheck ^= serNum[i]; 8000958: 200e movs r0, #14 800095a: 183b adds r3, r7, r0 800095c: 781b ldrb r3, [r3, #0] 800095e: 687a ldr r2, [r7, #4] 8000960: 18d3 adds r3, r2, r3 8000962: 7819 ldrb r1, [r3, #0] 8000964: 220d movs r2, #13 8000966: 18bb adds r3, r7, r2 8000968: 18ba adds r2, r7, r2 800096a: 7812 ldrb r2, [r2, #0] 800096c: 404a eors r2, r1 800096e: 701a strb r2, [r3, #0] for (i = 0; i < 4; i++) { 8000970: 183b adds r3, r7, r0 8000972: 781a ldrb r2, [r3, #0] 8000974: 183b adds r3, r7, r0 8000976: 3201 adds r2, #1 8000978: 701a strb r2, [r3, #0] 800097a: 220e movs r2, #14 800097c: 18bb adds r3, r7, r2 800097e: 781b ldrb r3, [r3, #0] 8000980: 2b03 cmp r3, #3 8000982: d9e9 bls.n 8000958 } if (serNumCheck != serNum[i]) { 8000984: 18bb adds r3, r7, r2 8000986: 781b ldrb r3, [r3, #0] 8000988: 687a ldr r2, [r7, #4] 800098a: 18d3 adds r3, r2, r3 800098c: 781b ldrb r3, [r3, #0] 800098e: 220d movs r2, #13 8000990: 18ba adds r2, r7, r2 8000992: 7812 ldrb r2, [r2, #0] 8000994: 429a cmp r2, r3 8000996: d003 beq.n 80009a0 status = false; 8000998: 230f movs r3, #15 800099a: 18fb adds r3, r7, r3 800099c: 2200 movs r2, #0 800099e: 701a strb r2, [r3, #0] } } return status; 80009a0: 230f movs r3, #15 80009a2: 18fb adds r3, r7, r3 80009a4: 781b ldrb r3, [r3, #0] } 80009a6: 0018 movs r0, r3 80009a8: 46bd mov sp, r7 80009aa: b004 add sp, #16 80009ac: bdb0 pop {r4, r5, r7, pc} 080009ae : void rc522_halt(void) { 80009ae: b580 push {r7, lr} 80009b0: b084 sub sp, #16 80009b2: af02 add r7, sp, #8 uint16_t unLen; uint8_t buff[4]; buff[0] = PICC_HALT; 80009b4: 003b movs r3, r7 80009b6: 2250 movs r2, #80 @ 0x50 80009b8: 701a strb r2, [r3, #0] buff[1] = 0; 80009ba: 003b movs r3, r7 80009bc: 2200 movs r2, #0 80009be: 705a strb r2, [r3, #1] rc522_calculateCRC(buff, 2, &buff[2]); 80009c0: 003b movs r3, r7 80009c2: 1c9a adds r2, r3, #2 80009c4: 003b movs r3, r7 80009c6: 2102 movs r1, #2 80009c8: 0018 movs r0, r3 80009ca: f000 f80d bl 80009e8 rc522_toCard(PCD_TRANSCEIVE, buff, 4, buff, &unLen); 80009ce: 003a movs r2, r7 80009d0: 0039 movs r1, r7 80009d2: 1dbb adds r3, r7, #6 80009d4: 9300 str r3, [sp, #0] 80009d6: 0013 movs r3, r2 80009d8: 2204 movs r2, #4 80009da: 200c movs r0, #12 80009dc: f7ff fe3c bl 8000658 } 80009e0: 46c0 nop @ (mov r8, r8) 80009e2: 46bd mov sp, r7 80009e4: b002 add sp, #8 80009e6: bd80 pop {r7, pc} 080009e8 : void rc522_calculateCRC(uint8_t* pIndata, uint8_t len, uint8_t* pOutData) { 80009e8: b5b0 push {r4, r5, r7, lr} 80009ea: b086 sub sp, #24 80009ec: af00 add r7, sp, #0 80009ee: 60f8 str r0, [r7, #12] 80009f0: 607a str r2, [r7, #4] 80009f2: 230b movs r3, #11 80009f4: 18fb adds r3, r7, r3 80009f6: 1c0a adds r2, r1, #0 80009f8: 701a strb r2, [r3, #0] uint8_t i, n; rc522_clearBit(MFRC522_REG_DIV_IRQ, 0x04); //CRCIrq = 0 80009fa: 2104 movs r1, #4 80009fc: 2005 movs r0, #5 80009fe: f7ff fd8f bl 8000520 rc522_setBit(MFRC522_REG_FIFO_LEVEL, 0x80); //Clear the FIFO pointer 8000a02: 2180 movs r1, #128 @ 0x80 8000a04: 200a movs r0, #10 8000a06: f7ff fd6d bl 80004e4 //Write_MFRC522(CommandReg, PCD_IDLE); //Writing data to the FIFO for (i = 0; i < len; i++) { 8000a0a: 2317 movs r3, #23 8000a0c: 18fb adds r3, r7, r3 8000a0e: 2200 movs r2, #0 8000a10: 701a strb r2, [r3, #0] 8000a12: e00e b.n 8000a32 rc522_regWrite8(MFRC522_REG_FIFO_DATA, *(pIndata+i)); 8000a14: 2417 movs r4, #23 8000a16: 193b adds r3, r7, r4 8000a18: 781b ldrb r3, [r3, #0] 8000a1a: 68fa ldr r2, [r7, #12] 8000a1c: 18d3 adds r3, r2, r3 8000a1e: 781b ldrb r3, [r3, #0] 8000a20: 0019 movs r1, r3 8000a22: 2009 movs r0, #9 8000a24: f7ff fd34 bl 8000490 for (i = 0; i < len; i++) { 8000a28: 193b adds r3, r7, r4 8000a2a: 781a ldrb r2, [r3, #0] 8000a2c: 193b adds r3, r7, r4 8000a2e: 3201 adds r2, #1 8000a30: 701a strb r2, [r3, #0] 8000a32: 2417 movs r4, #23 8000a34: 193a adds r2, r7, r4 8000a36: 230b movs r3, #11 8000a38: 18fb adds r3, r7, r3 8000a3a: 7812 ldrb r2, [r2, #0] 8000a3c: 781b ldrb r3, [r3, #0] 8000a3e: 429a cmp r2, r3 8000a40: d3e8 bcc.n 8000a14 } rc522_regWrite8(MFRC522_REG_COMMAND, PCD_CALCCRC); 8000a42: 2103 movs r1, #3 8000a44: 2001 movs r0, #1 8000a46: f7ff fd23 bl 8000490 //Wait CRC calculation is complete i = 0xFF; 8000a4a: 193b adds r3, r7, r4 8000a4c: 22ff movs r2, #255 @ 0xff 8000a4e: 701a strb r2, [r3, #0] do { n = rc522_regRead8(MFRC522_REG_DIV_IRQ); 8000a50: 2516 movs r5, #22 8000a52: 197c adds r4, r7, r5 8000a54: 2005 movs r0, #5 8000a56: f7ff fce5 bl 8000424 8000a5a: 0003 movs r3, r0 8000a5c: 7023 strb r3, [r4, #0] i--; 8000a5e: 2117 movs r1, #23 8000a60: 187b adds r3, r7, r1 8000a62: 781a ldrb r2, [r3, #0] 8000a64: 187b adds r3, r7, r1 8000a66: 3a01 subs r2, #1 8000a68: 701a strb r2, [r3, #0] } while ((i!=0) && !(n&0x04)); //CRCIrq = 1 8000a6a: 187b adds r3, r7, r1 8000a6c: 781b ldrb r3, [r3, #0] 8000a6e: 2b00 cmp r3, #0 8000a70: d004 beq.n 8000a7c 8000a72: 197b adds r3, r7, r5 8000a74: 781b ldrb r3, [r3, #0] 8000a76: 2204 movs r2, #4 8000a78: 4013 ands r3, r2 8000a7a: d0e9 beq.n 8000a50 //Read CRC calculation result pOutData[0] = rc522_regRead8(MFRC522_REG_CRC_RESULT_L); 8000a7c: 2022 movs r0, #34 @ 0x22 8000a7e: f7ff fcd1 bl 8000424 8000a82: 0003 movs r3, r0 8000a84: 001a movs r2, r3 8000a86: 687b ldr r3, [r7, #4] 8000a88: 701a strb r2, [r3, #0] pOutData[1] = rc522_regRead8(MFRC522_REG_CRC_RESULT_M); 8000a8a: 687b ldr r3, [r7, #4] 8000a8c: 1c5c adds r4, r3, #1 8000a8e: 2021 movs r0, #33 @ 0x21 8000a90: f7ff fcc8 bl 8000424 8000a94: 0003 movs r3, r0 8000a96: 7023 strb r3, [r4, #0] } 8000a98: 46c0 nop @ (mov r8, r8) 8000a9a: 46bd mov sp, r7 8000a9c: b006 add sp, #24 8000a9e: bdb0 pop {r4, r5, r7, pc} 08000aa0 : } return true; } void rc522_init(void) { 8000aa0: b580 push {r7, lr} 8000aa2: af00 add r7, sp, #0 * SPI -> SPI * PA8 ->RST * PB0 ->CS * */ HAL_GPIO_WritePin(RFID_RST_GPIO_Port, RFID_RST_Pin, 0); 8000aa4: 4b15 ldr r3, [pc, #84] @ (8000afc ) 8000aa6: 2200 movs r2, #0 8000aa8: 2104 movs r1, #4 8000aaa: 0018 movs r0, r3 8000aac: f001 f8da bl 8001c64 HAL_GPIO_WritePin(RFID_RST_GPIO_Port, RFID_RST_Pin, 1); 8000ab0: 4b12 ldr r3, [pc, #72] @ (8000afc ) 8000ab2: 2201 movs r2, #1 8000ab4: 2104 movs r1, #4 8000ab6: 0018 movs r0, r3 8000ab8: f001 f8d4 bl 8001c64 rc522_reset(); 8000abc: f7ff fd52 bl 8000564 rc522_regWrite8(MFRC522_REG_T_MODE, 0x80); 8000ac0: 2180 movs r1, #128 @ 0x80 8000ac2: 202a movs r0, #42 @ 0x2a 8000ac4: f7ff fce4 bl 8000490 rc522_regWrite8(MFRC522_REG_T_PRESCALER, 0xA9); 8000ac8: 21a9 movs r1, #169 @ 0xa9 8000aca: 202b movs r0, #43 @ 0x2b 8000acc: f7ff fce0 bl 8000490 rc522_regWrite8(MFRC522_REG_T_RELOAD_L, 0xE8); 8000ad0: 21e8 movs r1, #232 @ 0xe8 8000ad2: 202d movs r0, #45 @ 0x2d 8000ad4: f7ff fcdc bl 8000490 rc522_regWrite8(MFRC522_REG_T_RELOAD_H, 0x03); 8000ad8: 2103 movs r1, #3 8000ada: 202c movs r0, #44 @ 0x2c 8000adc: f7ff fcd8 bl 8000490 rc522_regWrite8(MFRC522_REG_TX_AUTO, 0x40); 8000ae0: 2140 movs r1, #64 @ 0x40 8000ae2: 2015 movs r0, #21 8000ae4: f7ff fcd4 bl 8000490 rc522_regWrite8(MFRC522_REG_MODE, 0x3D); 8000ae8: 213d movs r1, #61 @ 0x3d 8000aea: 2011 movs r0, #17 8000aec: f7ff fcd0 bl 8000490 rc522_antennaON(); //Open the antenna 8000af0: f7ff fd41 bl 8000576 } 8000af4: 46c0 nop @ (mov r8, r8) 8000af6: 46bd mov sp, r7 8000af8: bd80 pop {r7, pc} 8000afa: 46c0 nop @ (mov r8, r8) 8000afc: 50000400 .word 0x50000400 08000b00
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000b00: b590 push {r4, r7, lr} 8000b02: b085 sub sp, #20 8000b04: af02 add r7, sp, #8 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000b06: f000 fd35 bl 8001574 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000b0a: f000 f835 bl 8000b78 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000b0e: f000 f941 bl 8000d94 MX_I2C1_Init(); 8000b12: f000 f873 bl 8000bfc MX_SPI1_Init(); 8000b16: f000 f8b1 bl 8000c7c MX_USART2_UART_Init(); 8000b1a: f000 f8ed bl 8000cf8 /* USER CODE BEGIN 2 */ init_keypad(); 8000b1e: f000 faa9 bl 8001074 init_buttons(); 8000b22: f000 fac9 bl 80010b8 rc522_init(); 8000b26: f7ff ffbb bl 8000aa0 printf("Hello, world!\r\n"); 8000b2a: 4b11 ldr r3, [pc, #68] @ (8000b70 ) 8000b2c: 0018 movs r0, r3 8000b2e: f004 fcc1 bl 80054b4 /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ uint8_t rfid_id[4] = {0}; 8000b32: 1d3b adds r3, r7, #4 8000b34: 2200 movs r2, #0 8000b36: 601a str r2, [r3, #0] while (1) { HAL_Delay(500); 8000b38: 23fa movs r3, #250 @ 0xfa 8000b3a: 005b lsls r3, r3, #1 8000b3c: 0018 movs r0, r3 8000b3e: f000 fd9f bl 8001680 // printf("s: %d\r\n", keypad_state); // printf("r: %d\r\n", recv_cnt); // printf("d: %d %d %d %d, %d %d %d %d\r\n", data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]); // HAL_I2C_Slave_Receive_IT(&hi2c1, (uint8_t*)&data, 8); if(rc522_checkCard(rfid_id)) { 8000b42: 1d3b adds r3, r7, #4 8000b44: 0018 movs r0, r3 8000b46: f7ff fd2c bl 80005a2 8000b4a: 1e03 subs r3, r0, #0 8000b4c: d0f4 beq.n 8000b38 printf("0x%x 0x%x 0x%x 0x%x\r\n", rfid_id[0], rfid_id[1], rfid_id[2], rfid_id[3]); 8000b4e: 1d3b adds r3, r7, #4 8000b50: 781b ldrb r3, [r3, #0] 8000b52: 0019 movs r1, r3 8000b54: 1d3b adds r3, r7, #4 8000b56: 785b ldrb r3, [r3, #1] 8000b58: 001a movs r2, r3 8000b5a: 1d3b adds r3, r7, #4 8000b5c: 789b ldrb r3, [r3, #2] 8000b5e: 001c movs r4, r3 8000b60: 1d3b adds r3, r7, #4 8000b62: 78db ldrb r3, [r3, #3] 8000b64: 4803 ldr r0, [pc, #12] @ (8000b74 ) 8000b66: 9300 str r3, [sp, #0] 8000b68: 0023 movs r3, r4 8000b6a: f004 fc3d bl 80053e8 HAL_Delay(500); 8000b6e: e7e3 b.n 8000b38 8000b70: 08006218 .word 0x08006218 8000b74: 08006228 .word 0x08006228 08000b78 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000b78: b590 push {r4, r7, lr} 8000b7a: b093 sub sp, #76 @ 0x4c 8000b7c: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000b7e: 2414 movs r4, #20 8000b80: 193b adds r3, r7, r4 8000b82: 0018 movs r0, r3 8000b84: 2334 movs r3, #52 @ 0x34 8000b86: 001a movs r2, r3 8000b88: 2100 movs r1, #0 8000b8a: f004 fd89 bl 80056a0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000b8e: 1d3b adds r3, r7, #4 8000b90: 0018 movs r0, r3 8000b92: 2310 movs r3, #16 8000b94: 001a movs r2, r3 8000b96: 2100 movs r1, #0 8000b98: f004 fd82 bl 80056a0 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8000b9c: 2380 movs r3, #128 @ 0x80 8000b9e: 009b lsls r3, r3, #2 8000ba0: 0018 movs r0, r3 8000ba2: f002 f817 bl 8002bd4 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000ba6: 193b adds r3, r7, r4 8000ba8: 2201 movs r2, #1 8000baa: 601a str r2, [r3, #0] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000bac: 193b adds r3, r7, r4 8000bae: 2280 movs r2, #128 @ 0x80 8000bb0: 0252 lsls r2, r2, #9 8000bb2: 605a str r2, [r3, #4] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000bb4: 193b adds r3, r7, r4 8000bb6: 2200 movs r2, #0 8000bb8: 61da str r2, [r3, #28] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000bba: 193b adds r3, r7, r4 8000bbc: 0018 movs r0, r3 8000bbe: f002 f855 bl 8002c6c 8000bc2: 1e03 subs r3, r0, #0 8000bc4: d001 beq.n 8000bca { Error_Handler(); 8000bc6: f000 fa95 bl 80010f4 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000bca: 1d3b adds r3, r7, #4 8000bcc: 2207 movs r2, #7 8000bce: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; 8000bd0: 1d3b adds r3, r7, #4 8000bd2: 2201 movs r2, #1 8000bd4: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000bd6: 1d3b adds r3, r7, #4 8000bd8: 2200 movs r2, #0 8000bda: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8000bdc: 1d3b adds r3, r7, #4 8000bde: 2200 movs r2, #0 8000be0: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8000be2: 1d3b adds r3, r7, #4 8000be4: 2100 movs r1, #0 8000be6: 0018 movs r0, r3 8000be8: f002 fb50 bl 800328c 8000bec: 1e03 subs r3, r0, #0 8000bee: d001 beq.n 8000bf4 { Error_Handler(); 8000bf0: f000 fa80 bl 80010f4 } } 8000bf4: 46c0 nop @ (mov r8, r8) 8000bf6: 46bd mov sp, r7 8000bf8: b013 add sp, #76 @ 0x4c 8000bfa: bd90 pop {r4, r7, pc} 08000bfc : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 8000bfc: b580 push {r7, lr} 8000bfe: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 8000c00: 4b1b ldr r3, [pc, #108] @ (8000c70 ) 8000c02: 4a1c ldr r2, [pc, #112] @ (8000c74 ) 8000c04: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x2000090E; 8000c06: 4b1a ldr r3, [pc, #104] @ (8000c70 ) 8000c08: 4a1b ldr r2, [pc, #108] @ (8000c78 ) 8000c0a: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 252; 8000c0c: 4b18 ldr r3, [pc, #96] @ (8000c70 ) 8000c0e: 22fc movs r2, #252 @ 0xfc 8000c10: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000c12: 4b17 ldr r3, [pc, #92] @ (8000c70 ) 8000c14: 2201 movs r2, #1 8000c16: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000c18: 4b15 ldr r3, [pc, #84] @ (8000c70 ) 8000c1a: 2200 movs r2, #0 8000c1c: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 8000c1e: 4b14 ldr r3, [pc, #80] @ (8000c70 ) 8000c20: 2200 movs r2, #0 8000c22: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 8000c24: 4b12 ldr r3, [pc, #72] @ (8000c70 ) 8000c26: 2200 movs r2, #0 8000c28: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000c2a: 4b11 ldr r3, [pc, #68] @ (8000c70 ) 8000c2c: 2200 movs r2, #0 8000c2e: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000c30: 4b0f ldr r3, [pc, #60] @ (8000c70 ) 8000c32: 2200 movs r2, #0 8000c34: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 8000c36: 4b0e ldr r3, [pc, #56] @ (8000c70 ) 8000c38: 0018 movs r0, r3 8000c3a: f001 f831 bl 8001ca0 8000c3e: 1e03 subs r3, r0, #0 8000c40: d001 beq.n 8000c46 { Error_Handler(); 8000c42: f000 fa57 bl 80010f4 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000c46: 4b0a ldr r3, [pc, #40] @ (8000c70 ) 8000c48: 2100 movs r1, #0 8000c4a: 0018 movs r0, r3 8000c4c: f001 ff2a bl 8002aa4 8000c50: 1e03 subs r3, r0, #0 8000c52: d001 beq.n 8000c58 { Error_Handler(); 8000c54: f000 fa4e bl 80010f4 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8000c58: 4b05 ldr r3, [pc, #20] @ (8000c70 ) 8000c5a: 2100 movs r1, #0 8000c5c: 0018 movs r0, r3 8000c5e: f001 ff6d bl 8002b3c 8000c62: 1e03 subs r3, r0, #0 8000c64: d001 beq.n 8000c6a { Error_Handler(); 8000c66: f000 fa45 bl 80010f4 } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 8000c6a: 46c0 nop @ (mov r8, r8) 8000c6c: 46bd mov sp, r7 8000c6e: bd80 pop {r7, pc} 8000c70: 20000084 .word 0x20000084 8000c74: 40005400 .word 0x40005400 8000c78: 2000090e .word 0x2000090e 08000c7c : * @brief SPI1 Initialization Function * @param None * @retval None */ static void MX_SPI1_Init(void) { 8000c7c: b580 push {r7, lr} 8000c7e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI1_Init 1 */ /* USER CODE END SPI1_Init 1 */ /* SPI1 parameter configuration*/ hspi1.Instance = SPI1; 8000c80: 4b1b ldr r3, [pc, #108] @ (8000cf0 ) 8000c82: 4a1c ldr r2, [pc, #112] @ (8000cf4 ) 8000c84: 601a str r2, [r3, #0] hspi1.Init.Mode = SPI_MODE_MASTER; 8000c86: 4b1a ldr r3, [pc, #104] @ (8000cf0 ) 8000c88: 2282 movs r2, #130 @ 0x82 8000c8a: 0052 lsls r2, r2, #1 8000c8c: 605a str r2, [r3, #4] hspi1.Init.Direction = SPI_DIRECTION_2LINES; 8000c8e: 4b18 ldr r3, [pc, #96] @ (8000cf0 ) 8000c90: 2200 movs r2, #0 8000c92: 609a str r2, [r3, #8] hspi1.Init.DataSize = SPI_DATASIZE_8BIT; 8000c94: 4b16 ldr r3, [pc, #88] @ (8000cf0 ) 8000c96: 22e0 movs r2, #224 @ 0xe0 8000c98: 00d2 lsls r2, r2, #3 8000c9a: 60da str r2, [r3, #12] hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 8000c9c: 4b14 ldr r3, [pc, #80] @ (8000cf0 ) 8000c9e: 2200 movs r2, #0 8000ca0: 611a str r2, [r3, #16] hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 8000ca2: 4b13 ldr r3, [pc, #76] @ (8000cf0 ) 8000ca4: 2200 movs r2, #0 8000ca6: 615a str r2, [r3, #20] hspi1.Init.NSS = SPI_NSS_SOFT; 8000ca8: 4b11 ldr r3, [pc, #68] @ (8000cf0 ) 8000caa: 2280 movs r2, #128 @ 0x80 8000cac: 0092 lsls r2, r2, #2 8000cae: 619a str r2, [r3, #24] hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 8000cb0: 4b0f ldr r3, [pc, #60] @ (8000cf0 ) 8000cb2: 2200 movs r2, #0 8000cb4: 61da str r2, [r3, #28] hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000cb6: 4b0e ldr r3, [pc, #56] @ (8000cf0 ) 8000cb8: 2200 movs r2, #0 8000cba: 621a str r2, [r3, #32] hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 8000cbc: 4b0c ldr r3, [pc, #48] @ (8000cf0 ) 8000cbe: 2200 movs r2, #0 8000cc0: 625a str r2, [r3, #36] @ 0x24 hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000cc2: 4b0b ldr r3, [pc, #44] @ (8000cf0 ) 8000cc4: 2200 movs r2, #0 8000cc6: 629a str r2, [r3, #40] @ 0x28 hspi1.Init.CRCPolynomial = 7; 8000cc8: 4b09 ldr r3, [pc, #36] @ (8000cf0 ) 8000cca: 2207 movs r2, #7 8000ccc: 62da str r2, [r3, #44] @ 0x2c hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; 8000cce: 4b08 ldr r3, [pc, #32] @ (8000cf0 ) 8000cd0: 2200 movs r2, #0 8000cd2: 631a str r2, [r3, #48] @ 0x30 hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 8000cd4: 4b06 ldr r3, [pc, #24] @ (8000cf0 ) 8000cd6: 2208 movs r2, #8 8000cd8: 635a str r2, [r3, #52] @ 0x34 if (HAL_SPI_Init(&hspi1) != HAL_OK) 8000cda: 4b05 ldr r3, [pc, #20] @ (8000cf0 ) 8000cdc: 0018 movs r0, r3 8000cde: f002 fdb3 bl 8003848 8000ce2: 1e03 subs r3, r0, #0 8000ce4: d001 beq.n 8000cea { Error_Handler(); 8000ce6: f000 fa05 bl 80010f4 } /* USER CODE BEGIN SPI1_Init 2 */ /* USER CODE END SPI1_Init 2 */ } 8000cea: 46c0 nop @ (mov r8, r8) 8000cec: 46bd mov sp, r7 8000cee: bd80 pop {r7, pc} 8000cf0: 200000d8 .word 0x200000d8 8000cf4: 40013000 .word 0x40013000 08000cf8 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 8000cf8: b580 push {r7, lr} 8000cfa: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000cfc: 4b23 ldr r3, [pc, #140] @ (8000d8c ) 8000cfe: 4a24 ldr r2, [pc, #144] @ (8000d90 ) 8000d00: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8000d02: 4b22 ldr r3, [pc, #136] @ (8000d8c ) 8000d04: 22e1 movs r2, #225 @ 0xe1 8000d06: 0252 lsls r2, r2, #9 8000d08: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8000d0a: 4b20 ldr r3, [pc, #128] @ (8000d8c ) 8000d0c: 2200 movs r2, #0 8000d0e: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000d10: 4b1e ldr r3, [pc, #120] @ (8000d8c ) 8000d12: 2200 movs r2, #0 8000d14: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8000d16: 4b1d ldr r3, [pc, #116] @ (8000d8c ) 8000d18: 2200 movs r2, #0 8000d1a: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000d1c: 4b1b ldr r3, [pc, #108] @ (8000d8c ) 8000d1e: 220c movs r2, #12 8000d20: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000d22: 4b1a ldr r3, [pc, #104] @ (8000d8c ) 8000d24: 2200 movs r2, #0 8000d26: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8000d28: 4b18 ldr r3, [pc, #96] @ (8000d8c ) 8000d2a: 2200 movs r2, #0 8000d2c: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000d2e: 4b17 ldr r3, [pc, #92] @ (8000d8c ) 8000d30: 2200 movs r2, #0 8000d32: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000d34: 4b15 ldr r3, [pc, #84] @ (8000d8c ) 8000d36: 2200 movs r2, #0 8000d38: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000d3a: 4b14 ldr r3, [pc, #80] @ (8000d8c ) 8000d3c: 2200 movs r2, #0 8000d3e: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8000d40: 4b12 ldr r3, [pc, #72] @ (8000d8c ) 8000d42: 0018 movs r0, r3 8000d44: f003 fca0 bl 8004688 8000d48: 1e03 subs r3, r0, #0 8000d4a: d001 beq.n 8000d50 { Error_Handler(); 8000d4c: f000 f9d2 bl 80010f4 } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d50: 4b0e ldr r3, [pc, #56] @ (8000d8c ) 8000d52: 2100 movs r1, #0 8000d54: 0018 movs r0, r3 8000d56: f004 f9a3 bl 80050a0 8000d5a: 1e03 subs r3, r0, #0 8000d5c: d001 beq.n 8000d62 { Error_Handler(); 8000d5e: f000 f9c9 bl 80010f4 } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d62: 4b0a ldr r3, [pc, #40] @ (8000d8c ) 8000d64: 2100 movs r1, #0 8000d66: 0018 movs r0, r3 8000d68: f004 f9da bl 8005120 8000d6c: 1e03 subs r3, r0, #0 8000d6e: d001 beq.n 8000d74 { Error_Handler(); 8000d70: f000 f9c0 bl 80010f4 } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 8000d74: 4b05 ldr r3, [pc, #20] @ (8000d8c ) 8000d76: 0018 movs r0, r3 8000d78: f004 f958 bl 800502c 8000d7c: 1e03 subs r3, r0, #0 8000d7e: d001 beq.n 8000d84 { Error_Handler(); 8000d80: f000 f9b8 bl 80010f4 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 8000d84: 46c0 nop @ (mov r8, r8) 8000d86: 46bd mov sp, r7 8000d88: bd80 pop {r7, pc} 8000d8a: 46c0 nop @ (mov r8, r8) 8000d8c: 2000013c .word 0x2000013c 8000d90: 40004400 .word 0x40004400 08000d94 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000d94: b590 push {r4, r7, lr} 8000d96: b08b sub sp, #44 @ 0x2c 8000d98: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000d9a: 2414 movs r4, #20 8000d9c: 193b adds r3, r7, r4 8000d9e: 0018 movs r0, r3 8000da0: 2314 movs r3, #20 8000da2: 001a movs r2, r3 8000da4: 2100 movs r1, #0 8000da6: f004 fc7b bl 80056a0 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 8000daa: 4b9b ldr r3, [pc, #620] @ (8001018 ) 8000dac: 6b5a ldr r2, [r3, #52] @ 0x34 8000dae: 4b9a ldr r3, [pc, #616] @ (8001018 ) 8000db0: 2120 movs r1, #32 8000db2: 430a orrs r2, r1 8000db4: 635a str r2, [r3, #52] @ 0x34 8000db6: 4b98 ldr r3, [pc, #608] @ (8001018 ) 8000db8: 6b5b ldr r3, [r3, #52] @ 0x34 8000dba: 2220 movs r2, #32 8000dbc: 4013 ands r3, r2 8000dbe: 613b str r3, [r7, #16] 8000dc0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000dc2: 4b95 ldr r3, [pc, #596] @ (8001018 ) 8000dc4: 6b5a ldr r2, [r3, #52] @ 0x34 8000dc6: 4b94 ldr r3, [pc, #592] @ (8001018 ) 8000dc8: 2101 movs r1, #1 8000dca: 430a orrs r2, r1 8000dcc: 635a str r2, [r3, #52] @ 0x34 8000dce: 4b92 ldr r3, [pc, #584] @ (8001018 ) 8000dd0: 6b5b ldr r3, [r3, #52] @ 0x34 8000dd2: 2201 movs r2, #1 8000dd4: 4013 ands r3, r2 8000dd6: 60fb str r3, [r7, #12] 8000dd8: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000dda: 4b8f ldr r3, [pc, #572] @ (8001018 ) 8000ddc: 6b5a ldr r2, [r3, #52] @ 0x34 8000dde: 4b8e ldr r3, [pc, #568] @ (8001018 ) 8000de0: 2102 movs r1, #2 8000de2: 430a orrs r2, r1 8000de4: 635a str r2, [r3, #52] @ 0x34 8000de6: 4b8c ldr r3, [pc, #560] @ (8001018 ) 8000de8: 6b5b ldr r3, [r3, #52] @ 0x34 8000dea: 2202 movs r2, #2 8000dec: 4013 ands r3, r2 8000dee: 60bb str r3, [r7, #8] 8000df0: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000df2: 4b89 ldr r3, [pc, #548] @ (8001018 ) 8000df4: 6b5a ldr r2, [r3, #52] @ 0x34 8000df6: 4b88 ldr r3, [pc, #544] @ (8001018 ) 8000df8: 2104 movs r1, #4 8000dfa: 430a orrs r2, r1 8000dfc: 635a str r2, [r3, #52] @ 0x34 8000dfe: 4b86 ldr r3, [pc, #536] @ (8001018 ) 8000e00: 6b5b ldr r3, [r3, #52] @ 0x34 8000e02: 2204 movs r2, #4 8000e04: 4013 ands r3, r2 8000e06: 607b str r3, [r7, #4] 8000e08: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000e0a: 4b83 ldr r3, [pc, #524] @ (8001018 ) 8000e0c: 6b5a ldr r2, [r3, #52] @ 0x34 8000e0e: 4b82 ldr r3, [pc, #520] @ (8001018 ) 8000e10: 2108 movs r1, #8 8000e12: 430a orrs r2, r1 8000e14: 635a str r2, [r3, #52] @ 0x34 8000e16: 4b80 ldr r3, [pc, #512] @ (8001018 ) 8000e18: 6b5b ldr r3, [r3, #52] @ 0x34 8000e1a: 2208 movs r2, #8 8000e1c: 4013 ands r3, r2 8000e1e: 603b str r3, [r7, #0] 8000e20: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RFID_CS_GPIO_Port, RFID_CS_Pin, GPIO_PIN_RESET); 8000e22: 23a0 movs r3, #160 @ 0xa0 8000e24: 05db lsls r3, r3, #23 8000e26: 2200 movs r2, #0 8000e28: 2110 movs r1, #16 8000e2a: 0018 movs r0, r3 8000e2c: f000 ff1a bl 8001c64 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(RFID_RST_GPIO_Port, RFID_RST_Pin, GPIO_PIN_RESET); 8000e30: 4b7a ldr r3, [pc, #488] @ (800101c ) 8000e32: 2200 movs r2, #0 8000e34: 2104 movs r1, #4 8000e36: 0018 movs r0, r3 8000e38: f000 ff14 bl 8001c64 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, COL1_Pin|KP_C2_Pin|KP_C3_Pin|KP_C4_Pin, GPIO_PIN_SET); 8000e3c: 4978 ldr r1, [pc, #480] @ (8001020 ) 8000e3e: 4b77 ldr r3, [pc, #476] @ (800101c ) 8000e40: 2201 movs r2, #1 8000e42: 0018 movs r0, r3 8000e44: f000 ff0e bl 8001c64 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(COL2_GPIO_Port, COL2_Pin, GPIO_PIN_SET); 8000e48: 2380 movs r3, #128 @ 0x80 8000e4a: 0059 lsls r1, r3, #1 8000e4c: 23a0 movs r3, #160 @ 0xa0 8000e4e: 05db lsls r3, r3, #23 8000e50: 2201 movs r2, #1 8000e52: 0018 movs r0, r3 8000e54: f000 ff06 bl 8001c64 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, COL3_Pin|KP_C1_Pin, GPIO_PIN_SET); 8000e58: 4b72 ldr r3, [pc, #456] @ (8001024 ) 8000e5a: 2201 movs r2, #1 8000e5c: 210a movs r1, #10 8000e5e: 0018 movs r0, r3 8000e60: f000 ff00 bl 8001c64 /*Configure GPIO pin : INT_Pin */ GPIO_InitStruct.Pin = INT_Pin; 8000e64: 193b adds r3, r7, r4 8000e66: 2202 movs r2, #2 8000e68: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000e6a: 193b adds r3, r7, r4 8000e6c: 2202 movs r2, #2 8000e6e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e70: 193b adds r3, r7, r4 8000e72: 2200 movs r2, #0 8000e74: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000e76: 193b adds r3, r7, r4 8000e78: 2200 movs r2, #0 8000e7a: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF7_EVENTOUT; 8000e7c: 193b adds r3, r7, r4 8000e7e: 2207 movs r2, #7 8000e80: 611a str r2, [r3, #16] HAL_GPIO_Init(INT_GPIO_Port, &GPIO_InitStruct); 8000e82: 193a adds r2, r7, r4 8000e84: 23a0 movs r3, #160 @ 0xa0 8000e86: 05db lsls r3, r3, #23 8000e88: 0011 movs r1, r2 8000e8a: 0018 movs r0, r3 8000e8c: f000 fd86 bl 800199c /*Configure GPIO pin : RFID_CS_Pin */ GPIO_InitStruct.Pin = RFID_CS_Pin; 8000e90: 193b adds r3, r7, r4 8000e92: 2210 movs r2, #16 8000e94: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000e96: 193b adds r3, r7, r4 8000e98: 2201 movs r2, #1 8000e9a: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000e9c: 193b adds r3, r7, r4 8000e9e: 2200 movs r2, #0 8000ea0: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ea2: 193b adds r3, r7, r4 8000ea4: 2200 movs r2, #0 8000ea6: 60da str r2, [r3, #12] HAL_GPIO_Init(RFID_CS_GPIO_Port, &GPIO_InitStruct); 8000ea8: 193a adds r2, r7, r4 8000eaa: 23a0 movs r3, #160 @ 0xa0 8000eac: 05db lsls r3, r3, #23 8000eae: 0011 movs r1, r2 8000eb0: 0018 movs r0, r3 8000eb2: f000 fd73 bl 800199c /*Configure GPIO pins : HALL_Pin CLOSE_Pin */ GPIO_InitStruct.Pin = HALL_Pin|CLOSE_Pin; 8000eb6: 193b adds r3, r7, r4 8000eb8: 2203 movs r2, #3 8000eba: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8000ebc: 193b adds r3, r7, r4 8000ebe: 2203 movs r2, #3 8000ec0: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000ec2: 193b adds r3, r7, r4 8000ec4: 2200 movs r2, #0 8000ec6: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000ec8: 193b adds r3, r7, r4 8000eca: 4a54 ldr r2, [pc, #336] @ (800101c ) 8000ecc: 0019 movs r1, r3 8000ece: 0010 movs r0, r2 8000ed0: f000 fd64 bl 800199c /*Configure GPIO pin : RFID_RST_Pin */ GPIO_InitStruct.Pin = RFID_RST_Pin; 8000ed4: 193b adds r3, r7, r4 8000ed6: 2204 movs r2, #4 8000ed8: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000eda: 193b adds r3, r7, r4 8000edc: 2201 movs r2, #1 8000ede: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000ee0: 193b adds r3, r7, r4 8000ee2: 2200 movs r2, #0 8000ee4: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ee6: 193b adds r3, r7, r4 8000ee8: 2200 movs r2, #0 8000eea: 60da str r2, [r3, #12] HAL_GPIO_Init(RFID_RST_GPIO_Port, &GPIO_InitStruct); 8000eec: 193b adds r3, r7, r4 8000eee: 4a4b ldr r2, [pc, #300] @ (800101c ) 8000ef0: 0019 movs r1, r3 8000ef2: 0010 movs r0, r2 8000ef4: f000 fd52 bl 800199c /*Configure GPIO pins : SWT1_Pin SWT2_Pin */ GPIO_InitStruct.Pin = SWT1_Pin|SWT2_Pin; 8000ef8: 0021 movs r1, r4 8000efa: 187b adds r3, r7, r1 8000efc: 22c0 movs r2, #192 @ 0xc0 8000efe: 0112 lsls r2, r2, #4 8000f00: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000f02: 000c movs r4, r1 8000f04: 193b adds r3, r7, r4 8000f06: 2200 movs r2, #0 8000f08: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f0a: 193b adds r3, r7, r4 8000f0c: 2200 movs r2, #0 8000f0e: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f10: 193b adds r3, r7, r4 8000f12: 4a42 ldr r2, [pc, #264] @ (800101c ) 8000f14: 0019 movs r1, r3 8000f16: 0010 movs r0, r2 8000f18: f000 fd40 bl 800199c /*Configure GPIO pins : COL1_Pin KP_C2_Pin KP_C3_Pin KP_C4_Pin */ GPIO_InitStruct.Pin = COL1_Pin|KP_C2_Pin|KP_C3_Pin|KP_C4_Pin; 8000f1c: 193b adds r3, r7, r4 8000f1e: 4a40 ldr r2, [pc, #256] @ (8001020 ) 8000f20: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 8000f22: 193b adds r3, r7, r4 8000f24: 2211 movs r2, #17 8000f26: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f28: 193b adds r3, r7, r4 8000f2a: 2200 movs r2, #0 8000f2c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f2e: 193b adds r3, r7, r4 8000f30: 2200 movs r2, #0 8000f32: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000f34: 193b adds r3, r7, r4 8000f36: 4a39 ldr r2, [pc, #228] @ (800101c ) 8000f38: 0019 movs r1, r3 8000f3a: 0010 movs r0, r2 8000f3c: f000 fd2e bl 800199c /*Configure GPIO pin : COL2_Pin */ GPIO_InitStruct.Pin = COL2_Pin; 8000f40: 0021 movs r1, r4 8000f42: 187b adds r3, r7, r1 8000f44: 2280 movs r2, #128 @ 0x80 8000f46: 0052 lsls r2, r2, #1 8000f48: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 8000f4a: 000c movs r4, r1 8000f4c: 193b adds r3, r7, r4 8000f4e: 2211 movs r2, #17 8000f50: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f52: 193b adds r3, r7, r4 8000f54: 2200 movs r2, #0 8000f56: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f58: 193b adds r3, r7, r4 8000f5a: 2200 movs r2, #0 8000f5c: 60da str r2, [r3, #12] HAL_GPIO_Init(COL2_GPIO_Port, &GPIO_InitStruct); 8000f5e: 193a adds r2, r7, r4 8000f60: 23a0 movs r3, #160 @ 0xa0 8000f62: 05db lsls r3, r3, #23 8000f64: 0011 movs r1, r2 8000f66: 0018 movs r0, r3 8000f68: f000 fd18 bl 800199c /*Configure GPIO pins : SWT3_Pin SWT4_Pin */ GPIO_InitStruct.Pin = SWT3_Pin|SWT4_Pin; 8000f6c: 193b adds r3, r7, r4 8000f6e: 22c0 movs r2, #192 @ 0xc0 8000f70: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000f72: 193b adds r3, r7, r4 8000f74: 2200 movs r2, #0 8000f76: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f78: 193b adds r3, r7, r4 8000f7a: 2200 movs r2, #0 8000f7c: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000f7e: 193b adds r3, r7, r4 8000f80: 4a29 ldr r2, [pc, #164] @ (8001028 ) 8000f82: 0019 movs r1, r3 8000f84: 0010 movs r0, r2 8000f86: f000 fd09 bl 800199c /*Configure GPIO pins : ROW1_Pin ROW2_Pin ROW3_Pin */ GPIO_InitStruct.Pin = ROW1_Pin|ROW2_Pin|ROW3_Pin; 8000f8a: 193b adds r3, r7, r4 8000f8c: 2298 movs r2, #152 @ 0x98 8000f8e: 0212 lsls r2, r2, #8 8000f90: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000f92: 193b adds r3, r7, r4 8000f94: 2200 movs r2, #0 8000f96: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000f98: 193b adds r3, r7, r4 8000f9a: 2201 movs r2, #1 8000f9c: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000f9e: 193a adds r2, r7, r4 8000fa0: 23a0 movs r3, #160 @ 0xa0 8000fa2: 05db lsls r3, r3, #23 8000fa4: 0011 movs r1, r2 8000fa6: 0018 movs r0, r3 8000fa8: f000 fcf8 bl 800199c /*Configure GPIO pins : ROW4_Pin TOUCH_Pin */ GPIO_InitStruct.Pin = ROW4_Pin|TOUCH_Pin; 8000fac: 193b adds r3, r7, r4 8000fae: 2205 movs r2, #5 8000fb0: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000fb2: 193b adds r3, r7, r4 8000fb4: 2200 movs r2, #0 8000fb6: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fb8: 193b adds r3, r7, r4 8000fba: 2200 movs r2, #0 8000fbc: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000fbe: 193b adds r3, r7, r4 8000fc0: 4a18 ldr r2, [pc, #96] @ (8001024 ) 8000fc2: 0019 movs r1, r3 8000fc4: 0010 movs r0, r2 8000fc6: f000 fce9 bl 800199c /*Configure GPIO pins : COL3_Pin KP_C1_Pin */ GPIO_InitStruct.Pin = COL3_Pin|KP_C1_Pin; 8000fca: 193b adds r3, r7, r4 8000fcc: 220a movs r2, #10 8000fce: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; 8000fd0: 193b adds r3, r7, r4 8000fd2: 2211 movs r2, #17 8000fd4: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000fd6: 193b adds r3, r7, r4 8000fd8: 2200 movs r2, #0 8000fda: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000fdc: 193b adds r3, r7, r4 8000fde: 2200 movs r2, #0 8000fe0: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000fe2: 193b adds r3, r7, r4 8000fe4: 4a0f ldr r2, [pc, #60] @ (8001024 ) 8000fe6: 0019 movs r1, r3 8000fe8: 0010 movs r0, r2 8000fea: f000 fcd7 bl 800199c /*Configure GPIO pins : KP_R1_Pin KP_R2_Pin KP_R3_Pin KP_R4_Pin */ GPIO_InitStruct.Pin = KP_R1_Pin|KP_R2_Pin|KP_R3_Pin|KP_R4_Pin; 8000fee: 0021 movs r1, r4 8000ff0: 187b adds r3, r7, r1 8000ff2: 22f0 movs r2, #240 @ 0xf0 8000ff4: 0092 lsls r2, r2, #2 8000ff6: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000ff8: 187b adds r3, r7, r1 8000ffa: 2200 movs r2, #0 8000ffc: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000ffe: 187b adds r3, r7, r1 8001000: 2201 movs r2, #1 8001002: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001004: 187b adds r3, r7, r1 8001006: 4a05 ldr r2, [pc, #20] @ (800101c ) 8001008: 0019 movs r1, r3 800100a: 0010 movs r0, r2 800100c: f000 fcc6 bl 800199c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001010: 46c0 nop @ (mov r8, r8) 8001012: 46bd mov sp, r7 8001014: b00b add sp, #44 @ 0x2c 8001016: bd90 pop {r4, r7, pc} 8001018: 40021000 .word 0x40021000 800101c: 50000400 .word 0x50000400 8001020: 00008038 .word 0x00008038 8001024: 50000c00 .word 0x50000c00 8001028: 50000800 .word 0x50000800 0800102c <__io_putchar>: /* USER CODE BEGIN 4 */ PUTCHAR_PROTOTYPE { 800102c: b580 push {r7, lr} 800102e: b082 sub sp, #8 8001030: af00 add r7, sp, #0 8001032: 6078 str r0, [r7, #4] /* Place your implementation of fputc here */ /* e.g. write a character to the USART1 and Loop until the end of transmission */ HAL_UART_Transmit(&huart2, (uint8_t *)&ch, 1, 0xFFFF); 8001034: 4b05 ldr r3, [pc, #20] @ (800104c <__io_putchar+0x20>) 8001036: 1d39 adds r1, r7, #4 8001038: 4805 ldr r0, [pc, #20] @ (8001050 <__io_putchar+0x24>) 800103a: 2201 movs r2, #1 800103c: f003 fb7a bl 8004734 return ch; 8001040: 687b ldr r3, [r7, #4] } 8001042: 0018 movs r0, r3 8001044: 46bd mov sp, r7 8001046: b002 add sp, #8 8001048: bd80 pop {r7, pc} 800104a: 46c0 nop @ (mov r8, r8) 800104c: 0000ffff .word 0x0000ffff 8001050: 2000013c .word 0x2000013c 08001054 : void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef* hi2c) { 8001054: b580 push {r7, lr} 8001056: b082 sub sp, #8 8001058: af00 add r7, sp, #0 800105a: 6078 str r0, [r7, #4] recv_cnt += 1; 800105c: 4b04 ldr r3, [pc, #16] @ (8001070 ) 800105e: 881b ldrh r3, [r3, #0] 8001060: 3301 adds r3, #1 8001062: b29a uxth r2, r3 8001064: 4b02 ldr r3, [pc, #8] @ (8001070 ) 8001066: 801a strh r2, [r3, #0] } 8001068: 46c0 nop @ (mov r8, r8) 800106a: 46bd mov sp, r7 800106c: b002 add sp, #8 800106e: bd80 pop {r7, pc} 8001070: 200001d0 .word 0x200001d0 08001074 : void init_keypad(void) { 8001074: b580 push {r7, lr} 8001076: af00 add r7, sp, #0 HAL_GPIO_WritePin(KP_C1_GPIO_Port, KP_C1_Pin, GPIO_PIN_SET); 8001078: 4b0d ldr r3, [pc, #52] @ (80010b0 ) 800107a: 2201 movs r2, #1 800107c: 2108 movs r1, #8 800107e: 0018 movs r0, r3 8001080: f000 fdf0 bl 8001c64 HAL_GPIO_WritePin(KP_C2_GPIO_Port, KP_C2_Pin, GPIO_PIN_SET); 8001084: 4b0b ldr r3, [pc, #44] @ (80010b4 ) 8001086: 2201 movs r2, #1 8001088: 2108 movs r1, #8 800108a: 0018 movs r0, r3 800108c: f000 fdea bl 8001c64 HAL_GPIO_WritePin(KP_C3_GPIO_Port, KP_C3_Pin, GPIO_PIN_SET); 8001090: 4b08 ldr r3, [pc, #32] @ (80010b4 ) 8001092: 2201 movs r2, #1 8001094: 2110 movs r1, #16 8001096: 0018 movs r0, r3 8001098: f000 fde4 bl 8001c64 HAL_GPIO_WritePin(KP_C4_GPIO_Port, KP_C4_Pin, GPIO_PIN_SET); 800109c: 4b05 ldr r3, [pc, #20] @ (80010b4 ) 800109e: 2201 movs r2, #1 80010a0: 2120 movs r1, #32 80010a2: 0018 movs r0, r3 80010a4: f000 fdde bl 8001c64 } 80010a8: 46c0 nop @ (mov r8, r8) 80010aa: 46bd mov sp, r7 80010ac: bd80 pop {r7, pc} 80010ae: 46c0 nop @ (mov r8, r8) 80010b0: 50000c00 .word 0x50000c00 80010b4: 50000400 .word 0x50000400 080010b8 : void init_buttons(void) { 80010b8: b580 push {r7, lr} 80010ba: af00 add r7, sp, #0 HAL_GPIO_WritePin(COL1_GPIO_Port, COL1_Pin, GPIO_PIN_SET); 80010bc: 2380 movs r3, #128 @ 0x80 80010be: 021b lsls r3, r3, #8 80010c0: 480a ldr r0, [pc, #40] @ (80010ec ) 80010c2: 2201 movs r2, #1 80010c4: 0019 movs r1, r3 80010c6: f000 fdcd bl 8001c64 HAL_GPIO_WritePin(COL2_GPIO_Port, COL2_Pin, GPIO_PIN_SET); 80010ca: 2380 movs r3, #128 @ 0x80 80010cc: 0059 lsls r1, r3, #1 80010ce: 23a0 movs r3, #160 @ 0xa0 80010d0: 05db lsls r3, r3, #23 80010d2: 2201 movs r2, #1 80010d4: 0018 movs r0, r3 80010d6: f000 fdc5 bl 8001c64 HAL_GPIO_WritePin(COL3_GPIO_Port, COL3_Pin, GPIO_PIN_SET); 80010da: 4b05 ldr r3, [pc, #20] @ (80010f0 ) 80010dc: 2201 movs r2, #1 80010de: 2102 movs r1, #2 80010e0: 0018 movs r0, r3 80010e2: f000 fdbf bl 8001c64 } 80010e6: 46c0 nop @ (mov r8, r8) 80010e8: 46bd mov sp, r7 80010ea: bd80 pop {r7, pc} 80010ec: 50000400 .word 0x50000400 80010f0: 50000c00 .word 0x50000c00 080010f4 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80010f4: b580 push {r7, lr} 80010f6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80010f8: b672 cpsid i } 80010fa: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80010fc: 46c0 nop @ (mov r8, r8) 80010fe: e7fd b.n 80010fc 08001100 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001100: b580 push {r7, lr} 8001102: b082 sub sp, #8 8001104: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001106: 4b11 ldr r3, [pc, #68] @ (800114c ) 8001108: 6c1a ldr r2, [r3, #64] @ 0x40 800110a: 4b10 ldr r3, [pc, #64] @ (800114c ) 800110c: 2101 movs r1, #1 800110e: 430a orrs r2, r1 8001110: 641a str r2, [r3, #64] @ 0x40 8001112: 4b0e ldr r3, [pc, #56] @ (800114c ) 8001114: 6c1b ldr r3, [r3, #64] @ 0x40 8001116: 2201 movs r2, #1 8001118: 4013 ands r3, r2 800111a: 607b str r3, [r7, #4] 800111c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800111e: 4b0b ldr r3, [pc, #44] @ (800114c ) 8001120: 6bda ldr r2, [r3, #60] @ 0x3c 8001122: 4b0a ldr r3, [pc, #40] @ (800114c ) 8001124: 2180 movs r1, #128 @ 0x80 8001126: 0549 lsls r1, r1, #21 8001128: 430a orrs r2, r1 800112a: 63da str r2, [r3, #60] @ 0x3c 800112c: 4b07 ldr r3, [pc, #28] @ (800114c ) 800112e: 6bda ldr r2, [r3, #60] @ 0x3c 8001130: 2380 movs r3, #128 @ 0x80 8001132: 055b lsls r3, r3, #21 8001134: 4013 ands r3, r2 8001136: 603b str r3, [r7, #0] 8001138: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); 800113a: 23c0 movs r3, #192 @ 0xc0 800113c: 00db lsls r3, r3, #3 800113e: 0018 movs r0, r3 8001140: f000 fac2 bl 80016c8 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001144: 46c0 nop @ (mov r8, r8) 8001146: 46bd mov sp, r7 8001148: b002 add sp, #8 800114a: bd80 pop {r7, pc} 800114c: 40021000 .word 0x40021000 08001150 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8001150: b590 push {r4, r7, lr} 8001152: b091 sub sp, #68 @ 0x44 8001154: af00 add r7, sp, #0 8001156: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001158: 232c movs r3, #44 @ 0x2c 800115a: 18fb adds r3, r7, r3 800115c: 0018 movs r0, r3 800115e: 2314 movs r3, #20 8001160: 001a movs r2, r3 8001162: 2100 movs r1, #0 8001164: f004 fa9c bl 80056a0 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8001168: 2410 movs r4, #16 800116a: 193b adds r3, r7, r4 800116c: 0018 movs r0, r3 800116e: 231c movs r3, #28 8001170: 001a movs r2, r3 8001172: 2100 movs r1, #0 8001174: f004 fa94 bl 80056a0 if(hi2c->Instance==I2C1) 8001178: 687b ldr r3, [r7, #4] 800117a: 681b ldr r3, [r3, #0] 800117c: 4a27 ldr r2, [pc, #156] @ (800121c ) 800117e: 4293 cmp r3, r2 8001180: d147 bne.n 8001212 /* USER CODE END I2C1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 8001182: 193b adds r3, r7, r4 8001184: 2220 movs r2, #32 8001186: 601a str r2, [r3, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; 8001188: 193b adds r3, r7, r4 800118a: 2200 movs r2, #0 800118c: 60da str r2, [r3, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 800118e: 193b adds r3, r7, r4 8001190: 0018 movs r0, r3 8001192: f002 fa25 bl 80035e0 8001196: 1e03 subs r3, r0, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f7ff ffab bl 80010f4 } __HAL_RCC_GPIOA_CLK_ENABLE(); 800119e: 4b20 ldr r3, [pc, #128] @ (8001220 ) 80011a0: 6b5a ldr r2, [r3, #52] @ 0x34 80011a2: 4b1f ldr r3, [pc, #124] @ (8001220 ) 80011a4: 2101 movs r1, #1 80011a6: 430a orrs r2, r1 80011a8: 635a str r2, [r3, #52] @ 0x34 80011aa: 4b1d ldr r3, [pc, #116] @ (8001220 ) 80011ac: 6b5b ldr r3, [r3, #52] @ 0x34 80011ae: 2201 movs r2, #1 80011b0: 4013 ands r3, r2 80011b2: 60fb str r3, [r7, #12] 80011b4: 68fb ldr r3, [r7, #12] /**I2C1 GPIO Configuration PA9 ------> I2C1_SCL PA10 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; 80011b6: 212c movs r1, #44 @ 0x2c 80011b8: 187b adds r3, r7, r1 80011ba: 22c0 movs r2, #192 @ 0xc0 80011bc: 00d2 lsls r2, r2, #3 80011be: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 80011c0: 187b adds r3, r7, r1 80011c2: 2212 movs r2, #18 80011c4: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011c6: 187b adds r3, r7, r1 80011c8: 2200 movs r2, #0 80011ca: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80011cc: 187b adds r3, r7, r1 80011ce: 2200 movs r2, #0 80011d0: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF6_I2C1; 80011d2: 187b adds r3, r7, r1 80011d4: 2206 movs r2, #6 80011d6: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80011d8: 187a adds r2, r7, r1 80011da: 23a0 movs r3, #160 @ 0xa0 80011dc: 05db lsls r3, r3, #23 80011de: 0011 movs r1, r2 80011e0: 0018 movs r0, r3 80011e2: f000 fbdb bl 800199c /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 80011e6: 4b0e ldr r3, [pc, #56] @ (8001220 ) 80011e8: 6bda ldr r2, [r3, #60] @ 0x3c 80011ea: 4b0d ldr r3, [pc, #52] @ (8001220 ) 80011ec: 2180 movs r1, #128 @ 0x80 80011ee: 0389 lsls r1, r1, #14 80011f0: 430a orrs r2, r1 80011f2: 63da str r2, [r3, #60] @ 0x3c 80011f4: 4b0a ldr r3, [pc, #40] @ (8001220 ) 80011f6: 6bda ldr r2, [r3, #60] @ 0x3c 80011f8: 2380 movs r3, #128 @ 0x80 80011fa: 039b lsls r3, r3, #14 80011fc: 4013 ands r3, r2 80011fe: 60bb str r3, [r7, #8] 8001200: 68bb ldr r3, [r7, #8] /* I2C1 interrupt Init */ HAL_NVIC_SetPriority(I2C1_IRQn, 0, 0); 8001202: 2200 movs r2, #0 8001204: 2100 movs r1, #0 8001206: 2017 movs r0, #23 8001208: f000 fb20 bl 800184c HAL_NVIC_EnableIRQ(I2C1_IRQn); 800120c: 2017 movs r0, #23 800120e: f000 fb32 bl 8001876 /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8001212: 46c0 nop @ (mov r8, r8) 8001214: 46bd mov sp, r7 8001216: b011 add sp, #68 @ 0x44 8001218: bd90 pop {r4, r7, pc} 800121a: 46c0 nop @ (mov r8, r8) 800121c: 40005400 .word 0x40005400 8001220: 40021000 .word 0x40021000 08001224 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8001224: b590 push {r4, r7, lr} 8001226: b08b sub sp, #44 @ 0x2c 8001228: af00 add r7, sp, #0 800122a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800122c: 2414 movs r4, #20 800122e: 193b adds r3, r7, r4 8001230: 0018 movs r0, r3 8001232: 2314 movs r3, #20 8001234: 001a movs r2, r3 8001236: 2100 movs r1, #0 8001238: f004 fa32 bl 80056a0 if(hspi->Instance==SPI1) 800123c: 687b ldr r3, [r7, #4] 800123e: 681b ldr r3, [r3, #0] 8001240: 4a1b ldr r2, [pc, #108] @ (80012b0 ) 8001242: 4293 cmp r3, r2 8001244: d130 bne.n 80012a8 { /* USER CODE BEGIN SPI1_MspInit 0 */ /* USER CODE END SPI1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI1_CLK_ENABLE(); 8001246: 4b1b ldr r3, [pc, #108] @ (80012b4 ) 8001248: 6c1a ldr r2, [r3, #64] @ 0x40 800124a: 4b1a ldr r3, [pc, #104] @ (80012b4 ) 800124c: 2180 movs r1, #128 @ 0x80 800124e: 0149 lsls r1, r1, #5 8001250: 430a orrs r2, r1 8001252: 641a str r2, [r3, #64] @ 0x40 8001254: 4b17 ldr r3, [pc, #92] @ (80012b4 ) 8001256: 6c1a ldr r2, [r3, #64] @ 0x40 8001258: 2380 movs r3, #128 @ 0x80 800125a: 015b lsls r3, r3, #5 800125c: 4013 ands r3, r2 800125e: 613b str r3, [r7, #16] 8001260: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001262: 4b14 ldr r3, [pc, #80] @ (80012b4 ) 8001264: 6b5a ldr r2, [r3, #52] @ 0x34 8001266: 4b13 ldr r3, [pc, #76] @ (80012b4 ) 8001268: 2101 movs r1, #1 800126a: 430a orrs r2, r1 800126c: 635a str r2, [r3, #52] @ 0x34 800126e: 4b11 ldr r3, [pc, #68] @ (80012b4 ) 8001270: 6b5b ldr r3, [r3, #52] @ 0x34 8001272: 2201 movs r2, #1 8001274: 4013 ands r3, r2 8001276: 60fb str r3, [r7, #12] 8001278: 68fb ldr r3, [r7, #12] /**SPI1 GPIO Configuration PA5 ------> SPI1_SCK PA6 ------> SPI1_MISO PA7 ------> SPI1_MOSI */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 800127a: 0021 movs r1, r4 800127c: 187b adds r3, r7, r1 800127e: 22e0 movs r2, #224 @ 0xe0 8001280: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001282: 187b adds r3, r7, r1 8001284: 2202 movs r2, #2 8001286: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001288: 187b adds r3, r7, r1 800128a: 2200 movs r2, #0 800128c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800128e: 187b adds r3, r7, r1 8001290: 2200 movs r2, #0 8001292: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_SPI1; 8001294: 187b adds r3, r7, r1 8001296: 2200 movs r2, #0 8001298: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800129a: 187a adds r2, r7, r1 800129c: 23a0 movs r3, #160 @ 0xa0 800129e: 05db lsls r3, r3, #23 80012a0: 0011 movs r1, r2 80012a2: 0018 movs r0, r3 80012a4: f000 fb7a bl 800199c /* USER CODE BEGIN SPI1_MspInit 1 */ /* USER CODE END SPI1_MspInit 1 */ } } 80012a8: 46c0 nop @ (mov r8, r8) 80012aa: 46bd mov sp, r7 80012ac: b00b add sp, #44 @ 0x2c 80012ae: bd90 pop {r4, r7, pc} 80012b0: 40013000 .word 0x40013000 80012b4: 40021000 .word 0x40021000 080012b8 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80012b8: b590 push {r4, r7, lr} 80012ba: b091 sub sp, #68 @ 0x44 80012bc: af00 add r7, sp, #0 80012be: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80012c0: 232c movs r3, #44 @ 0x2c 80012c2: 18fb adds r3, r7, r3 80012c4: 0018 movs r0, r3 80012c6: 2314 movs r3, #20 80012c8: 001a movs r2, r3 80012ca: 2100 movs r1, #0 80012cc: f004 f9e8 bl 80056a0 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 80012d0: 2410 movs r4, #16 80012d2: 193b adds r3, r7, r4 80012d4: 0018 movs r0, r3 80012d6: 231c movs r3, #28 80012d8: 001a movs r2, r3 80012da: 2100 movs r1, #0 80012dc: f004 f9e0 bl 80056a0 if(huart->Instance==USART2) 80012e0: 687b ldr r3, [r7, #4] 80012e2: 681b ldr r3, [r3, #0] 80012e4: 4a22 ldr r2, [pc, #136] @ (8001370 ) 80012e6: 4293 cmp r3, r2 80012e8: d13e bne.n 8001368 /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; 80012ea: 193b adds r3, r7, r4 80012ec: 2202 movs r2, #2 80012ee: 601a str r2, [r3, #0] PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; 80012f0: 193b adds r3, r7, r4 80012f2: 2200 movs r2, #0 80012f4: 609a str r2, [r3, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 80012f6: 193b adds r3, r7, r4 80012f8: 0018 movs r0, r3 80012fa: f002 f971 bl 80035e0 80012fe: 1e03 subs r3, r0, #0 8001300: d001 beq.n 8001306 { Error_Handler(); 8001302: f7ff fef7 bl 80010f4 } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8001306: 4b1b ldr r3, [pc, #108] @ (8001374 ) 8001308: 6bda ldr r2, [r3, #60] @ 0x3c 800130a: 4b1a ldr r3, [pc, #104] @ (8001374 ) 800130c: 2180 movs r1, #128 @ 0x80 800130e: 0289 lsls r1, r1, #10 8001310: 430a orrs r2, r1 8001312: 63da str r2, [r3, #60] @ 0x3c 8001314: 4b17 ldr r3, [pc, #92] @ (8001374 ) 8001316: 6bda ldr r2, [r3, #60] @ 0x3c 8001318: 2380 movs r3, #128 @ 0x80 800131a: 029b lsls r3, r3, #10 800131c: 4013 ands r3, r2 800131e: 60fb str r3, [r7, #12] 8001320: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001322: 4b14 ldr r3, [pc, #80] @ (8001374 ) 8001324: 6b5a ldr r2, [r3, #52] @ 0x34 8001326: 4b13 ldr r3, [pc, #76] @ (8001374 ) 8001328: 2101 movs r1, #1 800132a: 430a orrs r2, r1 800132c: 635a str r2, [r3, #52] @ 0x34 800132e: 4b11 ldr r3, [pc, #68] @ (8001374 ) 8001330: 6b5b ldr r3, [r3, #52] @ 0x34 8001332: 2201 movs r2, #1 8001334: 4013 ands r3, r2 8001336: 60bb str r3, [r7, #8] 8001338: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; 800133a: 212c movs r1, #44 @ 0x2c 800133c: 187b adds r3, r7, r1 800133e: 220c movs r2, #12 8001340: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001342: 187b adds r3, r7, r1 8001344: 2202 movs r2, #2 8001346: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001348: 187b adds r3, r7, r1 800134a: 2200 movs r2, #0 800134c: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800134e: 187b adds r3, r7, r1 8001350: 2200 movs r2, #0 8001352: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; 8001354: 187b adds r3, r7, r1 8001356: 2201 movs r2, #1 8001358: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800135a: 187a adds r2, r7, r1 800135c: 23a0 movs r3, #160 @ 0xa0 800135e: 05db lsls r3, r3, #23 8001360: 0011 movs r1, r2 8001362: 0018 movs r0, r3 8001364: f000 fb1a bl 800199c /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8001368: 46c0 nop @ (mov r8, r8) 800136a: 46bd mov sp, r7 800136c: b011 add sp, #68 @ 0x44 800136e: bd90 pop {r4, r7, pc} 8001370: 40004400 .word 0x40004400 8001374: 40021000 .word 0x40021000 08001378 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001378: b580 push {r7, lr} 800137a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800137c: 46c0 nop @ (mov r8, r8) 800137e: e7fd b.n 800137c 08001380 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001380: b580 push {r7, lr} 8001382: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001384: 46c0 nop @ (mov r8, r8) 8001386: e7fd b.n 8001384 08001388 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001388: b580 push {r7, lr} 800138a: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 800138c: 46c0 nop @ (mov r8, r8) 800138e: 46bd mov sp, r7 8001390: bd80 pop {r7, pc} 08001392 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001392: b580 push {r7, lr} 8001394: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001396: 46c0 nop @ (mov r8, r8) 8001398: 46bd mov sp, r7 800139a: bd80 pop {r7, pc} 0800139c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 800139c: b580 push {r7, lr} 800139e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 80013a0: f000 f952 bl 8001648 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 80013a4: 46c0 nop @ (mov r8, r8) 80013a6: 46bd mov sp, r7 80013a8: bd80 pop {r7, pc} ... 080013ac : /** * @brief This function handles I2C1 event global interrupt / I2C1 wake-up interrupt through EXTI line 23. */ void I2C1_IRQHandler(void) { 80013ac: b580 push {r7, lr} 80013ae: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_IRQn 0 */ /* USER CODE END I2C1_IRQn 0 */ if (hi2c1.Instance->ISR & (I2C_FLAG_BERR | I2C_FLAG_ARLO | I2C_FLAG_OVR)) { 80013b0: 4b09 ldr r3, [pc, #36] @ (80013d8 ) 80013b2: 681b ldr r3, [r3, #0] 80013b4: 699a ldr r2, [r3, #24] 80013b6: 23e0 movs r3, #224 @ 0xe0 80013b8: 00db lsls r3, r3, #3 80013ba: 4013 ands r3, r2 80013bc: d004 beq.n 80013c8 HAL_I2C_ER_IRQHandler(&hi2c1); 80013be: 4b06 ldr r3, [pc, #24] @ (80013d8 ) 80013c0: 0018 movs r0, r3 80013c2: f000 fd2d bl 8001e20 HAL_I2C_EV_IRQHandler(&hi2c1); } /* USER CODE BEGIN I2C1_IRQn 1 */ /* USER CODE END I2C1_IRQn 1 */ } 80013c6: e003 b.n 80013d0 HAL_I2C_EV_IRQHandler(&hi2c1); 80013c8: 4b03 ldr r3, [pc, #12] @ (80013d8 ) 80013ca: 0018 movs r0, r3 80013cc: f000 fd0e bl 8001dec } 80013d0: 46c0 nop @ (mov r8, r8) 80013d2: 46bd mov sp, r7 80013d4: bd80 pop {r7, pc} 80013d6: 46c0 nop @ (mov r8, r8) 80013d8: 20000084 .word 0x20000084 080013dc <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80013dc: b580 push {r7, lr} 80013de: b086 sub sp, #24 80013e0: af00 add r7, sp, #0 80013e2: 60f8 str r0, [r7, #12] 80013e4: 60b9 str r1, [r7, #8] 80013e6: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80013e8: 2300 movs r3, #0 80013ea: 617b str r3, [r7, #20] 80013ec: e00a b.n 8001404 <_read+0x28> { *ptr++ = __io_getchar(); 80013ee: e000 b.n 80013f2 <_read+0x16> 80013f0: bf00 nop 80013f2: 0001 movs r1, r0 80013f4: 68bb ldr r3, [r7, #8] 80013f6: 1c5a adds r2, r3, #1 80013f8: 60ba str r2, [r7, #8] 80013fa: b2ca uxtb r2, r1 80013fc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 80013fe: 697b ldr r3, [r7, #20] 8001400: 3301 adds r3, #1 8001402: 617b str r3, [r7, #20] 8001404: 697a ldr r2, [r7, #20] 8001406: 687b ldr r3, [r7, #4] 8001408: 429a cmp r2, r3 800140a: dbf0 blt.n 80013ee <_read+0x12> } return len; 800140c: 687b ldr r3, [r7, #4] } 800140e: 0018 movs r0, r3 8001410: 46bd mov sp, r7 8001412: b006 add sp, #24 8001414: bd80 pop {r7, pc} 08001416 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8001416: b580 push {r7, lr} 8001418: b086 sub sp, #24 800141a: af00 add r7, sp, #0 800141c: 60f8 str r0, [r7, #12] 800141e: 60b9 str r1, [r7, #8] 8001420: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001422: 2300 movs r3, #0 8001424: 617b str r3, [r7, #20] 8001426: e009 b.n 800143c <_write+0x26> { __io_putchar(*ptr++); 8001428: 68bb ldr r3, [r7, #8] 800142a: 1c5a adds r2, r3, #1 800142c: 60ba str r2, [r7, #8] 800142e: 781b ldrb r3, [r3, #0] 8001430: 0018 movs r0, r3 8001432: f7ff fdfb bl 800102c <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 8001436: 697b ldr r3, [r7, #20] 8001438: 3301 adds r3, #1 800143a: 617b str r3, [r7, #20] 800143c: 697a ldr r2, [r7, #20] 800143e: 687b ldr r3, [r7, #4] 8001440: 429a cmp r2, r3 8001442: dbf1 blt.n 8001428 <_write+0x12> } return len; 8001444: 687b ldr r3, [r7, #4] } 8001446: 0018 movs r0, r3 8001448: 46bd mov sp, r7 800144a: b006 add sp, #24 800144c: bd80 pop {r7, pc} 0800144e <_close>: int _close(int file) { 800144e: b580 push {r7, lr} 8001450: b082 sub sp, #8 8001452: af00 add r7, sp, #0 8001454: 6078 str r0, [r7, #4] (void)file; return -1; 8001456: 2301 movs r3, #1 8001458: 425b negs r3, r3 } 800145a: 0018 movs r0, r3 800145c: 46bd mov sp, r7 800145e: b002 add sp, #8 8001460: bd80 pop {r7, pc} 08001462 <_fstat>: int _fstat(int file, struct stat *st) { 8001462: b580 push {r7, lr} 8001464: b082 sub sp, #8 8001466: af00 add r7, sp, #0 8001468: 6078 str r0, [r7, #4] 800146a: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 800146c: 683b ldr r3, [r7, #0] 800146e: 2280 movs r2, #128 @ 0x80 8001470: 0192 lsls r2, r2, #6 8001472: 605a str r2, [r3, #4] return 0; 8001474: 2300 movs r3, #0 } 8001476: 0018 movs r0, r3 8001478: 46bd mov sp, r7 800147a: b002 add sp, #8 800147c: bd80 pop {r7, pc} 0800147e <_isatty>: int _isatty(int file) { 800147e: b580 push {r7, lr} 8001480: b082 sub sp, #8 8001482: af00 add r7, sp, #0 8001484: 6078 str r0, [r7, #4] (void)file; return 1; 8001486: 2301 movs r3, #1 } 8001488: 0018 movs r0, r3 800148a: 46bd mov sp, r7 800148c: b002 add sp, #8 800148e: bd80 pop {r7, pc} 08001490 <_lseek>: int _lseek(int file, int ptr, int dir) { 8001490: b580 push {r7, lr} 8001492: b084 sub sp, #16 8001494: af00 add r7, sp, #0 8001496: 60f8 str r0, [r7, #12] 8001498: 60b9 str r1, [r7, #8] 800149a: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 800149c: 2300 movs r3, #0 } 800149e: 0018 movs r0, r3 80014a0: 46bd mov sp, r7 80014a2: b004 add sp, #16 80014a4: bd80 pop {r7, pc} ... 080014a8 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80014a8: b580 push {r7, lr} 80014aa: b086 sub sp, #24 80014ac: af00 add r7, sp, #0 80014ae: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80014b0: 4a14 ldr r2, [pc, #80] @ (8001504 <_sbrk+0x5c>) 80014b2: 4b15 ldr r3, [pc, #84] @ (8001508 <_sbrk+0x60>) 80014b4: 1ad3 subs r3, r2, r3 80014b6: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 80014b8: 697b ldr r3, [r7, #20] 80014ba: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80014bc: 4b13 ldr r3, [pc, #76] @ (800150c <_sbrk+0x64>) 80014be: 681b ldr r3, [r3, #0] 80014c0: 2b00 cmp r3, #0 80014c2: d102 bne.n 80014ca <_sbrk+0x22> { __sbrk_heap_end = &_end; 80014c4: 4b11 ldr r3, [pc, #68] @ (800150c <_sbrk+0x64>) 80014c6: 4a12 ldr r2, [pc, #72] @ (8001510 <_sbrk+0x68>) 80014c8: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 80014ca: 4b10 ldr r3, [pc, #64] @ (800150c <_sbrk+0x64>) 80014cc: 681a ldr r2, [r3, #0] 80014ce: 687b ldr r3, [r7, #4] 80014d0: 18d3 adds r3, r2, r3 80014d2: 693a ldr r2, [r7, #16] 80014d4: 429a cmp r2, r3 80014d6: d207 bcs.n 80014e8 <_sbrk+0x40> { errno = ENOMEM; 80014d8: f004 f938 bl 800574c <__errno> 80014dc: 0003 movs r3, r0 80014de: 220c movs r2, #12 80014e0: 601a str r2, [r3, #0] return (void *)-1; 80014e2: 2301 movs r3, #1 80014e4: 425b negs r3, r3 80014e6: e009 b.n 80014fc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80014e8: 4b08 ldr r3, [pc, #32] @ (800150c <_sbrk+0x64>) 80014ea: 681b ldr r3, [r3, #0] 80014ec: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80014ee: 4b07 ldr r3, [pc, #28] @ (800150c <_sbrk+0x64>) 80014f0: 681a ldr r2, [r3, #0] 80014f2: 687b ldr r3, [r7, #4] 80014f4: 18d2 adds r2, r2, r3 80014f6: 4b05 ldr r3, [pc, #20] @ (800150c <_sbrk+0x64>) 80014f8: 601a str r2, [r3, #0] return (void *)prev_heap_end; 80014fa: 68fb ldr r3, [r7, #12] } 80014fc: 0018 movs r0, r3 80014fe: 46bd mov sp, r7 8001500: b006 add sp, #24 8001502: bd80 pop {r7, pc} 8001504: 20009000 .word 0x20009000 8001508: 00000400 .word 0x00000400 800150c: 200001d4 .word 0x200001d4 8001510: 20000328 .word 0x20000328 08001514 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 8001514: b580 push {r7, lr} 8001516: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001518: 46c0 nop @ (mov r8, r8) 800151a: 46bd mov sp, r7 800151c: bd80 pop {r7, pc} ... 08001520 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8001520: 480d ldr r0, [pc, #52] @ (8001558 ) mov sp, r0 /* set stack pointer */ 8001522: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001524: f7ff fff6 bl 8001514 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001528: 480c ldr r0, [pc, #48] @ (800155c ) ldr r1, =_edata 800152a: 490d ldr r1, [pc, #52] @ (8001560 ) ldr r2, =_sidata 800152c: 4a0d ldr r2, [pc, #52] @ (8001564 ) movs r3, #0 800152e: 2300 movs r3, #0 b LoopCopyDataInit 8001530: e002 b.n 8001538 08001532 : CopyDataInit: ldr r4, [r2, r3] 8001532: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001534: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001536: 3304 adds r3, #4 08001538 : LoopCopyDataInit: adds r4, r0, r3 8001538: 18c4 adds r4, r0, r3 cmp r4, r1 800153a: 428c cmp r4, r1 bcc CopyDataInit 800153c: d3f9 bcc.n 8001532 /* Zero fill the bss segment. */ ldr r2, =_sbss 800153e: 4a0a ldr r2, [pc, #40] @ (8001568 ) ldr r4, =_ebss 8001540: 4c0a ldr r4, [pc, #40] @ (800156c ) movs r3, #0 8001542: 2300 movs r3, #0 b LoopFillZerobss 8001544: e001 b.n 800154a 08001546 : FillZerobss: str r3, [r2] 8001546: 6013 str r3, [r2, #0] adds r2, r2, #4 8001548: 3204 adds r2, #4 0800154a : LoopFillZerobss: cmp r2, r4 800154a: 42a2 cmp r2, r4 bcc FillZerobss 800154c: d3fb bcc.n 8001546 /* Call static constructors */ bl __libc_init_array 800154e: f004 f903 bl 8005758 <__libc_init_array> /* Call the application s entry point.*/ bl main 8001552: f7ff fad5 bl 8000b00
08001556 : LoopForever: b LoopForever 8001556: e7fe b.n 8001556 ldr r0, =_estack 8001558: 20009000 .word 0x20009000 ldr r0, =_sdata 800155c: 20000000 .word 0x20000000 ldr r1, =_edata 8001560: 20000068 .word 0x20000068 ldr r2, =_sidata 8001564: 08006304 .word 0x08006304 ldr r2, =_sbss 8001568: 20000068 .word 0x20000068 ldr r4, =_ebss 800156c: 20000328 .word 0x20000328 08001570 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001570: e7fe b.n 8001570 ... 08001574 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001574: b580 push {r7, lr} 8001576: b082 sub sp, #8 8001578: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 800157a: 1dfb adds r3, r7, #7 800157c: 2200 movs r2, #0 800157e: 701a strb r2, [r3, #0] #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001580: 4b0b ldr r3, [pc, #44] @ (80015b0 ) 8001582: 681a ldr r2, [r3, #0] 8001584: 4b0a ldr r3, [pc, #40] @ (80015b0 ) 8001586: 2180 movs r1, #128 @ 0x80 8001588: 0049 lsls r1, r1, #1 800158a: 430a orrs r2, r1 800158c: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 800158e: 2003 movs r0, #3 8001590: f000 f810 bl 80015b4 8001594: 1e03 subs r3, r0, #0 8001596: d003 beq.n 80015a0 { status = HAL_ERROR; 8001598: 1dfb adds r3, r7, #7 800159a: 2201 movs r2, #1 800159c: 701a strb r2, [r3, #0] 800159e: e001 b.n 80015a4 } else { /* Init the low level hardware */ HAL_MspInit(); 80015a0: f7ff fdae bl 8001100 } /* Return function status */ return status; 80015a4: 1dfb adds r3, r7, #7 80015a6: 781b ldrb r3, [r3, #0] } 80015a8: 0018 movs r0, r3 80015aa: 46bd mov sp, r7 80015ac: b002 add sp, #8 80015ae: bd80 pop {r7, pc} 80015b0: 40022000 .word 0x40022000 080015b4 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80015b4: b590 push {r4, r7, lr} 80015b6: b085 sub sp, #20 80015b8: af00 add r7, sp, #0 80015ba: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80015bc: 230f movs r3, #15 80015be: 18fb adds r3, r7, r3 80015c0: 2200 movs r2, #0 80015c2: 701a strb r2, [r3, #0] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 80015c4: 4b1d ldr r3, [pc, #116] @ (800163c ) 80015c6: 781b ldrb r3, [r3, #0] 80015c8: 2b00 cmp r3, #0 80015ca: d02b beq.n 8001624 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) 80015cc: 4b1c ldr r3, [pc, #112] @ (8001640 ) 80015ce: 681c ldr r4, [r3, #0] 80015d0: 4b1a ldr r3, [pc, #104] @ (800163c ) 80015d2: 781b ldrb r3, [r3, #0] 80015d4: 0019 movs r1, r3 80015d6: 23fa movs r3, #250 @ 0xfa 80015d8: 0098 lsls r0, r3, #2 80015da: f7fe fd9b bl 8000114 <__udivsi3> 80015de: 0003 movs r3, r0 80015e0: 0019 movs r1, r3 80015e2: 0020 movs r0, r4 80015e4: f7fe fd96 bl 8000114 <__udivsi3> 80015e8: 0003 movs r3, r0 80015ea: 0018 movs r0, r3 80015ec: f000 f953 bl 8001896 80015f0: 1e03 subs r3, r0, #0 80015f2: d112 bne.n 800161a { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80015f4: 687b ldr r3, [r7, #4] 80015f6: 2b03 cmp r3, #3 80015f8: d80a bhi.n 8001610 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 80015fa: 6879 ldr r1, [r7, #4] 80015fc: 2301 movs r3, #1 80015fe: 425b negs r3, r3 8001600: 2200 movs r2, #0 8001602: 0018 movs r0, r3 8001604: f000 f922 bl 800184c uwTickPrio = TickPriority; 8001608: 4b0e ldr r3, [pc, #56] @ (8001644 ) 800160a: 687a ldr r2, [r7, #4] 800160c: 601a str r2, [r3, #0] 800160e: e00d b.n 800162c } else { status = HAL_ERROR; 8001610: 230f movs r3, #15 8001612: 18fb adds r3, r7, r3 8001614: 2201 movs r2, #1 8001616: 701a strb r2, [r3, #0] 8001618: e008 b.n 800162c } } else { status = HAL_ERROR; 800161a: 230f movs r3, #15 800161c: 18fb adds r3, r7, r3 800161e: 2201 movs r2, #1 8001620: 701a strb r2, [r3, #0] 8001622: e003 b.n 800162c } } else { status = HAL_ERROR; 8001624: 230f movs r3, #15 8001626: 18fb adds r3, r7, r3 8001628: 2201 movs r2, #1 800162a: 701a strb r2, [r3, #0] } /* Return function status */ return status; 800162c: 230f movs r3, #15 800162e: 18fb adds r3, r7, r3 8001630: 781b ldrb r3, [r3, #0] } 8001632: 0018 movs r0, r3 8001634: 46bd mov sp, r7 8001636: b005 add sp, #20 8001638: bd90 pop {r4, r7, pc} 800163a: 46c0 nop @ (mov r8, r8) 800163c: 20000008 .word 0x20000008 8001640: 20000000 .word 0x20000000 8001644: 20000004 .word 0x20000004 08001648 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001648: b580 push {r7, lr} 800164a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800164c: 4b05 ldr r3, [pc, #20] @ (8001664 ) 800164e: 781b ldrb r3, [r3, #0] 8001650: 001a movs r2, r3 8001652: 4b05 ldr r3, [pc, #20] @ (8001668 ) 8001654: 681b ldr r3, [r3, #0] 8001656: 18d2 adds r2, r2, r3 8001658: 4b03 ldr r3, [pc, #12] @ (8001668 ) 800165a: 601a str r2, [r3, #0] } 800165c: 46c0 nop @ (mov r8, r8) 800165e: 46bd mov sp, r7 8001660: bd80 pop {r7, pc} 8001662: 46c0 nop @ (mov r8, r8) 8001664: 20000008 .word 0x20000008 8001668: 200001d8 .word 0x200001d8 0800166c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 800166c: b580 push {r7, lr} 800166e: af00 add r7, sp, #0 return uwTick; 8001670: 4b02 ldr r3, [pc, #8] @ (800167c ) 8001672: 681b ldr r3, [r3, #0] } 8001674: 0018 movs r0, r3 8001676: 46bd mov sp, r7 8001678: bd80 pop {r7, pc} 800167a: 46c0 nop @ (mov r8, r8) 800167c: 200001d8 .word 0x200001d8 08001680 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001680: b580 push {r7, lr} 8001682: b084 sub sp, #16 8001684: af00 add r7, sp, #0 8001686: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001688: f7ff fff0 bl 800166c 800168c: 0003 movs r3, r0 800168e: 60bb str r3, [r7, #8] uint32_t wait = Delay; 8001690: 687b ldr r3, [r7, #4] 8001692: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001694: 68fb ldr r3, [r7, #12] 8001696: 3301 adds r3, #1 8001698: d005 beq.n 80016a6 { wait += (uint32_t)(uwTickFreq); 800169a: 4b0a ldr r3, [pc, #40] @ (80016c4 ) 800169c: 781b ldrb r3, [r3, #0] 800169e: 001a movs r2, r3 80016a0: 68fb ldr r3, [r7, #12] 80016a2: 189b adds r3, r3, r2 80016a4: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 80016a6: 46c0 nop @ (mov r8, r8) 80016a8: f7ff ffe0 bl 800166c 80016ac: 0002 movs r2, r0 80016ae: 68bb ldr r3, [r7, #8] 80016b0: 1ad3 subs r3, r2, r3 80016b2: 68fa ldr r2, [r7, #12] 80016b4: 429a cmp r2, r3 80016b6: d8f7 bhi.n 80016a8 { } } 80016b8: 46c0 nop @ (mov r8, r8) 80016ba: 46c0 nop @ (mov r8, r8) 80016bc: 46bd mov sp, r7 80016be: b004 add sp, #16 80016c0: bd80 pop {r7, pc} 80016c2: 46c0 nop @ (mov r8, r8) 80016c4: 20000008 .word 0x20000008 080016c8 : * @arg @ref SYSCFG_UCPD1_STROBE * @arg @ref SYSCFG_UCPD2_STROBE * @retval None */ void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery) { 80016c8: b580 push {r7, lr} 80016ca: b082 sub sp, #8 80016cc: af00 add r7, sp, #0 80016ce: 6078 str r0, [r7, #4] assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery)); /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */ MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery); 80016d0: 4b06 ldr r3, [pc, #24] @ (80016ec ) 80016d2: 681b ldr r3, [r3, #0] 80016d4: 4a06 ldr r2, [pc, #24] @ (80016f0 ) 80016d6: 4013 ands r3, r2 80016d8: 0019 movs r1, r3 80016da: 4b04 ldr r3, [pc, #16] @ (80016ec ) 80016dc: 687a ldr r2, [r7, #4] 80016de: 430a orrs r2, r1 80016e0: 601a str r2, [r3, #0] } 80016e2: 46c0 nop @ (mov r8, r8) 80016e4: 46bd mov sp, r7 80016e6: b002 add sp, #8 80016e8: bd80 pop {r7, pc} 80016ea: 46c0 nop @ (mov r8, r8) 80016ec: 40010000 .word 0x40010000 80016f0: fffff9ff .word 0xfffff9ff 080016f4 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80016f4: b580 push {r7, lr} 80016f6: b082 sub sp, #8 80016f8: af00 add r7, sp, #0 80016fa: 0002 movs r2, r0 80016fc: 1dfb adds r3, r7, #7 80016fe: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8001700: 1dfb adds r3, r7, #7 8001702: 781b ldrb r3, [r3, #0] 8001704: 2b7f cmp r3, #127 @ 0x7f 8001706: d809 bhi.n 800171c <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001708: 1dfb adds r3, r7, #7 800170a: 781b ldrb r3, [r3, #0] 800170c: 001a movs r2, r3 800170e: 231f movs r3, #31 8001710: 401a ands r2, r3 8001712: 4b04 ldr r3, [pc, #16] @ (8001724 <__NVIC_EnableIRQ+0x30>) 8001714: 2101 movs r1, #1 8001716: 4091 lsls r1, r2 8001718: 000a movs r2, r1 800171a: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } 800171c: 46c0 nop @ (mov r8, r8) 800171e: 46bd mov sp, r7 8001720: b002 add sp, #8 8001722: bd80 pop {r7, pc} 8001724: e000e100 .word 0xe000e100 08001728 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001728: b590 push {r4, r7, lr} 800172a: b083 sub sp, #12 800172c: af00 add r7, sp, #0 800172e: 0002 movs r2, r0 8001730: 6039 str r1, [r7, #0] 8001732: 1dfb adds r3, r7, #7 8001734: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 8001736: 1dfb adds r3, r7, #7 8001738: 781b ldrb r3, [r3, #0] 800173a: 2b7f cmp r3, #127 @ 0x7f 800173c: d828 bhi.n 8001790 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800173e: 4a2f ldr r2, [pc, #188] @ (80017fc <__NVIC_SetPriority+0xd4>) 8001740: 1dfb adds r3, r7, #7 8001742: 781b ldrb r3, [r3, #0] 8001744: b25b sxtb r3, r3 8001746: 089b lsrs r3, r3, #2 8001748: 33c0 adds r3, #192 @ 0xc0 800174a: 009b lsls r3, r3, #2 800174c: 589b ldr r3, [r3, r2] 800174e: 1dfa adds r2, r7, #7 8001750: 7812 ldrb r2, [r2, #0] 8001752: 0011 movs r1, r2 8001754: 2203 movs r2, #3 8001756: 400a ands r2, r1 8001758: 00d2 lsls r2, r2, #3 800175a: 21ff movs r1, #255 @ 0xff 800175c: 4091 lsls r1, r2 800175e: 000a movs r2, r1 8001760: 43d2 mvns r2, r2 8001762: 401a ands r2, r3 8001764: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8001766: 683b ldr r3, [r7, #0] 8001768: 019b lsls r3, r3, #6 800176a: 22ff movs r2, #255 @ 0xff 800176c: 401a ands r2, r3 800176e: 1dfb adds r3, r7, #7 8001770: 781b ldrb r3, [r3, #0] 8001772: 0018 movs r0, r3 8001774: 2303 movs r3, #3 8001776: 4003 ands r3, r0 8001778: 00db lsls r3, r3, #3 800177a: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800177c: 481f ldr r0, [pc, #124] @ (80017fc <__NVIC_SetPriority+0xd4>) 800177e: 1dfb adds r3, r7, #7 8001780: 781b ldrb r3, [r3, #0] 8001782: b25b sxtb r3, r3 8001784: 089b lsrs r3, r3, #2 8001786: 430a orrs r2, r1 8001788: 33c0 adds r3, #192 @ 0xc0 800178a: 009b lsls r3, r3, #2 800178c: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 800178e: e031 b.n 80017f4 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001790: 4a1b ldr r2, [pc, #108] @ (8001800 <__NVIC_SetPriority+0xd8>) 8001792: 1dfb adds r3, r7, #7 8001794: 781b ldrb r3, [r3, #0] 8001796: 0019 movs r1, r3 8001798: 230f movs r3, #15 800179a: 400b ands r3, r1 800179c: 3b08 subs r3, #8 800179e: 089b lsrs r3, r3, #2 80017a0: 3306 adds r3, #6 80017a2: 009b lsls r3, r3, #2 80017a4: 18d3 adds r3, r2, r3 80017a6: 3304 adds r3, #4 80017a8: 681b ldr r3, [r3, #0] 80017aa: 1dfa adds r2, r7, #7 80017ac: 7812 ldrb r2, [r2, #0] 80017ae: 0011 movs r1, r2 80017b0: 2203 movs r2, #3 80017b2: 400a ands r2, r1 80017b4: 00d2 lsls r2, r2, #3 80017b6: 21ff movs r1, #255 @ 0xff 80017b8: 4091 lsls r1, r2 80017ba: 000a movs r2, r1 80017bc: 43d2 mvns r2, r2 80017be: 401a ands r2, r3 80017c0: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80017c2: 683b ldr r3, [r7, #0] 80017c4: 019b lsls r3, r3, #6 80017c6: 22ff movs r2, #255 @ 0xff 80017c8: 401a ands r2, r3 80017ca: 1dfb adds r3, r7, #7 80017cc: 781b ldrb r3, [r3, #0] 80017ce: 0018 movs r0, r3 80017d0: 2303 movs r3, #3 80017d2: 4003 ands r3, r0 80017d4: 00db lsls r3, r3, #3 80017d6: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80017d8: 4809 ldr r0, [pc, #36] @ (8001800 <__NVIC_SetPriority+0xd8>) 80017da: 1dfb adds r3, r7, #7 80017dc: 781b ldrb r3, [r3, #0] 80017de: 001c movs r4, r3 80017e0: 230f movs r3, #15 80017e2: 4023 ands r3, r4 80017e4: 3b08 subs r3, #8 80017e6: 089b lsrs r3, r3, #2 80017e8: 430a orrs r2, r1 80017ea: 3306 adds r3, #6 80017ec: 009b lsls r3, r3, #2 80017ee: 18c3 adds r3, r0, r3 80017f0: 3304 adds r3, #4 80017f2: 601a str r2, [r3, #0] } 80017f4: 46c0 nop @ (mov r8, r8) 80017f6: 46bd mov sp, r7 80017f8: b003 add sp, #12 80017fa: bd90 pop {r4, r7, pc} 80017fc: e000e100 .word 0xe000e100 8001800: e000ed00 .word 0xe000ed00 08001804 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8001804: b580 push {r7, lr} 8001806: b082 sub sp, #8 8001808: af00 add r7, sp, #0 800180a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 800180c: 687b ldr r3, [r7, #4] 800180e: 1e5a subs r2, r3, #1 8001810: 2380 movs r3, #128 @ 0x80 8001812: 045b lsls r3, r3, #17 8001814: 429a cmp r2, r3 8001816: d301 bcc.n 800181c { return (1UL); /* Reload value impossible */ 8001818: 2301 movs r3, #1 800181a: e010 b.n 800183e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 800181c: 4b0a ldr r3, [pc, #40] @ (8001848 ) 800181e: 687a ldr r2, [r7, #4] 8001820: 3a01 subs r2, #1 8001822: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 8001824: 2301 movs r3, #1 8001826: 425b negs r3, r3 8001828: 2103 movs r1, #3 800182a: 0018 movs r0, r3 800182c: f7ff ff7c bl 8001728 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001830: 4b05 ldr r3, [pc, #20] @ (8001848 ) 8001832: 2200 movs r2, #0 8001834: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 8001836: 4b04 ldr r3, [pc, #16] @ (8001848 ) 8001838: 2207 movs r2, #7 800183a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 800183c: 2300 movs r3, #0 } 800183e: 0018 movs r0, r3 8001840: 46bd mov sp, r7 8001842: b002 add sp, #8 8001844: bd80 pop {r7, pc} 8001846: 46c0 nop @ (mov r8, r8) 8001848: e000e010 .word 0xe000e010 0800184c : * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800184c: b580 push {r7, lr} 800184e: b084 sub sp, #16 8001850: af00 add r7, sp, #0 8001852: 60b9 str r1, [r7, #8] 8001854: 607a str r2, [r7, #4] 8001856: 210f movs r1, #15 8001858: 187b adds r3, r7, r1 800185a: 1c02 adds r2, r0, #0 800185c: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 800185e: 68ba ldr r2, [r7, #8] 8001860: 187b adds r3, r7, r1 8001862: 781b ldrb r3, [r3, #0] 8001864: b25b sxtb r3, r3 8001866: 0011 movs r1, r2 8001868: 0018 movs r0, r3 800186a: f7ff ff5d bl 8001728 <__NVIC_SetPriority> } 800186e: 46c0 nop @ (mov r8, r8) 8001870: 46bd mov sp, r7 8001872: b004 add sp, #16 8001874: bd80 pop {r7, pc} 08001876 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001876: b580 push {r7, lr} 8001878: b082 sub sp, #8 800187a: af00 add r7, sp, #0 800187c: 0002 movs r2, r0 800187e: 1dfb adds r3, r7, #7 8001880: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001882: 1dfb adds r3, r7, #7 8001884: 781b ldrb r3, [r3, #0] 8001886: b25b sxtb r3, r3 8001888: 0018 movs r0, r3 800188a: f7ff ff33 bl 80016f4 <__NVIC_EnableIRQ> } 800188e: 46c0 nop @ (mov r8, r8) 8001890: 46bd mov sp, r7 8001892: b002 add sp, #8 8001894: bd80 pop {r7, pc} 08001896 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8001896: b580 push {r7, lr} 8001898: b082 sub sp, #8 800189a: af00 add r7, sp, #0 800189c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800189e: 687b ldr r3, [r7, #4] 80018a0: 0018 movs r0, r3 80018a2: f7ff ffaf bl 8001804 80018a6: 0003 movs r3, r0 } 80018a8: 0018 movs r0, r3 80018aa: 46bd mov sp, r7 80018ac: b002 add sp, #8 80018ae: bd80 pop {r7, pc} 080018b0 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 80018b0: b580 push {r7, lr} 80018b2: b084 sub sp, #16 80018b4: af00 add r7, sp, #0 80018b6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80018b8: 210f movs r1, #15 80018ba: 187b adds r3, r7, r1 80018bc: 2200 movs r2, #0 80018be: 701a strb r2, [r3, #0] if (hdma->State != HAL_DMA_STATE_BUSY) 80018c0: 687b ldr r3, [r7, #4] 80018c2: 2225 movs r2, #37 @ 0x25 80018c4: 5c9b ldrb r3, [r3, r2] 80018c6: b2db uxtb r3, r3 80018c8: 2b02 cmp r3, #2 80018ca: d006 beq.n 80018da { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80018cc: 687b ldr r3, [r7, #4] 80018ce: 2204 movs r2, #4 80018d0: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 80018d2: 187b adds r3, r7, r1 80018d4: 2201 movs r2, #1 80018d6: 701a strb r2, [r3, #0] 80018d8: e049 b.n 800196e } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80018da: 687b ldr r3, [r7, #4] 80018dc: 681b ldr r3, [r3, #0] 80018de: 681a ldr r2, [r3, #0] 80018e0: 687b ldr r3, [r7, #4] 80018e2: 681b ldr r3, [r3, #0] 80018e4: 210e movs r1, #14 80018e6: 438a bics r2, r1 80018e8: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80018ea: 687b ldr r3, [r7, #4] 80018ec: 681b ldr r3, [r3, #0] 80018ee: 681a ldr r2, [r3, #0] 80018f0: 687b ldr r3, [r7, #4] 80018f2: 681b ldr r3, [r3, #0] 80018f4: 2101 movs r1, #1 80018f6: 438a bics r2, r1 80018f8: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80018fa: 687b ldr r3, [r7, #4] 80018fc: 6c5b ldr r3, [r3, #68] @ 0x44 80018fe: 681a ldr r2, [r3, #0] 8001900: 687b ldr r3, [r7, #4] 8001902: 6c5b ldr r3, [r3, #68] @ 0x44 8001904: 491d ldr r1, [pc, #116] @ (800197c ) 8001906: 400a ands r2, r1 8001908: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); 800190a: 4b1d ldr r3, [pc, #116] @ (8001980 ) 800190c: 6859 ldr r1, [r3, #4] 800190e: 687b ldr r3, [r7, #4] 8001910: 6c1b ldr r3, [r3, #64] @ 0x40 8001912: 221c movs r2, #28 8001914: 4013 ands r3, r2 8001916: 2201 movs r2, #1 8001918: 409a lsls r2, r3 800191a: 4b19 ldr r3, [pc, #100] @ (8001980 ) 800191c: 430a orrs r2, r1 800191e: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8001920: 687b ldr r3, [r7, #4] 8001922: 6c9b ldr r3, [r3, #72] @ 0x48 8001924: 687a ldr r2, [r7, #4] 8001926: 6cd2 ldr r2, [r2, #76] @ 0x4c 8001928: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 800192a: 687b ldr r3, [r7, #4] 800192c: 6d1b ldr r3, [r3, #80] @ 0x50 800192e: 2b00 cmp r3, #0 8001930: d00c beq.n 800194c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001932: 687b ldr r3, [r7, #4] 8001934: 6d1b ldr r3, [r3, #80] @ 0x50 8001936: 681a ldr r2, [r3, #0] 8001938: 687b ldr r3, [r7, #4] 800193a: 6d1b ldr r3, [r3, #80] @ 0x50 800193c: 490f ldr r1, [pc, #60] @ (800197c ) 800193e: 400a ands r2, r1 8001940: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001942: 687b ldr r3, [r7, #4] 8001944: 6d5b ldr r3, [r3, #84] @ 0x54 8001946: 687a ldr r2, [r7, #4] 8001948: 6d92 ldr r2, [r2, #88] @ 0x58 800194a: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800194c: 687b ldr r3, [r7, #4] 800194e: 2225 movs r2, #37 @ 0x25 8001950: 2101 movs r1, #1 8001952: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001954: 687b ldr r3, [r7, #4] 8001956: 2224 movs r2, #36 @ 0x24 8001958: 2100 movs r1, #0 800195a: 5499 strb r1, [r3, r2] /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 800195c: 687b ldr r3, [r7, #4] 800195e: 6b9b ldr r3, [r3, #56] @ 0x38 8001960: 2b00 cmp r3, #0 8001962: d004 beq.n 800196e { hdma->XferAbortCallback(hdma); 8001964: 687b ldr r3, [r7, #4] 8001966: 6b9b ldr r3, [r3, #56] @ 0x38 8001968: 687a ldr r2, [r7, #4] 800196a: 0010 movs r0, r2 800196c: 4798 blx r3 } } return status; 800196e: 230f movs r3, #15 8001970: 18fb adds r3, r7, r3 8001972: 781b ldrb r3, [r3, #0] } 8001974: 0018 movs r0, r3 8001976: 46bd mov sp, r7 8001978: b004 add sp, #16 800197a: bd80 pop {r7, pc} 800197c: fffffeff .word 0xfffffeff 8001980: 40020000 .word 0x40020000 08001984 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { 8001984: b580 push {r7, lr} 8001986: b082 sub sp, #8 8001988: af00 add r7, sp, #0 800198a: 6078 str r0, [r7, #4] /* Return DMA handle state */ return hdma->State; 800198c: 687b ldr r3, [r7, #4] 800198e: 2225 movs r2, #37 @ 0x25 8001990: 5c9b ldrb r3, [r3, r2] 8001992: b2db uxtb r3, r3 } 8001994: 0018 movs r0, r3 8001996: 46bd mov sp, r7 8001998: b002 add sp, #8 800199a: bd80 pop {r7, pc} 0800199c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800199c: b580 push {r7, lr} 800199e: b086 sub sp, #24 80019a0: af00 add r7, sp, #0 80019a2: 6078 str r0, [r7, #4] 80019a4: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 80019a6: 2300 movs r3, #0 80019a8: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 80019aa: e147 b.n 8001c3c { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 80019ac: 683b ldr r3, [r7, #0] 80019ae: 681b ldr r3, [r3, #0] 80019b0: 2101 movs r1, #1 80019b2: 697a ldr r2, [r7, #20] 80019b4: 4091 lsls r1, r2 80019b6: 000a movs r2, r1 80019b8: 4013 ands r3, r2 80019ba: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 80019bc: 68fb ldr r3, [r7, #12] 80019be: 2b00 cmp r3, #0 80019c0: d100 bne.n 80019c4 80019c2: e138 b.n 8001c36 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80019c4: 683b ldr r3, [r7, #0] 80019c6: 685b ldr r3, [r3, #4] 80019c8: 2203 movs r2, #3 80019ca: 4013 ands r3, r2 80019cc: 2b01 cmp r3, #1 80019ce: d005 beq.n 80019dc 80019d0: 683b ldr r3, [r7, #0] 80019d2: 685b ldr r3, [r3, #4] 80019d4: 2203 movs r2, #3 80019d6: 4013 ands r3, r2 80019d8: 2b02 cmp r3, #2 80019da: d130 bne.n 8001a3e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80019dc: 687b ldr r3, [r7, #4] 80019de: 689b ldr r3, [r3, #8] 80019e0: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 80019e2: 697b ldr r3, [r7, #20] 80019e4: 005b lsls r3, r3, #1 80019e6: 2203 movs r2, #3 80019e8: 409a lsls r2, r3 80019ea: 0013 movs r3, r2 80019ec: 43da mvns r2, r3 80019ee: 693b ldr r3, [r7, #16] 80019f0: 4013 ands r3, r2 80019f2: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80019f4: 683b ldr r3, [r7, #0] 80019f6: 68da ldr r2, [r3, #12] 80019f8: 697b ldr r3, [r7, #20] 80019fa: 005b lsls r3, r3, #1 80019fc: 409a lsls r2, r3 80019fe: 0013 movs r3, r2 8001a00: 693a ldr r2, [r7, #16] 8001a02: 4313 orrs r3, r2 8001a04: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8001a06: 687b ldr r3, [r7, #4] 8001a08: 693a ldr r2, [r7, #16] 8001a0a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001a0c: 687b ldr r3, [r7, #4] 8001a0e: 685b ldr r3, [r3, #4] 8001a10: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8001a12: 2201 movs r2, #1 8001a14: 697b ldr r3, [r7, #20] 8001a16: 409a lsls r2, r3 8001a18: 0013 movs r3, r2 8001a1a: 43da mvns r2, r3 8001a1c: 693b ldr r3, [r7, #16] 8001a1e: 4013 ands r3, r2 8001a20: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001a22: 683b ldr r3, [r7, #0] 8001a24: 685b ldr r3, [r3, #4] 8001a26: 091b lsrs r3, r3, #4 8001a28: 2201 movs r2, #1 8001a2a: 401a ands r2, r3 8001a2c: 697b ldr r3, [r7, #20] 8001a2e: 409a lsls r2, r3 8001a30: 0013 movs r3, r2 8001a32: 693a ldr r2, [r7, #16] 8001a34: 4313 orrs r3, r2 8001a36: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8001a38: 687b ldr r3, [r7, #4] 8001a3a: 693a ldr r2, [r7, #16] 8001a3c: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001a3e: 683b ldr r3, [r7, #0] 8001a40: 685b ldr r3, [r3, #4] 8001a42: 2203 movs r2, #3 8001a44: 4013 ands r3, r2 8001a46: 2b03 cmp r3, #3 8001a48: d017 beq.n 8001a7a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001a4a: 687b ldr r3, [r7, #4] 8001a4c: 68db ldr r3, [r3, #12] 8001a4e: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); 8001a50: 697b ldr r3, [r7, #20] 8001a52: 005b lsls r3, r3, #1 8001a54: 2203 movs r2, #3 8001a56: 409a lsls r2, r3 8001a58: 0013 movs r3, r2 8001a5a: 43da mvns r2, r3 8001a5c: 693b ldr r3, [r7, #16] 8001a5e: 4013 ands r3, r2 8001a60: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8001a62: 683b ldr r3, [r7, #0] 8001a64: 689a ldr r2, [r3, #8] 8001a66: 697b ldr r3, [r7, #20] 8001a68: 005b lsls r3, r3, #1 8001a6a: 409a lsls r2, r3 8001a6c: 0013 movs r3, r2 8001a6e: 693a ldr r2, [r7, #16] 8001a70: 4313 orrs r3, r2 8001a72: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001a74: 687b ldr r3, [r7, #4] 8001a76: 693a ldr r2, [r7, #16] 8001a78: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001a7a: 683b ldr r3, [r7, #0] 8001a7c: 685b ldr r3, [r3, #4] 8001a7e: 2203 movs r2, #3 8001a80: 4013 ands r3, r2 8001a82: 2b02 cmp r3, #2 8001a84: d123 bne.n 8001ace /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 8001a86: 697b ldr r3, [r7, #20] 8001a88: 08da lsrs r2, r3, #3 8001a8a: 687b ldr r3, [r7, #4] 8001a8c: 3208 adds r2, #8 8001a8e: 0092 lsls r2, r2, #2 8001a90: 58d3 ldr r3, [r2, r3] 8001a92: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001a94: 697b ldr r3, [r7, #20] 8001a96: 2207 movs r2, #7 8001a98: 4013 ands r3, r2 8001a9a: 009b lsls r3, r3, #2 8001a9c: 220f movs r2, #15 8001a9e: 409a lsls r2, r3 8001aa0: 0013 movs r3, r2 8001aa2: 43da mvns r2, r3 8001aa4: 693b ldr r3, [r7, #16] 8001aa6: 4013 ands r3, r2 8001aa8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 8001aaa: 683b ldr r3, [r7, #0] 8001aac: 691a ldr r2, [r3, #16] 8001aae: 697b ldr r3, [r7, #20] 8001ab0: 2107 movs r1, #7 8001ab2: 400b ands r3, r1 8001ab4: 009b lsls r3, r3, #2 8001ab6: 409a lsls r2, r3 8001ab8: 0013 movs r3, r2 8001aba: 693a ldr r2, [r7, #16] 8001abc: 4313 orrs r3, r2 8001abe: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8001ac0: 697b ldr r3, [r7, #20] 8001ac2: 08da lsrs r2, r3, #3 8001ac4: 687b ldr r3, [r7, #4] 8001ac6: 3208 adds r2, #8 8001ac8: 0092 lsls r2, r2, #2 8001aca: 6939 ldr r1, [r7, #16] 8001acc: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001ace: 687b ldr r3, [r7, #4] 8001ad0: 681b ldr r3, [r3, #0] 8001ad2: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 8001ad4: 697b ldr r3, [r7, #20] 8001ad6: 005b lsls r3, r3, #1 8001ad8: 2203 movs r2, #3 8001ada: 409a lsls r2, r3 8001adc: 0013 movs r3, r2 8001ade: 43da mvns r2, r3 8001ae0: 693b ldr r3, [r7, #16] 8001ae2: 4013 ands r3, r2 8001ae4: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 8001ae6: 683b ldr r3, [r7, #0] 8001ae8: 685b ldr r3, [r3, #4] 8001aea: 2203 movs r2, #3 8001aec: 401a ands r2, r3 8001aee: 697b ldr r3, [r7, #20] 8001af0: 005b lsls r3, r3, #1 8001af2: 409a lsls r2, r3 8001af4: 0013 movs r3, r2 8001af6: 693a ldr r2, [r7, #16] 8001af8: 4313 orrs r3, r2 8001afa: 613b str r3, [r7, #16] GPIOx->MODER = temp; 8001afc: 687b ldr r3, [r7, #4] 8001afe: 693a ldr r2, [r7, #16] 8001b00: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 8001b02: 683b ldr r3, [r7, #0] 8001b04: 685a ldr r2, [r3, #4] 8001b06: 23c0 movs r3, #192 @ 0xc0 8001b08: 029b lsls r3, r3, #10 8001b0a: 4013 ands r3, r2 8001b0c: d100 bne.n 8001b10 8001b0e: e092 b.n 8001c36 { temp = EXTI->EXTICR[position >> 2u]; 8001b10: 4a50 ldr r2, [pc, #320] @ (8001c54 ) 8001b12: 697b ldr r3, [r7, #20] 8001b14: 089b lsrs r3, r3, #2 8001b16: 3318 adds r3, #24 8001b18: 009b lsls r3, r3, #2 8001b1a: 589b ldr r3, [r3, r2] 8001b1c: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (8u * (position & 0x03u))); 8001b1e: 697b ldr r3, [r7, #20] 8001b20: 2203 movs r2, #3 8001b22: 4013 ands r3, r2 8001b24: 00db lsls r3, r3, #3 8001b26: 220f movs r2, #15 8001b28: 409a lsls r2, r3 8001b2a: 0013 movs r3, r2 8001b2c: 43da mvns r2, r3 8001b2e: 693b ldr r3, [r7, #16] 8001b30: 4013 ands r3, r2 8001b32: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); 8001b34: 687a ldr r2, [r7, #4] 8001b36: 23a0 movs r3, #160 @ 0xa0 8001b38: 05db lsls r3, r3, #23 8001b3a: 429a cmp r2, r3 8001b3c: d013 beq.n 8001b66 8001b3e: 687b ldr r3, [r7, #4] 8001b40: 4a45 ldr r2, [pc, #276] @ (8001c58 ) 8001b42: 4293 cmp r3, r2 8001b44: d00d beq.n 8001b62 8001b46: 687b ldr r3, [r7, #4] 8001b48: 4a44 ldr r2, [pc, #272] @ (8001c5c ) 8001b4a: 4293 cmp r3, r2 8001b4c: d007 beq.n 8001b5e 8001b4e: 687b ldr r3, [r7, #4] 8001b50: 4a43 ldr r2, [pc, #268] @ (8001c60 ) 8001b52: 4293 cmp r3, r2 8001b54: d101 bne.n 8001b5a 8001b56: 2303 movs r3, #3 8001b58: e006 b.n 8001b68 8001b5a: 2305 movs r3, #5 8001b5c: e004 b.n 8001b68 8001b5e: 2302 movs r3, #2 8001b60: e002 b.n 8001b68 8001b62: 2301 movs r3, #1 8001b64: e000 b.n 8001b68 8001b66: 2300 movs r3, #0 8001b68: 697a ldr r2, [r7, #20] 8001b6a: 2103 movs r1, #3 8001b6c: 400a ands r2, r1 8001b6e: 00d2 lsls r2, r2, #3 8001b70: 4093 lsls r3, r2 8001b72: 693a ldr r2, [r7, #16] 8001b74: 4313 orrs r3, r2 8001b76: 613b str r3, [r7, #16] EXTI->EXTICR[position >> 2u] = temp; 8001b78: 4936 ldr r1, [pc, #216] @ (8001c54 ) 8001b7a: 697b ldr r3, [r7, #20] 8001b7c: 089b lsrs r3, r3, #2 8001b7e: 3318 adds r3, #24 8001b80: 009b lsls r3, r3, #2 8001b82: 693a ldr r2, [r7, #16] 8001b84: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8001b86: 4b33 ldr r3, [pc, #204] @ (8001c54 ) 8001b88: 681b ldr r3, [r3, #0] 8001b8a: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001b8c: 68fb ldr r3, [r7, #12] 8001b8e: 43da mvns r2, r3 8001b90: 693b ldr r3, [r7, #16] 8001b92: 4013 ands r3, r2 8001b94: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 8001b96: 683b ldr r3, [r7, #0] 8001b98: 685a ldr r2, [r3, #4] 8001b9a: 2380 movs r3, #128 @ 0x80 8001b9c: 035b lsls r3, r3, #13 8001b9e: 4013 ands r3, r2 8001ba0: d003 beq.n 8001baa { temp |= iocurrent; 8001ba2: 693a ldr r2, [r7, #16] 8001ba4: 68fb ldr r3, [r7, #12] 8001ba6: 4313 orrs r3, r2 8001ba8: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8001baa: 4b2a ldr r3, [pc, #168] @ (8001c54 ) 8001bac: 693a ldr r2, [r7, #16] 8001bae: 601a str r2, [r3, #0] temp = EXTI->FTSR1; 8001bb0: 4b28 ldr r3, [pc, #160] @ (8001c54 ) 8001bb2: 685b ldr r3, [r3, #4] 8001bb4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001bb6: 68fb ldr r3, [r7, #12] 8001bb8: 43da mvns r2, r3 8001bba: 693b ldr r3, [r7, #16] 8001bbc: 4013 ands r3, r2 8001bbe: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8001bc0: 683b ldr r3, [r7, #0] 8001bc2: 685a ldr r2, [r3, #4] 8001bc4: 2380 movs r3, #128 @ 0x80 8001bc6: 039b lsls r3, r3, #14 8001bc8: 4013 ands r3, r2 8001bca: d003 beq.n 8001bd4 { temp |= iocurrent; 8001bcc: 693a ldr r2, [r7, #16] 8001bce: 68fb ldr r3, [r7, #12] 8001bd0: 4313 orrs r3, r2 8001bd2: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 8001bd4: 4b1f ldr r3, [pc, #124] @ (8001c54 ) 8001bd6: 693a ldr r2, [r7, #16] 8001bd8: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 8001bda: 4a1e ldr r2, [pc, #120] @ (8001c54 ) 8001bdc: 2384 movs r3, #132 @ 0x84 8001bde: 58d3 ldr r3, [r2, r3] 8001be0: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001be2: 68fb ldr r3, [r7, #12] 8001be4: 43da mvns r2, r3 8001be6: 693b ldr r3, [r7, #16] 8001be8: 4013 ands r3, r2 8001bea: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 8001bec: 683b ldr r3, [r7, #0] 8001bee: 685a ldr r2, [r3, #4] 8001bf0: 2380 movs r3, #128 @ 0x80 8001bf2: 029b lsls r3, r3, #10 8001bf4: 4013 ands r3, r2 8001bf6: d003 beq.n 8001c00 { temp |= iocurrent; 8001bf8: 693a ldr r2, [r7, #16] 8001bfa: 68fb ldr r3, [r7, #12] 8001bfc: 4313 orrs r3, r2 8001bfe: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8001c00: 4914 ldr r1, [pc, #80] @ (8001c54 ) 8001c02: 2284 movs r2, #132 @ 0x84 8001c04: 693b ldr r3, [r7, #16] 8001c06: 508b str r3, [r1, r2] temp = EXTI->IMR1; 8001c08: 4a12 ldr r2, [pc, #72] @ (8001c54 ) 8001c0a: 2380 movs r3, #128 @ 0x80 8001c0c: 58d3 ldr r3, [r2, r3] 8001c0e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001c10: 68fb ldr r3, [r7, #12] 8001c12: 43da mvns r2, r3 8001c14: 693b ldr r3, [r7, #16] 8001c16: 4013 ands r3, r2 8001c18: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 8001c1a: 683b ldr r3, [r7, #0] 8001c1c: 685a ldr r2, [r3, #4] 8001c1e: 2380 movs r3, #128 @ 0x80 8001c20: 025b lsls r3, r3, #9 8001c22: 4013 ands r3, r2 8001c24: d003 beq.n 8001c2e { temp |= iocurrent; 8001c26: 693a ldr r2, [r7, #16] 8001c28: 68fb ldr r3, [r7, #12] 8001c2a: 4313 orrs r3, r2 8001c2c: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8001c2e: 4909 ldr r1, [pc, #36] @ (8001c54 ) 8001c30: 2280 movs r2, #128 @ 0x80 8001c32: 693b ldr r3, [r7, #16] 8001c34: 508b str r3, [r1, r2] } } position++; 8001c36: 697b ldr r3, [r7, #20] 8001c38: 3301 adds r3, #1 8001c3a: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8001c3c: 683b ldr r3, [r7, #0] 8001c3e: 681a ldr r2, [r3, #0] 8001c40: 697b ldr r3, [r7, #20] 8001c42: 40da lsrs r2, r3 8001c44: 1e13 subs r3, r2, #0 8001c46: d000 beq.n 8001c4a 8001c48: e6b0 b.n 80019ac } } 8001c4a: 46c0 nop @ (mov r8, r8) 8001c4c: 46c0 nop @ (mov r8, r8) 8001c4e: 46bd mov sp, r7 8001c50: b006 add sp, #24 8001c52: bd80 pop {r7, pc} 8001c54: 40021800 .word 0x40021800 8001c58: 50000400 .word 0x50000400 8001c5c: 50000800 .word 0x50000800 8001c60: 50000c00 .word 0x50000c00 08001c64 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001c64: b580 push {r7, lr} 8001c66: b082 sub sp, #8 8001c68: af00 add r7, sp, #0 8001c6a: 6078 str r0, [r7, #4] 8001c6c: 0008 movs r0, r1 8001c6e: 0011 movs r1, r2 8001c70: 1cbb adds r3, r7, #2 8001c72: 1c02 adds r2, r0, #0 8001c74: 801a strh r2, [r3, #0] 8001c76: 1c7b adds r3, r7, #1 8001c78: 1c0a adds r2, r1, #0 8001c7a: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8001c7c: 1c7b adds r3, r7, #1 8001c7e: 781b ldrb r3, [r3, #0] 8001c80: 2b00 cmp r3, #0 8001c82: d004 beq.n 8001c8e { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001c84: 1cbb adds r3, r7, #2 8001c86: 881a ldrh r2, [r3, #0] 8001c88: 687b ldr r3, [r7, #4] 8001c8a: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8001c8c: e003 b.n 8001c96 GPIOx->BRR = (uint32_t)GPIO_Pin; 8001c8e: 1cbb adds r3, r7, #2 8001c90: 881a ldrh r2, [r3, #0] 8001c92: 687b ldr r3, [r7, #4] 8001c94: 629a str r2, [r3, #40] @ 0x28 } 8001c96: 46c0 nop @ (mov r8, r8) 8001c98: 46bd mov sp, r7 8001c9a: b002 add sp, #8 8001c9c: bd80 pop {r7, pc} ... 08001ca0 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8001ca0: b580 push {r7, lr} 8001ca2: b082 sub sp, #8 8001ca4: af00 add r7, sp, #0 8001ca6: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 8001ca8: 687b ldr r3, [r7, #4] 8001caa: 2b00 cmp r3, #0 8001cac: d101 bne.n 8001cb2 { return HAL_ERROR; 8001cae: 2301 movs r3, #1 8001cb0: e08f b.n 8001dd2 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8001cb2: 687b ldr r3, [r7, #4] 8001cb4: 2241 movs r2, #65 @ 0x41 8001cb6: 5c9b ldrb r3, [r3, r2] 8001cb8: b2db uxtb r3, r3 8001cba: 2b00 cmp r3, #0 8001cbc: d107 bne.n 8001cce { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8001cbe: 687b ldr r3, [r7, #4] 8001cc0: 2240 movs r2, #64 @ 0x40 8001cc2: 2100 movs r1, #0 8001cc4: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 8001cc6: 687b ldr r3, [r7, #4] 8001cc8: 0018 movs r0, r3 8001cca: f7ff fa41 bl 8001150 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8001cce: 687b ldr r3, [r7, #4] 8001cd0: 2241 movs r2, #65 @ 0x41 8001cd2: 2124 movs r1, #36 @ 0x24 8001cd4: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8001cd6: 687b ldr r3, [r7, #4] 8001cd8: 681b ldr r3, [r3, #0] 8001cda: 681a ldr r2, [r3, #0] 8001cdc: 687b ldr r3, [r7, #4] 8001cde: 681b ldr r3, [r3, #0] 8001ce0: 2101 movs r1, #1 8001ce2: 438a bics r2, r1 8001ce4: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 8001ce6: 687b ldr r3, [r7, #4] 8001ce8: 685a ldr r2, [r3, #4] 8001cea: 687b ldr r3, [r7, #4] 8001cec: 681b ldr r3, [r3, #0] 8001cee: 493b ldr r1, [pc, #236] @ (8001ddc ) 8001cf0: 400a ands r2, r1 8001cf2: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8001cf4: 687b ldr r3, [r7, #4] 8001cf6: 681b ldr r3, [r3, #0] 8001cf8: 689a ldr r2, [r3, #8] 8001cfa: 687b ldr r3, [r7, #4] 8001cfc: 681b ldr r3, [r3, #0] 8001cfe: 4938 ldr r1, [pc, #224] @ (8001de0 ) 8001d00: 400a ands r2, r1 8001d02: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8001d04: 687b ldr r3, [r7, #4] 8001d06: 68db ldr r3, [r3, #12] 8001d08: 2b01 cmp r3, #1 8001d0a: d108 bne.n 8001d1e { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8001d0c: 687b ldr r3, [r7, #4] 8001d0e: 689a ldr r2, [r3, #8] 8001d10: 687b ldr r3, [r7, #4] 8001d12: 681b ldr r3, [r3, #0] 8001d14: 2180 movs r1, #128 @ 0x80 8001d16: 0209 lsls r1, r1, #8 8001d18: 430a orrs r2, r1 8001d1a: 609a str r2, [r3, #8] 8001d1c: e007 b.n 8001d2e } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 8001d1e: 687b ldr r3, [r7, #4] 8001d20: 689a ldr r2, [r3, #8] 8001d22: 687b ldr r3, [r7, #4] 8001d24: 681b ldr r3, [r3, #0] 8001d26: 2184 movs r1, #132 @ 0x84 8001d28: 0209 lsls r1, r1, #8 8001d2a: 430a orrs r2, r1 8001d2c: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8001d2e: 687b ldr r3, [r7, #4] 8001d30: 68db ldr r3, [r3, #12] 8001d32: 2b02 cmp r3, #2 8001d34: d109 bne.n 8001d4a { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001d36: 687b ldr r3, [r7, #4] 8001d38: 681b ldr r3, [r3, #0] 8001d3a: 685a ldr r2, [r3, #4] 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 681b ldr r3, [r3, #0] 8001d40: 2180 movs r1, #128 @ 0x80 8001d42: 0109 lsls r1, r1, #4 8001d44: 430a orrs r2, r1 8001d46: 605a str r2, [r3, #4] 8001d48: e007 b.n 8001d5a } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001d4a: 687b ldr r3, [r7, #4] 8001d4c: 681b ldr r3, [r3, #0] 8001d4e: 685a ldr r2, [r3, #4] 8001d50: 687b ldr r3, [r7, #4] 8001d52: 681b ldr r3, [r3, #0] 8001d54: 4923 ldr r1, [pc, #140] @ (8001de4 ) 8001d56: 400a ands r2, r1 8001d58: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8001d5a: 687b ldr r3, [r7, #4] 8001d5c: 681b ldr r3, [r3, #0] 8001d5e: 685a ldr r2, [r3, #4] 8001d60: 687b ldr r3, [r7, #4] 8001d62: 681b ldr r3, [r3, #0] 8001d64: 4920 ldr r1, [pc, #128] @ (8001de8 ) 8001d66: 430a orrs r2, r1 8001d68: 605a str r2, [r3, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8001d6a: 687b ldr r3, [r7, #4] 8001d6c: 681b ldr r3, [r3, #0] 8001d6e: 68da ldr r2, [r3, #12] 8001d70: 687b ldr r3, [r7, #4] 8001d72: 681b ldr r3, [r3, #0] 8001d74: 491a ldr r1, [pc, #104] @ (8001de0 ) 8001d76: 400a ands r2, r1 8001d78: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001d7a: 687b ldr r3, [r7, #4] 8001d7c: 691a ldr r2, [r3, #16] 8001d7e: 687b ldr r3, [r7, #4] 8001d80: 695b ldr r3, [r3, #20] 8001d82: 431a orrs r2, r3 8001d84: 0011 movs r1, r2 (hi2c->Init.OwnAddress2Masks << 8)); 8001d86: 687b ldr r3, [r7, #4] 8001d88: 699b ldr r3, [r3, #24] 8001d8a: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 681b ldr r3, [r3, #0] 8001d90: 430a orrs r2, r1 8001d92: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 8001d94: 687b ldr r3, [r7, #4] 8001d96: 69d9 ldr r1, [r3, #28] 8001d98: 687b ldr r3, [r7, #4] 8001d9a: 6a1a ldr r2, [r3, #32] 8001d9c: 687b ldr r3, [r7, #4] 8001d9e: 681b ldr r3, [r3, #0] 8001da0: 430a orrs r2, r1 8001da2: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8001da4: 687b ldr r3, [r7, #4] 8001da6: 681b ldr r3, [r3, #0] 8001da8: 681a ldr r2, [r3, #0] 8001daa: 687b ldr r3, [r7, #4] 8001dac: 681b ldr r3, [r3, #0] 8001dae: 2101 movs r1, #1 8001db0: 430a orrs r2, r1 8001db2: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8001db4: 687b ldr r3, [r7, #4] 8001db6: 2200 movs r2, #0 8001db8: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 8001dba: 687b ldr r3, [r7, #4] 8001dbc: 2241 movs r2, #65 @ 0x41 8001dbe: 2120 movs r1, #32 8001dc0: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8001dc2: 687b ldr r3, [r7, #4] 8001dc4: 2200 movs r2, #0 8001dc6: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8001dc8: 687b ldr r3, [r7, #4] 8001dca: 2242 movs r2, #66 @ 0x42 8001dcc: 2100 movs r1, #0 8001dce: 5499 strb r1, [r3, r2] return HAL_OK; 8001dd0: 2300 movs r3, #0 } 8001dd2: 0018 movs r0, r3 8001dd4: 46bd mov sp, r7 8001dd6: b002 add sp, #8 8001dd8: bd80 pop {r7, pc} 8001dda: 46c0 nop @ (mov r8, r8) 8001ddc: f0ffffff .word 0xf0ffffff 8001de0: ffff7fff .word 0xffff7fff 8001de4: fffff7ff .word 0xfffff7ff 8001de8: 02008000 .word 0x02008000 08001dec : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { 8001dec: b580 push {r7, lr} 8001dee: b084 sub sp, #16 8001df0: af00 add r7, sp, #0 8001df2: 6078 str r0, [r7, #4] /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8001df4: 687b ldr r3, [r7, #4] 8001df6: 681b ldr r3, [r3, #0] 8001df8: 699b ldr r3, [r3, #24] 8001dfa: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8001dfc: 687b ldr r3, [r7, #4] 8001dfe: 681b ldr r3, [r3, #0] 8001e00: 681b ldr r3, [r3, #0] 8001e02: 60bb str r3, [r7, #8] /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) 8001e04: 687b ldr r3, [r7, #4] 8001e06: 6b5b ldr r3, [r3, #52] @ 0x34 8001e08: 2b00 cmp r3, #0 8001e0a: d005 beq.n 8001e18 { hi2c->XferISR(hi2c, itflags, itsources); 8001e0c: 687b ldr r3, [r7, #4] 8001e0e: 6b5b ldr r3, [r3, #52] @ 0x34 8001e10: 68ba ldr r2, [r7, #8] 8001e12: 68f9 ldr r1, [r7, #12] 8001e14: 6878 ldr r0, [r7, #4] 8001e16: 4798 blx r3 } } 8001e18: 46c0 nop @ (mov r8, r8) 8001e1a: 46bd mov sp, r7 8001e1c: b004 add sp, #16 8001e1e: bd80 pop {r7, pc} 08001e20 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { 8001e20: b580 push {r7, lr} 8001e22: b086 sub sp, #24 8001e24: af00 add r7, sp, #0 8001e26: 6078 str r0, [r7, #4] uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8001e28: 687b ldr r3, [r7, #4] 8001e2a: 681b ldr r3, [r3, #0] 8001e2c: 699b ldr r3, [r3, #24] 8001e2e: 617b str r3, [r7, #20] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8001e30: 687b ldr r3, [r7, #4] 8001e32: 681b ldr r3, [r3, #0] 8001e34: 681b ldr r3, [r3, #0] 8001e36: 613b str r3, [r7, #16] uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8001e38: 697a ldr r2, [r7, #20] 8001e3a: 2380 movs r3, #128 @ 0x80 8001e3c: 005b lsls r3, r3, #1 8001e3e: 4013 ands r3, r2 8001e40: d00e beq.n 8001e60 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001e42: 693b ldr r3, [r7, #16] 8001e44: 2280 movs r2, #128 @ 0x80 8001e46: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8001e48: d00a beq.n 8001e60 { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; 8001e4a: 687b ldr r3, [r7, #4] 8001e4c: 6c5b ldr r3, [r3, #68] @ 0x44 8001e4e: 2201 movs r2, #1 8001e50: 431a orrs r2, r3 8001e52: 687b ldr r3, [r7, #4] 8001e54: 645a str r2, [r3, #68] @ 0x44 /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8001e56: 687b ldr r3, [r7, #4] 8001e58: 681b ldr r3, [r3, #0] 8001e5a: 2280 movs r2, #128 @ 0x80 8001e5c: 0052 lsls r2, r2, #1 8001e5e: 61da str r2, [r3, #28] } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8001e60: 697a ldr r2, [r7, #20] 8001e62: 2380 movs r3, #128 @ 0x80 8001e64: 00db lsls r3, r3, #3 8001e66: 4013 ands r3, r2 8001e68: d00e beq.n 8001e88 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001e6a: 693b ldr r3, [r7, #16] 8001e6c: 2280 movs r2, #128 @ 0x80 8001e6e: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8001e70: d00a beq.n 8001e88 { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; 8001e72: 687b ldr r3, [r7, #4] 8001e74: 6c5b ldr r3, [r3, #68] @ 0x44 8001e76: 2208 movs r2, #8 8001e78: 431a orrs r2, r3 8001e7a: 687b ldr r3, [r7, #4] 8001e7c: 645a str r2, [r3, #68] @ 0x44 /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 8001e7e: 687b ldr r3, [r7, #4] 8001e80: 681b ldr r3, [r3, #0] 8001e82: 2280 movs r2, #128 @ 0x80 8001e84: 00d2 lsls r2, r2, #3 8001e86: 61da str r2, [r3, #28] } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8001e88: 697a ldr r2, [r7, #20] 8001e8a: 2380 movs r3, #128 @ 0x80 8001e8c: 009b lsls r3, r3, #2 8001e8e: 4013 ands r3, r2 8001e90: d00e beq.n 8001eb0 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001e92: 693b ldr r3, [r7, #16] 8001e94: 2280 movs r2, #128 @ 0x80 8001e96: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8001e98: d00a beq.n 8001eb0 { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 6c5b ldr r3, [r3, #68] @ 0x44 8001e9e: 2202 movs r2, #2 8001ea0: 431a orrs r2, r3 8001ea2: 687b ldr r3, [r7, #4] 8001ea4: 645a str r2, [r3, #68] @ 0x44 /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 681b ldr r3, [r3, #0] 8001eaa: 2280 movs r2, #128 @ 0x80 8001eac: 0092 lsls r2, r2, #2 8001eae: 61da str r2, [r3, #28] } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 8001eb0: 687b ldr r3, [r7, #4] 8001eb2: 6c5b ldr r3, [r3, #68] @ 0x44 8001eb4: 60fb str r3, [r7, #12] /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) 8001eb6: 68fb ldr r3, [r7, #12] 8001eb8: 220b movs r2, #11 8001eba: 4013 ands r3, r2 8001ebc: d005 beq.n 8001eca { I2C_ITError(hi2c, tmperror); 8001ebe: 68fa ldr r2, [r7, #12] 8001ec0: 687b ldr r3, [r7, #4] 8001ec2: 0011 movs r1, r2 8001ec4: 0018 movs r0, r3 8001ec6: f000 fc1d bl 8002704 } } 8001eca: 46c0 nop @ (mov r8, r8) 8001ecc: 46bd mov sp, r7 8001ece: b006 add sp, #24 8001ed0: bd80 pop {r7, pc} 08001ed2 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8001ed2: b580 push {r7, lr} 8001ed4: b082 sub sp, #8 8001ed6: af00 add r7, sp, #0 8001ed8: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file */ } 8001eda: 46c0 nop @ (mov r8, r8) 8001edc: 46bd mov sp, r7 8001ede: b002 add sp, #8 8001ee0: bd80 pop {r7, pc} 08001ee2 : * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION * @param AddrMatchCode Address Match Code * @retval None */ __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { 8001ee2: b580 push {r7, lr} 8001ee4: b082 sub sp, #8 8001ee6: af00 add r7, sp, #0 8001ee8: 6078 str r0, [r7, #4] 8001eea: 0008 movs r0, r1 8001eec: 0011 movs r1, r2 8001eee: 1cfb adds r3, r7, #3 8001ef0: 1c02 adds r2, r0, #0 8001ef2: 701a strb r2, [r3, #0] 8001ef4: 003b movs r3, r7 8001ef6: 1c0a adds r2, r1, #0 8001ef8: 801a strh r2, [r3, #0] UNUSED(AddrMatchCode); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AddrCallback() could be implemented in the user file */ } 8001efa: 46c0 nop @ (mov r8, r8) 8001efc: 46bd mov sp, r7 8001efe: b002 add sp, #8 8001f00: bd80 pop {r7, pc} 08001f02 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { 8001f02: b580 push {r7, lr} 8001f04: b082 sub sp, #8 8001f06: af00 add r7, sp, #0 8001f08: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ListenCpltCallback() could be implemented in the user file */ } 8001f0a: 46c0 nop @ (mov r8, r8) 8001f0c: 46bd mov sp, r7 8001f0e: b002 add sp, #8 8001f10: bd80 pop {r7, pc} 08001f12 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { 8001f12: b580 push {r7, lr} 8001f14: b082 sub sp, #8 8001f16: af00 add r7, sp, #0 8001f18: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } 8001f1a: 46c0 nop @ (mov r8, r8) 8001f1c: 46bd mov sp, r7 8001f1e: b002 add sp, #8 8001f20: bd80 pop {r7, pc} 08001f22 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { 8001f22: b580 push {r7, lr} 8001f24: b082 sub sp, #8 8001f26: af00 add r7, sp, #0 8001f28: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } 8001f2a: 46c0 nop @ (mov r8, r8) 8001f2c: 46bd mov sp, r7 8001f2e: b002 add sp, #8 8001f30: bd80 pop {r7, pc} ... 08001f34 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8001f34: b580 push {r7, lr} 8001f36: b086 sub sp, #24 8001f38: af00 add r7, sp, #0 8001f3a: 60f8 str r0, [r7, #12] 8001f3c: 60b9 str r1, [r7, #8] 8001f3e: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8001f40: 68fb ldr r3, [r7, #12] 8001f42: 6adb ldr r3, [r3, #44] @ 0x2c 8001f44: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 8001f46: 68bb ldr r3, [r7, #8] 8001f48: 613b str r3, [r7, #16] /* Process locked */ __HAL_LOCK(hi2c); 8001f4a: 68fb ldr r3, [r7, #12] 8001f4c: 2240 movs r2, #64 @ 0x40 8001f4e: 5c9b ldrb r3, [r3, r2] 8001f50: 2b01 cmp r3, #1 8001f52: d101 bne.n 8001f58 8001f54: 2302 movs r3, #2 8001f56: e0e7 b.n 8002128 8001f58: 68fb ldr r3, [r7, #12] 8001f5a: 2240 movs r2, #64 @ 0x40 8001f5c: 2101 movs r1, #1 8001f5e: 5499 strb r1, [r3, r2] /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8001f60: 693b ldr r3, [r7, #16] 8001f62: 2220 movs r2, #32 8001f64: 4013 ands r3, r2 8001f66: d00a beq.n 8001f7e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8001f68: 687b ldr r3, [r7, #4] 8001f6a: 2220 movs r2, #32 8001f6c: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8001f6e: d006 beq.n 8001f7e { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); 8001f70: 693a ldr r2, [r7, #16] 8001f72: 68fb ldr r3, [r7, #12] 8001f74: 0011 movs r1, r2 8001f76: 0018 movs r0, r3 8001f78: f000 f9e4 bl 8002344 8001f7c: e0cf b.n 800211e } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8001f7e: 693b ldr r3, [r7, #16] 8001f80: 2210 movs r2, #16 8001f82: 4013 ands r3, r2 8001f84: d052 beq.n 800202c (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8001f86: 687b ldr r3, [r7, #4] 8001f88: 2210 movs r2, #16 8001f8a: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8001f8c: d04e beq.n 800202c { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8001f8e: 68fb ldr r3, [r7, #12] 8001f90: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001f92: b29b uxth r3, r3 8001f94: 2b00 cmp r3, #0 8001f96: d12d bne.n 8001ff4 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8001f98: 68fb ldr r3, [r7, #12] 8001f9a: 2241 movs r2, #65 @ 0x41 8001f9c: 5c9b ldrb r3, [r3, r2] 8001f9e: b2db uxtb r3, r3 8001fa0: 2b28 cmp r3, #40 @ 0x28 8001fa2: d10b bne.n 8001fbc 8001fa4: 697a ldr r2, [r7, #20] 8001fa6: 2380 movs r3, #128 @ 0x80 8001fa8: 049b lsls r3, r3, #18 8001faa: 429a cmp r2, r3 8001fac: d106 bne.n 8001fbc /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8001fae: 693a ldr r2, [r7, #16] 8001fb0: 68fb ldr r3, [r7, #12] 8001fb2: 0011 movs r1, r2 8001fb4: 0018 movs r0, r3 8001fb6: f000 fb4d bl 8002654 8001fba: e036 b.n 800202a } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8001fbc: 68fb ldr r3, [r7, #12] 8001fbe: 2241 movs r2, #65 @ 0x41 8001fc0: 5c9b ldrb r3, [r3, r2] 8001fc2: b2db uxtb r3, r3 8001fc4: 2b29 cmp r3, #41 @ 0x29 8001fc6: d110 bne.n 8001fea 8001fc8: 697b ldr r3, [r7, #20] 8001fca: 4a59 ldr r2, [pc, #356] @ (8002130 ) 8001fcc: 4293 cmp r3, r2 8001fce: d00c beq.n 8001fea { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001fd0: 68fb ldr r3, [r7, #12] 8001fd2: 681b ldr r3, [r3, #0] 8001fd4: 2210 movs r2, #16 8001fd6: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8001fd8: 68fb ldr r3, [r7, #12] 8001fda: 0018 movs r0, r3 8001fdc: f000 fcbd bl 800295a /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8001fe0: 68fb ldr r3, [r7, #12] 8001fe2: 0018 movs r0, r3 8001fe4: f000 f94a bl 800227c 8001fe8: e01f b.n 800202a } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001fea: 68fb ldr r3, [r7, #12] 8001fec: 681b ldr r3, [r3, #0] 8001fee: 2210 movs r2, #16 8001ff0: 61da str r2, [r3, #28] if (hi2c->XferCount == 0U) 8001ff2: e091 b.n 8002118 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001ff4: 68fb ldr r3, [r7, #12] 8001ff6: 681b ldr r3, [r3, #0] 8001ff8: 2210 movs r2, #16 8001ffa: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8001ffc: 68fb ldr r3, [r7, #12] 8001ffe: 6c5b ldr r3, [r3, #68] @ 0x44 8002000: 2204 movs r2, #4 8002002: 431a orrs r2, r3 8002004: 68fb ldr r3, [r7, #12] 8002006: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8002008: 697b ldr r3, [r7, #20] 800200a: 2b00 cmp r3, #0 800200c: d005 beq.n 800201a 800200e: 697a ldr r2, [r7, #20] 8002010: 2380 movs r3, #128 @ 0x80 8002012: 045b lsls r3, r3, #17 8002014: 429a cmp r2, r3 8002016: d000 beq.n 800201a 8002018: e07e b.n 8002118 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 800201a: 68fb ldr r3, [r7, #12] 800201c: 6c5a ldr r2, [r3, #68] @ 0x44 800201e: 68fb ldr r3, [r7, #12] 8002020: 0011 movs r1, r2 8002022: 0018 movs r0, r3 8002024: f000 fb6e bl 8002704 if (hi2c->XferCount == 0U) 8002028: e076 b.n 8002118 800202a: e075 b.n 8002118 } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 800202c: 693b ldr r3, [r7, #16] 800202e: 2204 movs r2, #4 8002030: 4013 ands r3, r2 8002032: d02f beq.n 8002094 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 8002034: 687b ldr r3, [r7, #4] 8002036: 2204 movs r2, #4 8002038: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 800203a: d02b beq.n 8002094 { if (hi2c->XferCount > 0U) 800203c: 68fb ldr r3, [r7, #12] 800203e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002040: b29b uxth r3, r3 8002042: 2b00 cmp r3, #0 8002044: d018 beq.n 8002078 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8002046: 68fb ldr r3, [r7, #12] 8002048: 681b ldr r3, [r3, #0] 800204a: 6a5a ldr r2, [r3, #36] @ 0x24 800204c: 68fb ldr r3, [r7, #12] 800204e: 6a5b ldr r3, [r3, #36] @ 0x24 8002050: b2d2 uxtb r2, r2 8002052: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002054: 68fb ldr r3, [r7, #12] 8002056: 6a5b ldr r3, [r3, #36] @ 0x24 8002058: 1c5a adds r2, r3, #1 800205a: 68fb ldr r3, [r7, #12] 800205c: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 800205e: 68fb ldr r3, [r7, #12] 8002060: 8d1b ldrh r3, [r3, #40] @ 0x28 8002062: 3b01 subs r3, #1 8002064: b29a uxth r2, r3 8002066: 68fb ldr r3, [r7, #12] 8002068: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 800206a: 68fb ldr r3, [r7, #12] 800206c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800206e: b29b uxth r3, r3 8002070: 3b01 subs r3, #1 8002072: b29a uxth r2, r3 8002074: 68fb ldr r3, [r7, #12] 8002076: 855a strh r2, [r3, #42] @ 0x2a } if ((hi2c->XferCount == 0U) && \ 8002078: 68fb ldr r3, [r7, #12] 800207a: 8d5b ldrh r3, [r3, #42] @ 0x2a 800207c: b29b uxth r3, r3 800207e: 2b00 cmp r3, #0 8002080: d14c bne.n 800211c 8002082: 697b ldr r3, [r7, #20] 8002084: 4a2a ldr r2, [pc, #168] @ (8002130 ) 8002086: 4293 cmp r3, r2 8002088: d048 beq.n 800211c (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800208a: 68fb ldr r3, [r7, #12] 800208c: 0018 movs r0, r3 800208e: f000 f8f5 bl 800227c if ((hi2c->XferCount == 0U) && \ 8002092: e043 b.n 800211c } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8002094: 693b ldr r3, [r7, #16] 8002096: 2208 movs r2, #8 8002098: 4013 ands r3, r2 800209a: d00a beq.n 80020b2 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 800209c: 687b ldr r3, [r7, #4] 800209e: 2208 movs r2, #8 80020a0: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 80020a2: d006 beq.n 80020b2 { I2C_ITAddrCplt(hi2c, tmpITFlags); 80020a4: 693a ldr r2, [r7, #16] 80020a6: 68fb ldr r3, [r7, #12] 80020a8: 0011 movs r1, r2 80020aa: 0018 movs r0, r3 80020ac: f000 f842 bl 8002134 80020b0: e035 b.n 800211e } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 80020b2: 693b ldr r3, [r7, #16] 80020b4: 2202 movs r2, #2 80020b6: 4013 ands r3, r2 80020b8: d031 beq.n 800211e (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 80020ba: 687b ldr r3, [r7, #4] 80020bc: 2202 movs r2, #2 80020be: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 80020c0: d02d beq.n 800211e { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) 80020c2: 68fb ldr r3, [r7, #12] 80020c4: 8d5b ldrh r3, [r3, #42] @ 0x2a 80020c6: b29b uxth r3, r3 80020c8: 2b00 cmp r3, #0 80020ca: d018 beq.n 80020fe { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 80020cc: 68fb ldr r3, [r7, #12] 80020ce: 6a5b ldr r3, [r3, #36] @ 0x24 80020d0: 781a ldrb r2, [r3, #0] 80020d2: 68fb ldr r3, [r7, #12] 80020d4: 681b ldr r3, [r3, #0] 80020d6: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 80020d8: 68fb ldr r3, [r7, #12] 80020da: 6a5b ldr r3, [r3, #36] @ 0x24 80020dc: 1c5a adds r2, r3, #1 80020de: 68fb ldr r3, [r7, #12] 80020e0: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 80020e2: 68fb ldr r3, [r7, #12] 80020e4: 8d5b ldrh r3, [r3, #42] @ 0x2a 80020e6: b29b uxth r3, r3 80020e8: 3b01 subs r3, #1 80020ea: b29a uxth r2, r3 80020ec: 68fb ldr r3, [r7, #12] 80020ee: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 80020f0: 68fb ldr r3, [r7, #12] 80020f2: 8d1b ldrh r3, [r3, #40] @ 0x28 80020f4: 3b01 subs r3, #1 80020f6: b29a uxth r2, r3 80020f8: 68fb ldr r3, [r7, #12] 80020fa: 851a strh r2, [r3, #40] @ 0x28 80020fc: e00f b.n 800211e } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) 80020fe: 697a ldr r2, [r7, #20] 8002100: 2380 movs r3, #128 @ 0x80 8002102: 045b lsls r3, r3, #17 8002104: 429a cmp r2, r3 8002106: d002 beq.n 800210e 8002108: 697b ldr r3, [r7, #20] 800210a: 2b00 cmp r3, #0 800210c: d107 bne.n 800211e { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 800210e: 68fb ldr r3, [r7, #12] 8002110: 0018 movs r0, r3 8002112: f000 f8b3 bl 800227c 8002116: e002 b.n 800211e if (hi2c->XferCount == 0U) 8002118: 46c0 nop @ (mov r8, r8) 800211a: e000 b.n 800211e if ((hi2c->XferCount == 0U) && \ 800211c: 46c0 nop @ (mov r8, r8) { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800211e: 68fb ldr r3, [r7, #12] 8002120: 2240 movs r2, #64 @ 0x40 8002122: 2100 movs r1, #0 8002124: 5499 strb r1, [r3, r2] return HAL_OK; 8002126: 2300 movs r3, #0 } 8002128: 0018 movs r0, r3 800212a: 46bd mov sp, r7 800212c: b006 add sp, #24 800212e: bd80 pop {r7, pc} 8002130: ffff0000 .word 0xffff0000 08002134 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8002134: b5b0 push {r4, r5, r7, lr} 8002136: b084 sub sp, #16 8002138: af00 add r7, sp, #0 800213a: 6078 str r0, [r7, #4] 800213c: 6039 str r1, [r7, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 800213e: 687b ldr r3, [r7, #4] 8002140: 2241 movs r2, #65 @ 0x41 8002142: 5c9b ldrb r3, [r3, r2] 8002144: b2db uxtb r3, r3 8002146: 001a movs r2, r3 8002148: 2328 movs r3, #40 @ 0x28 800214a: 4013 ands r3, r2 800214c: 2b28 cmp r3, #40 @ 0x28 800214e: d000 beq.n 8002152 8002150: e088 b.n 8002264 { transferdirection = I2C_GET_DIR(hi2c); 8002152: 687b ldr r3, [r7, #4] 8002154: 681b ldr r3, [r3, #0] 8002156: 699b ldr r3, [r3, #24] 8002158: 0c1b lsrs r3, r3, #16 800215a: b2da uxtb r2, r3 800215c: 250f movs r5, #15 800215e: 197b adds r3, r7, r5 8002160: 2101 movs r1, #1 8002162: 400a ands r2, r1 8002164: 701a strb r2, [r3, #0] slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); 8002166: 687b ldr r3, [r7, #4] 8002168: 681b ldr r3, [r3, #0] 800216a: 699b ldr r3, [r3, #24] 800216c: 0c1b lsrs r3, r3, #16 800216e: b29a uxth r2, r3 8002170: 200c movs r0, #12 8002172: 183b adds r3, r7, r0 8002174: 21fe movs r1, #254 @ 0xfe 8002176: 400a ands r2, r1 8002178: 801a strh r2, [r3, #0] ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); 800217a: 687b ldr r3, [r7, #4] 800217c: 681b ldr r3, [r3, #0] 800217e: 689b ldr r3, [r3, #8] 8002180: b29a uxth r2, r3 8002182: 240a movs r4, #10 8002184: 193b adds r3, r7, r4 8002186: 0592 lsls r2, r2, #22 8002188: 0d92 lsrs r2, r2, #22 800218a: 801a strh r2, [r3, #0] ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); 800218c: 687b ldr r3, [r7, #4] 800218e: 681b ldr r3, [r3, #0] 8002190: 68db ldr r3, [r3, #12] 8002192: b29a uxth r2, r3 8002194: 2308 movs r3, #8 8002196: 18fb adds r3, r7, r3 8002198: 21fe movs r1, #254 @ 0xfe 800219a: 400a ands r2, r1 800219c: 801a strh r2, [r3, #0] /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 800219e: 687b ldr r3, [r7, #4] 80021a0: 68db ldr r3, [r3, #12] 80021a2: 2b02 cmp r3, #2 80021a4: d148 bne.n 8002238 { if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) 80021a6: 0021 movs r1, r4 80021a8: 187b adds r3, r7, r1 80021aa: 881b ldrh r3, [r3, #0] 80021ac: 09db lsrs r3, r3, #7 80021ae: b29a uxth r2, r3 80021b0: 183b adds r3, r7, r0 80021b2: 881b ldrh r3, [r3, #0] 80021b4: 4053 eors r3, r2 80021b6: b29b uxth r3, r3 80021b8: 001a movs r2, r3 80021ba: 2306 movs r3, #6 80021bc: 4013 ands r3, r2 80021be: d120 bne.n 8002202 { slaveaddrcode = ownadd1code; 80021c0: 183b adds r3, r7, r0 80021c2: 187a adds r2, r7, r1 80021c4: 8812 ldrh r2, [r2, #0] 80021c6: 801a strh r2, [r3, #0] hi2c->AddrEventCount++; 80021c8: 687b ldr r3, [r7, #4] 80021ca: 6c9b ldr r3, [r3, #72] @ 0x48 80021cc: 1c5a adds r2, r3, #1 80021ce: 687b ldr r3, [r7, #4] 80021d0: 649a str r2, [r3, #72] @ 0x48 if (hi2c->AddrEventCount == 2U) 80021d2: 687b ldr r3, [r7, #4] 80021d4: 6c9b ldr r3, [r3, #72] @ 0x48 80021d6: 2b02 cmp r3, #2 80021d8: d14c bne.n 8002274 { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; 80021da: 687b ldr r3, [r7, #4] 80021dc: 2200 movs r2, #0 80021de: 649a str r2, [r3, #72] @ 0x48 /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 80021e0: 687b ldr r3, [r7, #4] 80021e2: 681b ldr r3, [r3, #0] 80021e4: 2208 movs r2, #8 80021e6: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80021e8: 687b ldr r3, [r7, #4] 80021ea: 2240 movs r2, #64 @ 0x40 80021ec: 2100 movs r1, #0 80021ee: 5499 strb r1, [r3, r2] /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 80021f0: 183b adds r3, r7, r0 80021f2: 881a ldrh r2, [r3, #0] 80021f4: 197b adds r3, r7, r5 80021f6: 7819 ldrb r1, [r3, #0] 80021f8: 687b ldr r3, [r7, #4] 80021fa: 0018 movs r0, r3 80021fc: f7ff fe71 bl 8001ee2 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } 8002200: e038 b.n 8002274 slaveaddrcode = ownadd2code; 8002202: 240c movs r4, #12 8002204: 193b adds r3, r7, r4 8002206: 2208 movs r2, #8 8002208: 18ba adds r2, r7, r2 800220a: 8812 ldrh r2, [r2, #0] 800220c: 801a strh r2, [r3, #0] I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 800220e: 2380 movs r3, #128 @ 0x80 8002210: 021a lsls r2, r3, #8 8002212: 687b ldr r3, [r7, #4] 8002214: 0011 movs r1, r2 8002216: 0018 movs r0, r3 8002218: f000 fbe0 bl 80029dc __HAL_UNLOCK(hi2c); 800221c: 687b ldr r3, [r7, #4] 800221e: 2240 movs r2, #64 @ 0x40 8002220: 2100 movs r1, #0 8002222: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8002224: 193b adds r3, r7, r4 8002226: 881a ldrh r2, [r3, #0] 8002228: 230f movs r3, #15 800222a: 18fb adds r3, r7, r3 800222c: 7819 ldrb r1, [r3, #0] 800222e: 687b ldr r3, [r7, #4] 8002230: 0018 movs r0, r3 8002232: f7ff fe56 bl 8001ee2 } 8002236: e01d b.n 8002274 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8002238: 2380 movs r3, #128 @ 0x80 800223a: 021a lsls r2, r3, #8 800223c: 687b ldr r3, [r7, #4] 800223e: 0011 movs r1, r2 8002240: 0018 movs r0, r3 8002242: f000 fbcb bl 80029dc __HAL_UNLOCK(hi2c); 8002246: 687b ldr r3, [r7, #4] 8002248: 2240 movs r2, #64 @ 0x40 800224a: 2100 movs r1, #0 800224c: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 800224e: 230c movs r3, #12 8002250: 18fb adds r3, r7, r3 8002252: 881a ldrh r2, [r3, #0] 8002254: 230f movs r3, #15 8002256: 18fb adds r3, r7, r3 8002258: 7819 ldrb r1, [r3, #0] 800225a: 687b ldr r3, [r7, #4] 800225c: 0018 movs r0, r3 800225e: f7ff fe40 bl 8001ee2 } 8002262: e007 b.n 8002274 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8002264: 687b ldr r3, [r7, #4] 8002266: 681b ldr r3, [r3, #0] 8002268: 2208 movs r2, #8 800226a: 61da str r2, [r3, #28] __HAL_UNLOCK(hi2c); 800226c: 687b ldr r3, [r7, #4] 800226e: 2240 movs r2, #64 @ 0x40 8002270: 2100 movs r1, #0 8002272: 5499 strb r1, [r3, r2] } 8002274: 46c0 nop @ (mov r8, r8) 8002276: 46bd mov sp, r7 8002278: b004 add sp, #16 800227a: bdb0 pop {r4, r5, r7, pc} 0800227c : * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { 800227c: b580 push {r7, lr} 800227e: b084 sub sp, #16 8002280: af00 add r7, sp, #0 8002282: 6078 str r0, [r7, #4] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 8002284: 687b ldr r3, [r7, #4] 8002286: 681b ldr r3, [r3, #0] 8002288: 681b ldr r3, [r3, #0] 800228a: 60fb str r3, [r7, #12] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 800228c: 687b ldr r3, [r7, #4] 800228e: 2242 movs r2, #66 @ 0x42 8002290: 2100 movs r1, #0 8002292: 5499 strb r1, [r3, r2] /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8002294: 68fa ldr r2, [r7, #12] 8002296: 2380 movs r3, #128 @ 0x80 8002298: 01db lsls r3, r3, #7 800229a: 4013 ands r3, r2 800229c: d008 beq.n 80022b0 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 800229e: 687b ldr r3, [r7, #4] 80022a0: 681b ldr r3, [r3, #0] 80022a2: 681a ldr r2, [r3, #0] 80022a4: 687b ldr r3, [r7, #4] 80022a6: 681b ldr r3, [r3, #0] 80022a8: 4924 ldr r1, [pc, #144] @ (800233c ) 80022aa: 400a ands r2, r1 80022ac: 601a str r2, [r3, #0] 80022ae: e00c b.n 80022ca } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80022b0: 68fa ldr r2, [r7, #12] 80022b2: 2380 movs r3, #128 @ 0x80 80022b4: 021b lsls r3, r3, #8 80022b6: 4013 ands r3, r2 80022b8: d007 beq.n 80022ca { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80022ba: 687b ldr r3, [r7, #4] 80022bc: 681b ldr r3, [r3, #0] 80022be: 681a ldr r2, [r3, #0] 80022c0: 687b ldr r3, [r7, #4] 80022c2: 681b ldr r3, [r3, #0] 80022c4: 491e ldr r1, [pc, #120] @ (8002340 ) 80022c6: 400a ands r2, r1 80022c8: 601a str r2, [r3, #0] else { /* Do nothing */ } if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 80022ca: 687b ldr r3, [r7, #4] 80022cc: 2241 movs r2, #65 @ 0x41 80022ce: 5c9b ldrb r3, [r3, r2] 80022d0: b2db uxtb r3, r3 80022d2: 2b29 cmp r3, #41 @ 0x29 80022d4: d114 bne.n 8002300 { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; 80022d6: 687b ldr r3, [r7, #4] 80022d8: 2241 movs r2, #65 @ 0x41 80022da: 2128 movs r1, #40 @ 0x28 80022dc: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 80022de: 687b ldr r3, [r7, #4] 80022e0: 2221 movs r2, #33 @ 0x21 80022e2: 631a str r2, [r3, #48] @ 0x30 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80022e4: 687b ldr r3, [r7, #4] 80022e6: 2101 movs r1, #1 80022e8: 0018 movs r0, r3 80022ea: f000 fb77 bl 80029dc /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80022ee: 687b ldr r3, [r7, #4] 80022f0: 2240 movs r2, #64 @ 0x40 80022f2: 2100 movs r1, #0 80022f4: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); 80022f6: 687b ldr r3, [r7, #4] 80022f8: 0018 movs r0, r3 80022fa: f7ff fdea bl 8001ed2 } else { /* Nothing to do */ } } 80022fe: e019 b.n 8002334 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 8002300: 687b ldr r3, [r7, #4] 8002302: 2241 movs r2, #65 @ 0x41 8002304: 5c9b ldrb r3, [r3, r2] 8002306: b2db uxtb r3, r3 8002308: 2b2a cmp r3, #42 @ 0x2a 800230a: d113 bne.n 8002334 hi2c->State = HAL_I2C_STATE_LISTEN; 800230c: 687b ldr r3, [r7, #4] 800230e: 2241 movs r2, #65 @ 0x41 8002310: 2128 movs r1, #40 @ 0x28 8002312: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8002314: 687b ldr r3, [r7, #4] 8002316: 2222 movs r2, #34 @ 0x22 8002318: 631a str r2, [r3, #48] @ 0x30 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 800231a: 687b ldr r3, [r7, #4] 800231c: 2102 movs r1, #2 800231e: 0018 movs r0, r3 8002320: f000 fb5c bl 80029dc __HAL_UNLOCK(hi2c); 8002324: 687b ldr r3, [r7, #4] 8002326: 2240 movs r2, #64 @ 0x40 8002328: 2100 movs r1, #0 800232a: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 800232c: 687b ldr r3, [r7, #4] 800232e: 0018 movs r0, r3 8002330: f7fe fe90 bl 8001054 } 8002334: 46c0 nop @ (mov r8, r8) 8002336: 46bd mov sp, r7 8002338: b004 add sp, #16 800233a: bd80 pop {r7, pc} 800233c: ffffbfff .word 0xffffbfff 8002340: ffff7fff .word 0xffff7fff 08002344 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8002344: b580 push {r7, lr} 8002346: b086 sub sp, #24 8002348: af00 add r7, sp, #0 800234a: 6078 str r0, [r7, #4] 800234c: 6039 str r1, [r7, #0] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 800234e: 687b ldr r3, [r7, #4] 8002350: 681b ldr r3, [r3, #0] 8002352: 681b ldr r3, [r3, #0] 8002354: 613b str r3, [r7, #16] uint32_t tmpITFlags = ITFlags; 8002356: 683b ldr r3, [r7, #0] 8002358: 617b str r3, [r7, #20] uint32_t tmpoptions = hi2c->XferOptions; 800235a: 687b ldr r3, [r7, #4] 800235c: 6adb ldr r3, [r3, #44] @ 0x2c 800235e: 60fb str r3, [r7, #12] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 8002360: 200b movs r0, #11 8002362: 183b adds r3, r7, r0 8002364: 687a ldr r2, [r7, #4] 8002366: 2141 movs r1, #65 @ 0x41 8002368: 5c52 ldrb r2, [r2, r1] 800236a: 701a strb r2, [r3, #0] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800236c: 687b ldr r3, [r7, #4] 800236e: 681b ldr r3, [r3, #0] 8002370: 2220 movs r2, #32 8002372: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8002374: 183b adds r3, r7, r0 8002376: 781b ldrb r3, [r3, #0] 8002378: 2b21 cmp r3, #33 @ 0x21 800237a: d003 beq.n 8002384 800237c: 183b adds r3, r7, r0 800237e: 781b ldrb r3, [r3, #0] 8002380: 2b29 cmp r3, #41 @ 0x29 8002382: d109 bne.n 8002398 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 8002384: 4aac ldr r2, [pc, #688] @ (8002638 ) 8002386: 687b ldr r3, [r7, #4] 8002388: 0011 movs r1, r2 800238a: 0018 movs r0, r3 800238c: f000 fb26 bl 80029dc hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8002390: 687b ldr r3, [r7, #4] 8002392: 2221 movs r2, #33 @ 0x21 8002394: 631a str r2, [r3, #48] @ 0x30 8002396: e020 b.n 80023da } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 8002398: 220b movs r2, #11 800239a: 18bb adds r3, r7, r2 800239c: 781b ldrb r3, [r3, #0] 800239e: 2b22 cmp r3, #34 @ 0x22 80023a0: d003 beq.n 80023aa 80023a2: 18bb adds r3, r7, r2 80023a4: 781b ldrb r3, [r3, #0] 80023a6: 2b2a cmp r3, #42 @ 0x2a 80023a8: d109 bne.n 80023be { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 80023aa: 4aa4 ldr r2, [pc, #656] @ (800263c ) 80023ac: 687b ldr r3, [r7, #4] 80023ae: 0011 movs r1, r2 80023b0: 0018 movs r0, r3 80023b2: f000 fb13 bl 80029dc hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 80023b6: 687b ldr r3, [r7, #4] 80023b8: 2222 movs r2, #34 @ 0x22 80023ba: 631a str r2, [r3, #48] @ 0x30 80023bc: e00d b.n 80023da } else if (tmpstate == HAL_I2C_STATE_LISTEN) 80023be: 230b movs r3, #11 80023c0: 18fb adds r3, r7, r3 80023c2: 781b ldrb r3, [r3, #0] 80023c4: 2b28 cmp r3, #40 @ 0x28 80023c6: d108 bne.n 80023da { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); 80023c8: 4a9d ldr r2, [pc, #628] @ (8002640 ) 80023ca: 687b ldr r3, [r7, #4] 80023cc: 0011 movs r1, r2 80023ce: 0018 movs r0, r3 80023d0: f000 fb04 bl 80029dc hi2c->PreviousState = I2C_STATE_NONE; 80023d4: 687b ldr r3, [r7, #4] 80023d6: 2200 movs r2, #0 80023d8: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 80023da: 687b ldr r3, [r7, #4] 80023dc: 681b ldr r3, [r3, #0] 80023de: 685a ldr r2, [r3, #4] 80023e0: 687b ldr r3, [r7, #4] 80023e2: 681b ldr r3, [r3, #0] 80023e4: 2180 movs r1, #128 @ 0x80 80023e6: 0209 lsls r1, r1, #8 80023e8: 430a orrs r2, r1 80023ea: 605a str r2, [r3, #4] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 80023ec: 687b ldr r3, [r7, #4] 80023ee: 681b ldr r3, [r3, #0] 80023f0: 685a ldr r2, [r3, #4] 80023f2: 687b ldr r3, [r7, #4] 80023f4: 681b ldr r3, [r3, #0] 80023f6: 4993 ldr r1, [pc, #588] @ (8002644 ) 80023f8: 400a ands r2, r1 80023fa: 605a str r2, [r3, #4] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80023fc: 687b ldr r3, [r7, #4] 80023fe: 0018 movs r0, r3 8002400: f000 faab bl 800295a /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8002404: 693a ldr r2, [r7, #16] 8002406: 2380 movs r3, #128 @ 0x80 8002408: 01db lsls r3, r3, #7 800240a: 4013 ands r3, r2 800240c: d013 beq.n 8002436 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 800240e: 687b ldr r3, [r7, #4] 8002410: 681b ldr r3, [r3, #0] 8002412: 681a ldr r2, [r3, #0] 8002414: 687b ldr r3, [r7, #4] 8002416: 681b ldr r3, [r3, #0] 8002418: 498b ldr r1, [pc, #556] @ (8002648 ) 800241a: 400a ands r2, r1 800241c: 601a str r2, [r3, #0] if (hi2c->hdmatx != NULL) 800241e: 687b ldr r3, [r7, #4] 8002420: 6b9b ldr r3, [r3, #56] @ 0x38 8002422: 2b00 cmp r3, #0 8002424: d01f beq.n 8002466 { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); 8002426: 687b ldr r3, [r7, #4] 8002428: 6b9b ldr r3, [r3, #56] @ 0x38 800242a: 681b ldr r3, [r3, #0] 800242c: 685b ldr r3, [r3, #4] 800242e: b29a uxth r2, r3 8002430: 687b ldr r3, [r7, #4] 8002432: 855a strh r2, [r3, #42] @ 0x2a 8002434: e017 b.n 8002466 } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 8002436: 693a ldr r2, [r7, #16] 8002438: 2380 movs r3, #128 @ 0x80 800243a: 021b lsls r3, r3, #8 800243c: 4013 ands r3, r2 800243e: d012 beq.n 8002466 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8002440: 687b ldr r3, [r7, #4] 8002442: 681b ldr r3, [r3, #0] 8002444: 681a ldr r2, [r3, #0] 8002446: 687b ldr r3, [r7, #4] 8002448: 681b ldr r3, [r3, #0] 800244a: 4980 ldr r1, [pc, #512] @ (800264c ) 800244c: 400a ands r2, r1 800244e: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 8002450: 687b ldr r3, [r7, #4] 8002452: 6bdb ldr r3, [r3, #60] @ 0x3c 8002454: 2b00 cmp r3, #0 8002456: d006 beq.n 8002466 { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); 8002458: 687b ldr r3, [r7, #4] 800245a: 6bdb ldr r3, [r3, #60] @ 0x3c 800245c: 681b ldr r3, [r3, #0] 800245e: 685b ldr r3, [r3, #4] 8002460: b29a uxth r2, r3 8002462: 687b ldr r3, [r7, #4] 8002464: 855a strh r2, [r3, #42] @ 0x2a { /* Do nothing */ } /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) 8002466: 697b ldr r3, [r7, #20] 8002468: 2204 movs r2, #4 800246a: 4013 ands r3, r2 800246c: d020 beq.n 80024b0 { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 800246e: 697b ldr r3, [r7, #20] 8002470: 2204 movs r2, #4 8002472: 4393 bics r3, r2 8002474: 617b str r3, [r7, #20] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8002476: 687b ldr r3, [r7, #4] 8002478: 681b ldr r3, [r3, #0] 800247a: 6a5a ldr r2, [r3, #36] @ 0x24 800247c: 687b ldr r3, [r7, #4] 800247e: 6a5b ldr r3, [r3, #36] @ 0x24 8002480: b2d2 uxtb r2, r2 8002482: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002484: 687b ldr r3, [r7, #4] 8002486: 6a5b ldr r3, [r3, #36] @ 0x24 8002488: 1c5a adds r2, r3, #1 800248a: 687b ldr r3, [r7, #4] 800248c: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 800248e: 687b ldr r3, [r7, #4] 8002490: 8d1b ldrh r3, [r3, #40] @ 0x28 8002492: 2b00 cmp r3, #0 8002494: d00c beq.n 80024b0 { hi2c->XferSize--; 8002496: 687b ldr r3, [r7, #4] 8002498: 8d1b ldrh r3, [r3, #40] @ 0x28 800249a: 3b01 subs r3, #1 800249c: b29a uxth r2, r3 800249e: 687b ldr r3, [r7, #4] 80024a0: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 80024a2: 687b ldr r3, [r7, #4] 80024a4: 8d5b ldrh r3, [r3, #42] @ 0x2a 80024a6: b29b uxth r3, r3 80024a8: 3b01 subs r3, #1 80024aa: b29a uxth r2, r3 80024ac: 687b ldr r3, [r7, #4] 80024ae: 855a strh r2, [r3, #42] @ 0x2a } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) 80024b0: 687b ldr r3, [r7, #4] 80024b2: 8d5b ldrh r3, [r3, #42] @ 0x2a 80024b4: b29b uxth r3, r3 80024b6: 2b00 cmp r3, #0 80024b8: d005 beq.n 80024c6 { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80024ba: 687b ldr r3, [r7, #4] 80024bc: 6c5b ldr r3, [r3, #68] @ 0x44 80024be: 2204 movs r2, #4 80024c0: 431a orrs r2, r3 80024c2: 687b ldr r3, [r7, #4] 80024c4: 645a str r2, [r3, #68] @ 0x44 } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 80024c6: 697b ldr r3, [r7, #20] 80024c8: 2210 movs r2, #16 80024ca: 4013 ands r3, r2 80024cc: d04f beq.n 800256e (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) 80024ce: 693b ldr r3, [r7, #16] 80024d0: 2210 movs r2, #16 80024d2: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 80024d4: d04b beq.n 800256e { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 80024d6: 687b ldr r3, [r7, #4] 80024d8: 8d5b ldrh r3, [r3, #42] @ 0x2a 80024da: b29b uxth r3, r3 80024dc: 2b00 cmp r3, #0 80024de: d12d bne.n 800253c { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 80024e0: 687b ldr r3, [r7, #4] 80024e2: 2241 movs r2, #65 @ 0x41 80024e4: 5c9b ldrb r3, [r3, r2] 80024e6: b2db uxtb r3, r3 80024e8: 2b28 cmp r3, #40 @ 0x28 80024ea: d10b bne.n 8002504 80024ec: 68fa ldr r2, [r7, #12] 80024ee: 2380 movs r3, #128 @ 0x80 80024f0: 049b lsls r3, r3, #18 80024f2: 429a cmp r2, r3 80024f4: d106 bne.n 8002504 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 80024f6: 697a ldr r2, [r7, #20] 80024f8: 687b ldr r3, [r7, #4] 80024fa: 0011 movs r1, r2 80024fc: 0018 movs r0, r3 80024fe: f000 f8a9 bl 8002654 8002502: e034 b.n 800256e } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8002504: 687b ldr r3, [r7, #4] 8002506: 2241 movs r2, #65 @ 0x41 8002508: 5c9b ldrb r3, [r3, r2] 800250a: b2db uxtb r3, r3 800250c: 2b29 cmp r3, #41 @ 0x29 800250e: d110 bne.n 8002532 8002510: 68fb ldr r3, [r7, #12] 8002512: 4a4f ldr r2, [pc, #316] @ (8002650 ) 8002514: 4293 cmp r3, r2 8002516: d00c beq.n 8002532 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002518: 687b ldr r3, [r7, #4] 800251a: 681b ldr r3, [r3, #0] 800251c: 2210 movs r2, #16 800251e: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8002520: 687b ldr r3, [r7, #4] 8002522: 0018 movs r0, r3 8002524: f000 fa19 bl 800295a /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8002528: 687b ldr r3, [r7, #4] 800252a: 0018 movs r0, r3 800252c: f7ff fea6 bl 800227c 8002530: e01d b.n 800256e } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002532: 687b ldr r3, [r7, #4] 8002534: 681b ldr r3, [r3, #0] 8002536: 2210 movs r2, #16 8002538: 61da str r2, [r3, #28] 800253a: e018 b.n 800256e } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 800253c: 687b ldr r3, [r7, #4] 800253e: 681b ldr r3, [r3, #0] 8002540: 2210 movs r2, #16 8002542: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8002544: 687b ldr r3, [r7, #4] 8002546: 6c5b ldr r3, [r3, #68] @ 0x44 8002548: 2204 movs r2, #4 800254a: 431a orrs r2, r3 800254c: 687b ldr r3, [r7, #4] 800254e: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8002550: 68fb ldr r3, [r7, #12] 8002552: 2b00 cmp r3, #0 8002554: d004 beq.n 8002560 8002556: 68fa ldr r2, [r7, #12] 8002558: 2380 movs r3, #128 @ 0x80 800255a: 045b lsls r3, r3, #17 800255c: 429a cmp r2, r3 800255e: d106 bne.n 800256e { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002560: 687b ldr r3, [r7, #4] 8002562: 6c5a ldr r2, [r3, #68] @ 0x44 8002564: 687b ldr r3, [r7, #4] 8002566: 0011 movs r1, r2 8002568: 0018 movs r0, r3 800256a: f000 f8cb bl 8002704 } } } hi2c->Mode = HAL_I2C_MODE_NONE; 800256e: 687b ldr r3, [r7, #4] 8002570: 2242 movs r2, #66 @ 0x42 8002572: 2100 movs r1, #0 8002574: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 8002576: 687b ldr r3, [r7, #4] 8002578: 2200 movs r2, #0 800257a: 635a str r2, [r3, #52] @ 0x34 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 800257c: 687b ldr r3, [r7, #4] 800257e: 6c5b ldr r3, [r3, #68] @ 0x44 8002580: 2b00 cmp r3, #0 8002582: d013 beq.n 80025ac { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002584: 687b ldr r3, [r7, #4] 8002586: 6c5a ldr r2, [r3, #68] @ 0x44 8002588: 687b ldr r3, [r7, #4] 800258a: 0011 movs r1, r2 800258c: 0018 movs r0, r3 800258e: f000 f8b9 bl 8002704 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) 8002592: 687b ldr r3, [r7, #4] 8002594: 2241 movs r2, #65 @ 0x41 8002596: 5c9b ldrb r3, [r3, r2] 8002598: b2db uxtb r3, r3 800259a: 2b28 cmp r3, #40 @ 0x28 800259c: d147 bne.n 800262e { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 800259e: 697a ldr r2, [r7, #20] 80025a0: 687b ldr r3, [r7, #4] 80025a2: 0011 movs r1, r2 80025a4: 0018 movs r0, r3 80025a6: f000 f855 bl 8002654 hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 80025aa: e040 b.n 800262e else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 80025ac: 687b ldr r3, [r7, #4] 80025ae: 6adb ldr r3, [r3, #44] @ 0x2c 80025b0: 4a27 ldr r2, [pc, #156] @ (8002650 ) 80025b2: 4293 cmp r3, r2 80025b4: d016 beq.n 80025e4 I2C_ITSlaveSeqCplt(hi2c); 80025b6: 687b ldr r3, [r7, #4] 80025b8: 0018 movs r0, r3 80025ba: f7ff fe5f bl 800227c hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80025be: 687b ldr r3, [r7, #4] 80025c0: 4a23 ldr r2, [pc, #140] @ (8002650 ) 80025c2: 62da str r2, [r3, #44] @ 0x2c hi2c->State = HAL_I2C_STATE_READY; 80025c4: 687b ldr r3, [r7, #4] 80025c6: 2241 movs r2, #65 @ 0x41 80025c8: 2120 movs r1, #32 80025ca: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 80025cc: 687b ldr r3, [r7, #4] 80025ce: 2200 movs r2, #0 80025d0: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80025d2: 687b ldr r3, [r7, #4] 80025d4: 2240 movs r2, #64 @ 0x40 80025d6: 2100 movs r1, #0 80025d8: 5499 strb r1, [r3, r2] HAL_I2C_ListenCpltCallback(hi2c); 80025da: 687b ldr r3, [r7, #4] 80025dc: 0018 movs r0, r3 80025de: f7ff fc90 bl 8001f02 } 80025e2: e024 b.n 800262e else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80025e4: 687b ldr r3, [r7, #4] 80025e6: 2241 movs r2, #65 @ 0x41 80025e8: 5c9b ldrb r3, [r3, r2] 80025ea: b2db uxtb r3, r3 80025ec: 2b22 cmp r3, #34 @ 0x22 80025ee: d10f bne.n 8002610 hi2c->State = HAL_I2C_STATE_READY; 80025f0: 687b ldr r3, [r7, #4] 80025f2: 2241 movs r2, #65 @ 0x41 80025f4: 2120 movs r1, #32 80025f6: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 80025f8: 687b ldr r3, [r7, #4] 80025fa: 2200 movs r2, #0 80025fc: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 80025fe: 687b ldr r3, [r7, #4] 8002600: 2240 movs r2, #64 @ 0x40 8002602: 2100 movs r1, #0 8002604: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 8002606: 687b ldr r3, [r7, #4] 8002608: 0018 movs r0, r3 800260a: f7fe fd23 bl 8001054 } 800260e: e00e b.n 800262e hi2c->State = HAL_I2C_STATE_READY; 8002610: 687b ldr r3, [r7, #4] 8002612: 2241 movs r2, #65 @ 0x41 8002614: 2120 movs r1, #32 8002616: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002618: 687b ldr r3, [r7, #4] 800261a: 2200 movs r2, #0 800261c: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 800261e: 687b ldr r3, [r7, #4] 8002620: 2240 movs r2, #64 @ 0x40 8002622: 2100 movs r1, #0 8002624: 5499 strb r1, [r3, r2] HAL_I2C_SlaveTxCpltCallback(hi2c); 8002626: 687b ldr r3, [r7, #4] 8002628: 0018 movs r0, r3 800262a: f7ff fc52 bl 8001ed2 } 800262e: 46c0 nop @ (mov r8, r8) 8002630: 46bd mov sp, r7 8002632: b006 add sp, #24 8002634: bd80 pop {r7, pc} 8002636: 46c0 nop @ (mov r8, r8) 8002638: 00008001 .word 0x00008001 800263c: 00008002 .word 0x00008002 8002640: 00008003 .word 0x00008003 8002644: fe00e800 .word 0xfe00e800 8002648: ffffbfff .word 0xffffbfff 800264c: ffff7fff .word 0xffff7fff 8002650: ffff0000 .word 0xffff0000 08002654 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8002654: b580 push {r7, lr} 8002656: b082 sub sp, #8 8002658: af00 add r7, sp, #0 800265a: 6078 str r0, [r7, #4] 800265c: 6039 str r1, [r7, #0] /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; 800265e: 687b ldr r3, [r7, #4] 8002660: 4a26 ldr r2, [pc, #152] @ (80026fc ) 8002662: 62da str r2, [r3, #44] @ 0x2c hi2c->PreviousState = I2C_STATE_NONE; 8002664: 687b ldr r3, [r7, #4] 8002666: 2200 movs r2, #0 8002668: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 800266a: 687b ldr r3, [r7, #4] 800266c: 2241 movs r2, #65 @ 0x41 800266e: 2120 movs r1, #32 8002670: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8002672: 687b ldr r3, [r7, #4] 8002674: 2242 movs r2, #66 @ 0x42 8002676: 2100 movs r1, #0 8002678: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 800267a: 687b ldr r3, [r7, #4] 800267c: 2200 movs r2, #0 800267e: 635a str r2, [r3, #52] @ 0x34 /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) 8002680: 683b ldr r3, [r7, #0] 8002682: 2204 movs r2, #4 8002684: 4013 ands r3, r2 8002686: d022 beq.n 80026ce { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8002688: 687b ldr r3, [r7, #4] 800268a: 681b ldr r3, [r3, #0] 800268c: 6a5a ldr r2, [r3, #36] @ 0x24 800268e: 687b ldr r3, [r7, #4] 8002690: 6a5b ldr r3, [r3, #36] @ 0x24 8002692: b2d2 uxtb r2, r2 8002694: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002696: 687b ldr r3, [r7, #4] 8002698: 6a5b ldr r3, [r3, #36] @ 0x24 800269a: 1c5a adds r2, r3, #1 800269c: 687b ldr r3, [r7, #4] 800269e: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 80026a0: 687b ldr r3, [r7, #4] 80026a2: 8d1b ldrh r3, [r3, #40] @ 0x28 80026a4: 2b00 cmp r3, #0 80026a6: d012 beq.n 80026ce { hi2c->XferSize--; 80026a8: 687b ldr r3, [r7, #4] 80026aa: 8d1b ldrh r3, [r3, #40] @ 0x28 80026ac: 3b01 subs r3, #1 80026ae: b29a uxth r2, r3 80026b0: 687b ldr r3, [r7, #4] 80026b2: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 80026b4: 687b ldr r3, [r7, #4] 80026b6: 8d5b ldrh r3, [r3, #42] @ 0x2a 80026b8: b29b uxth r3, r3 80026ba: 3b01 subs r3, #1 80026bc: b29a uxth r2, r3 80026be: 687b ldr r3, [r7, #4] 80026c0: 855a strh r2, [r3, #42] @ 0x2a /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80026c2: 687b ldr r3, [r7, #4] 80026c4: 6c5b ldr r3, [r3, #68] @ 0x44 80026c6: 2204 movs r2, #4 80026c8: 431a orrs r2, r3 80026ca: 687b ldr r3, [r7, #4] 80026cc: 645a str r2, [r3, #68] @ 0x44 } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 80026ce: 4a0c ldr r2, [pc, #48] @ (8002700 ) 80026d0: 687b ldr r3, [r7, #4] 80026d2: 0011 movs r1, r2 80026d4: 0018 movs r0, r3 80026d6: f000 f981 bl 80029dc /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80026da: 687b ldr r3, [r7, #4] 80026dc: 681b ldr r3, [r3, #0] 80026de: 2210 movs r2, #16 80026e0: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80026e2: 687b ldr r3, [r7, #4] 80026e4: 2240 movs r2, #64 @ 0x40 80026e6: 2100 movs r1, #0 80026e8: 5499 strb r1, [r3, r2] /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); 80026ea: 687b ldr r3, [r7, #4] 80026ec: 0018 movs r0, r3 80026ee: f7ff fc08 bl 8001f02 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } 80026f2: 46c0 nop @ (mov r8, r8) 80026f4: 46bd mov sp, r7 80026f6: b002 add sp, #8 80026f8: bd80 pop {r7, pc} 80026fa: 46c0 nop @ (mov r8, r8) 80026fc: ffff0000 .word 0xffff0000 8002700: 00008003 .word 0x00008003 08002704 : * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { 8002704: b580 push {r7, lr} 8002706: b084 sub sp, #16 8002708: af00 add r7, sp, #0 800270a: 6078 str r0, [r7, #4] 800270c: 6039 str r1, [r7, #0] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 800270e: 200f movs r0, #15 8002710: 183b adds r3, r7, r0 8002712: 687a ldr r2, [r7, #4] 8002714: 2141 movs r1, #65 @ 0x41 8002716: 5c52 ldrb r2, [r2, r1] 8002718: 701a strb r2, [r3, #0] uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; 800271a: 687b ldr r3, [r7, #4] 800271c: 2242 movs r2, #66 @ 0x42 800271e: 2100 movs r1, #0 8002720: 5499 strb r1, [r3, r2] hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002722: 687b ldr r3, [r7, #4] 8002724: 4a72 ldr r2, [pc, #456] @ (80028f0 ) 8002726: 62da str r2, [r3, #44] @ 0x2c hi2c->XferCount = 0U; 8002728: 687b ldr r3, [r7, #4] 800272a: 2200 movs r2, #0 800272c: 855a strh r2, [r3, #42] @ 0x2a /* Set new error code */ hi2c->ErrorCode |= ErrorCode; 800272e: 687b ldr r3, [r7, #4] 8002730: 6c5a ldr r2, [r3, #68] @ 0x44 8002732: 683b ldr r3, [r7, #0] 8002734: 431a orrs r2, r3 8002736: 687b ldr r3, [r7, #4] 8002738: 645a str r2, [r3, #68] @ 0x44 /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || 800273a: 183b adds r3, r7, r0 800273c: 781b ldrb r3, [r3, #0] 800273e: 2b28 cmp r3, #40 @ 0x28 8002740: d007 beq.n 8002752 8002742: 183b adds r3, r7, r0 8002744: 781b ldrb r3, [r3, #0] 8002746: 2b29 cmp r3, #41 @ 0x29 8002748: d003 beq.n 8002752 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || 800274a: 183b adds r3, r7, r0 800274c: 781b ldrb r3, [r3, #0] 800274e: 2b2a cmp r3, #42 @ 0x2a 8002750: d10c bne.n 800276c (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8002752: 687b ldr r3, [r7, #4] 8002754: 2103 movs r1, #3 8002756: 0018 movs r0, r3 8002758: f000 f940 bl 80029dc /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; 800275c: 687b ldr r3, [r7, #4] 800275e: 2241 movs r2, #65 @ 0x41 8002760: 2128 movs r1, #40 @ 0x28 8002762: 5499 strb r1, [r3, r2] hi2c->XferISR = I2C_Slave_ISR_IT; 8002764: 687b ldr r3, [r7, #4] 8002766: 4a63 ldr r2, [pc, #396] @ (80028f4 ) 8002768: 635a str r2, [r3, #52] @ 0x34 800276a: e032 b.n 80027d2 } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 800276c: 4a62 ldr r2, [pc, #392] @ (80028f8 ) 800276e: 687b ldr r3, [r7, #4] 8002770: 0011 movs r1, r2 8002772: 0018 movs r0, r3 8002774: f000 f932 bl 80029dc /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8002778: 687b ldr r3, [r7, #4] 800277a: 0018 movs r0, r3 800277c: f000 f8ed bl 800295a /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) 8002780: 687b ldr r3, [r7, #4] 8002782: 2241 movs r2, #65 @ 0x41 8002784: 5c9b ldrb r3, [r3, r2] 8002786: b2db uxtb r3, r3 8002788: 2b60 cmp r3, #96 @ 0x60 800278a: d01f beq.n 80027cc { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; 800278c: 687b ldr r3, [r7, #4] 800278e: 2241 movs r2, #65 @ 0x41 8002790: 2120 movs r1, #32 8002792: 5499 strb r1, [r3, r2] /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 8002794: 687b ldr r3, [r7, #4] 8002796: 681b ldr r3, [r3, #0] 8002798: 699b ldr r3, [r3, #24] 800279a: 2220 movs r2, #32 800279c: 4013 ands r3, r2 800279e: 2b20 cmp r3, #32 80027a0: d114 bne.n 80027cc { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 80027a2: 687b ldr r3, [r7, #4] 80027a4: 681b ldr r3, [r3, #0] 80027a6: 699b ldr r3, [r3, #24] 80027a8: 2210 movs r2, #16 80027aa: 4013 ands r3, r2 80027ac: 2b10 cmp r3, #16 80027ae: d109 bne.n 80027c4 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80027b0: 687b ldr r3, [r7, #4] 80027b2: 681b ldr r3, [r3, #0] 80027b4: 2210 movs r2, #16 80027b6: 61da str r2, [r3, #28] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80027b8: 687b ldr r3, [r7, #4] 80027ba: 6c5b ldr r3, [r3, #68] @ 0x44 80027bc: 2204 movs r2, #4 80027be: 431a orrs r2, r3 80027c0: 687b ldr r3, [r7, #4] 80027c2: 645a str r2, [r3, #68] @ 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 80027c4: 687b ldr r3, [r7, #4] 80027c6: 681b ldr r3, [r3, #0] 80027c8: 2220 movs r2, #32 80027ca: 61da str r2, [r3, #28] } } hi2c->XferISR = NULL; 80027cc: 687b ldr r3, [r7, #4] 80027ce: 2200 movs r2, #0 80027d0: 635a str r2, [r3, #52] @ 0x34 } /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; 80027d2: 687b ldr r3, [r7, #4] 80027d4: 6b1b ldr r3, [r3, #48] @ 0x30 80027d6: 60bb str r3, [r7, #8] if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ 80027d8: 687b ldr r3, [r7, #4] 80027da: 6b9b ldr r3, [r3, #56] @ 0x38 80027dc: 2b00 cmp r3, #0 80027de: d03b beq.n 8002858 80027e0: 68bb ldr r3, [r7, #8] 80027e2: 2b11 cmp r3, #17 80027e4: d002 beq.n 80027ec 80027e6: 68bb ldr r3, [r7, #8] 80027e8: 2b21 cmp r3, #33 @ 0x21 80027ea: d135 bne.n 8002858 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 80027ec: 687b ldr r3, [r7, #4] 80027ee: 681b ldr r3, [r3, #0] 80027f0: 681a ldr r2, [r3, #0] 80027f2: 2380 movs r3, #128 @ 0x80 80027f4: 01db lsls r3, r3, #7 80027f6: 401a ands r2, r3 80027f8: 2380 movs r3, #128 @ 0x80 80027fa: 01db lsls r3, r3, #7 80027fc: 429a cmp r2, r3 80027fe: d107 bne.n 8002810 { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8002800: 687b ldr r3, [r7, #4] 8002802: 681b ldr r3, [r3, #0] 8002804: 681a ldr r2, [r3, #0] 8002806: 687b ldr r3, [r7, #4] 8002808: 681b ldr r3, [r3, #0] 800280a: 493c ldr r1, [pc, #240] @ (80028fc ) 800280c: 400a ands r2, r1 800280e: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002810: 687b ldr r3, [r7, #4] 8002812: 6b9b ldr r3, [r3, #56] @ 0x38 8002814: 0018 movs r0, r3 8002816: f7ff f8b5 bl 8001984 800281a: 0003 movs r3, r0 800281c: 2b01 cmp r3, #1 800281e: d016 beq.n 800284e { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 8002820: 687b ldr r3, [r7, #4] 8002822: 6b9b ldr r3, [r3, #56] @ 0x38 8002824: 4a36 ldr r2, [pc, #216] @ (8002900 ) 8002826: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002828: 687b ldr r3, [r7, #4] 800282a: 2240 movs r2, #64 @ 0x40 800282c: 2100 movs r1, #0 800282e: 5499 strb r1, [r3, r2] /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 8002830: 687b ldr r3, [r7, #4] 8002832: 6b9b ldr r3, [r3, #56] @ 0x38 8002834: 0018 movs r0, r3 8002836: f7ff f83b bl 80018b0 800283a: 1e03 subs r3, r0, #0 800283c: d051 beq.n 80028e2 { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 800283e: 687b ldr r3, [r7, #4] 8002840: 6b9b ldr r3, [r3, #56] @ 0x38 8002842: 6b9a ldr r2, [r3, #56] @ 0x38 8002844: 687b ldr r3, [r7, #4] 8002846: 6b9b ldr r3, [r3, #56] @ 0x38 8002848: 0018 movs r0, r3 800284a: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 800284c: e049 b.n 80028e2 } } else { I2C_TreatErrorCallback(hi2c); 800284e: 687b ldr r3, [r7, #4] 8002850: 0018 movs r0, r3 8002852: f000 f859 bl 8002908 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002856: e044 b.n 80028e2 } } /* Abort DMA RX transfer if any */ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ 8002858: 687b ldr r3, [r7, #4] 800285a: 6bdb ldr r3, [r3, #60] @ 0x3c 800285c: 2b00 cmp r3, #0 800285e: d03b beq.n 80028d8 8002860: 68bb ldr r3, [r7, #8] 8002862: 2b12 cmp r3, #18 8002864: d002 beq.n 800286c 8002866: 68bb ldr r3, [r7, #8] 8002868: 2b22 cmp r3, #34 @ 0x22 800286a: d135 bne.n 80028d8 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 800286c: 687b ldr r3, [r7, #4] 800286e: 681b ldr r3, [r3, #0] 8002870: 681a ldr r2, [r3, #0] 8002872: 2380 movs r3, #128 @ 0x80 8002874: 021b lsls r3, r3, #8 8002876: 401a ands r2, r3 8002878: 2380 movs r3, #128 @ 0x80 800287a: 021b lsls r3, r3, #8 800287c: 429a cmp r2, r3 800287e: d107 bne.n 8002890 { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8002880: 687b ldr r3, [r7, #4] 8002882: 681b ldr r3, [r3, #0] 8002884: 681a ldr r2, [r3, #0] 8002886: 687b ldr r3, [r7, #4] 8002888: 681b ldr r3, [r3, #0] 800288a: 491e ldr r1, [pc, #120] @ (8002904 ) 800288c: 400a ands r2, r1 800288e: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8002890: 687b ldr r3, [r7, #4] 8002892: 6bdb ldr r3, [r3, #60] @ 0x3c 8002894: 0018 movs r0, r3 8002896: f7ff f875 bl 8001984 800289a: 0003 movs r3, r0 800289c: 2b01 cmp r3, #1 800289e: d016 beq.n 80028ce { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 80028a0: 687b ldr r3, [r7, #4] 80028a2: 6bdb ldr r3, [r3, #60] @ 0x3c 80028a4: 4a16 ldr r2, [pc, #88] @ (8002900 ) 80028a6: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80028a8: 687b ldr r3, [r7, #4] 80028aa: 2240 movs r2, #64 @ 0x40 80028ac: 2100 movs r1, #0 80028ae: 5499 strb r1, [r3, r2] /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 80028b0: 687b ldr r3, [r7, #4] 80028b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80028b4: 0018 movs r0, r3 80028b6: f7fe fffb bl 80018b0 80028ba: 1e03 subs r3, r0, #0 80028bc: d013 beq.n 80028e6 { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 80028be: 687b ldr r3, [r7, #4] 80028c0: 6bdb ldr r3, [r3, #60] @ 0x3c 80028c2: 6b9a ldr r2, [r3, #56] @ 0x38 80028c4: 687b ldr r3, [r7, #4] 80028c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80028c8: 0018 movs r0, r3 80028ca: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 80028cc: e00b b.n 80028e6 } } else { I2C_TreatErrorCallback(hi2c); 80028ce: 687b ldr r3, [r7, #4] 80028d0: 0018 movs r0, r3 80028d2: f000 f819 bl 8002908 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 80028d6: e006 b.n 80028e6 } } else { I2C_TreatErrorCallback(hi2c); 80028d8: 687b ldr r3, [r7, #4] 80028da: 0018 movs r0, r3 80028dc: f000 f814 bl 8002908 } } 80028e0: e002 b.n 80028e8 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 80028e2: 46c0 nop @ (mov r8, r8) 80028e4: e000 b.n 80028e8 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 80028e6: 46c0 nop @ (mov r8, r8) } 80028e8: 46c0 nop @ (mov r8, r8) 80028ea: 46bd mov sp, r7 80028ec: b004 add sp, #16 80028ee: bd80 pop {r7, pc} 80028f0: ffff0000 .word 0xffff0000 80028f4: 08001f35 .word 0x08001f35 80028f8: 00008003 .word 0x00008003 80028fc: ffffbfff .word 0xffffbfff 8002900: 0800299f .word 0x0800299f 8002904: ffff7fff .word 0xffff7fff 08002908 : * @brief I2C Error callback treatment. * @param hi2c I2C handle. * @retval None */ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) { 8002908: b580 push {r7, lr} 800290a: b082 sub sp, #8 800290c: af00 add r7, sp, #0 800290e: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_ABORT) 8002910: 687b ldr r3, [r7, #4] 8002912: 2241 movs r2, #65 @ 0x41 8002914: 5c9b ldrb r3, [r3, r2] 8002916: b2db uxtb r3, r3 8002918: 2b60 cmp r3, #96 @ 0x60 800291a: d10f bne.n 800293c { hi2c->State = HAL_I2C_STATE_READY; 800291c: 687b ldr r3, [r7, #4] 800291e: 2241 movs r2, #65 @ 0x41 8002920: 2120 movs r1, #32 8002922: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002924: 687b ldr r3, [r7, #4] 8002926: 2200 movs r2, #0 8002928: 631a str r2, [r3, #48] @ 0x30 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800292a: 687b ldr r3, [r7, #4] 800292c: 2240 movs r2, #64 @ 0x40 800292e: 2100 movs r1, #0 8002930: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); 8002932: 687b ldr r3, [r7, #4] 8002934: 0018 movs r0, r3 8002936: f7ff faf4 bl 8001f22 hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 800293a: e00a b.n 8002952 hi2c->PreviousState = I2C_STATE_NONE; 800293c: 687b ldr r3, [r7, #4] 800293e: 2200 movs r2, #0 8002940: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8002942: 687b ldr r3, [r7, #4] 8002944: 2240 movs r2, #64 @ 0x40 8002946: 2100 movs r1, #0 8002948: 5499 strb r1, [r3, r2] HAL_I2C_ErrorCallback(hi2c); 800294a: 687b ldr r3, [r7, #4] 800294c: 0018 movs r0, r3 800294e: f7ff fae0 bl 8001f12 } 8002952: 46c0 nop @ (mov r8, r8) 8002954: 46bd mov sp, r7 8002956: b002 add sp, #8 8002958: bd80 pop {r7, pc} 0800295a : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 800295a: b580 push {r7, lr} 800295c: b082 sub sp, #8 800295e: af00 add r7, sp, #0 8002960: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 8002962: 687b ldr r3, [r7, #4] 8002964: 681b ldr r3, [r3, #0] 8002966: 699b ldr r3, [r3, #24] 8002968: 2202 movs r2, #2 800296a: 4013 ands r3, r2 800296c: 2b02 cmp r3, #2 800296e: d103 bne.n 8002978 { hi2c->Instance->TXDR = 0x00U; 8002970: 687b ldr r3, [r7, #4] 8002972: 681b ldr r3, [r3, #0] 8002974: 2200 movs r2, #0 8002976: 629a str r2, [r3, #40] @ 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 8002978: 687b ldr r3, [r7, #4] 800297a: 681b ldr r3, [r3, #0] 800297c: 699b ldr r3, [r3, #24] 800297e: 2201 movs r2, #1 8002980: 4013 ands r3, r2 8002982: 2b01 cmp r3, #1 8002984: d007 beq.n 8002996 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 8002986: 687b ldr r3, [r7, #4] 8002988: 681b ldr r3, [r3, #0] 800298a: 699a ldr r2, [r3, #24] 800298c: 687b ldr r3, [r7, #4] 800298e: 681b ldr r3, [r3, #0] 8002990: 2101 movs r1, #1 8002992: 430a orrs r2, r1 8002994: 619a str r2, [r3, #24] } } 8002996: 46c0 nop @ (mov r8, r8) 8002998: 46bd mov sp, r7 800299a: b002 add sp, #8 800299c: bd80 pop {r7, pc} 0800299e : * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { 800299e: b580 push {r7, lr} 80029a0: b084 sub sp, #16 80029a2: af00 add r7, sp, #0 80029a4: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 80029a6: 687b ldr r3, [r7, #4] 80029a8: 6a9b ldr r3, [r3, #40] @ 0x28 80029aa: 60fb str r3, [r7, #12] /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) 80029ac: 68fb ldr r3, [r7, #12] 80029ae: 6b9b ldr r3, [r3, #56] @ 0x38 80029b0: 2b00 cmp r3, #0 80029b2: d003 beq.n 80029bc { hi2c->hdmatx->XferAbortCallback = NULL; 80029b4: 68fb ldr r3, [r7, #12] 80029b6: 6b9b ldr r3, [r3, #56] @ 0x38 80029b8: 2200 movs r2, #0 80029ba: 639a str r2, [r3, #56] @ 0x38 } if (hi2c->hdmarx != NULL) 80029bc: 68fb ldr r3, [r7, #12] 80029be: 6bdb ldr r3, [r3, #60] @ 0x3c 80029c0: 2b00 cmp r3, #0 80029c2: d003 beq.n 80029cc { hi2c->hdmarx->XferAbortCallback = NULL; 80029c4: 68fb ldr r3, [r7, #12] 80029c6: 6bdb ldr r3, [r3, #60] @ 0x3c 80029c8: 2200 movs r2, #0 80029ca: 639a str r2, [r3, #56] @ 0x38 } I2C_TreatErrorCallback(hi2c); 80029cc: 68fb ldr r3, [r7, #12] 80029ce: 0018 movs r0, r3 80029d0: f7ff ff9a bl 8002908 } 80029d4: 46c0 nop @ (mov r8, r8) 80029d6: 46bd mov sp, r7 80029d8: b004 add sp, #16 80029da: bd80 pop {r7, pc} 080029dc : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80029dc: b580 push {r7, lr} 80029de: b084 sub sp, #16 80029e0: af00 add r7, sp, #0 80029e2: 6078 str r0, [r7, #4] 80029e4: 000a movs r2, r1 80029e6: 1cbb adds r3, r7, #2 80029e8: 801a strh r2, [r3, #0] uint32_t tmpisr = 0U; 80029ea: 2300 movs r3, #0 80029ec: 60fb str r3, [r7, #12] if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 80029ee: 1cbb adds r3, r7, #2 80029f0: 881b ldrh r3, [r3, #0] 80029f2: 2201 movs r2, #1 80029f4: 4013 ands r3, r2 80029f6: d010 beq.n 8002a1a { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; 80029f8: 68fb ldr r3, [r7, #12] 80029fa: 2242 movs r2, #66 @ 0x42 80029fc: 4313 orrs r3, r2 80029fe: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8002a00: 687b ldr r3, [r7, #4] 8002a02: 2241 movs r2, #65 @ 0x41 8002a04: 5c9b ldrb r3, [r3, r2] 8002a06: b2db uxtb r3, r3 8002a08: 001a movs r2, r3 8002a0a: 2328 movs r3, #40 @ 0x28 8002a0c: 4013 ands r3, r2 8002a0e: 2b28 cmp r3, #40 @ 0x28 8002a10: d003 beq.n 8002a1a { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8002a12: 68fb ldr r3, [r7, #12] 8002a14: 22b0 movs r2, #176 @ 0xb0 8002a16: 4313 orrs r3, r2 8002a18: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8002a1a: 1cbb adds r3, r7, #2 8002a1c: 881b ldrh r3, [r3, #0] 8002a1e: 2202 movs r2, #2 8002a20: 4013 ands r3, r2 8002a22: d010 beq.n 8002a46 { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; 8002a24: 68fb ldr r3, [r7, #12] 8002a26: 2244 movs r2, #68 @ 0x44 8002a28: 4313 orrs r3, r2 8002a2a: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8002a2c: 687b ldr r3, [r7, #4] 8002a2e: 2241 movs r2, #65 @ 0x41 8002a30: 5c9b ldrb r3, [r3, r2] 8002a32: b2db uxtb r3, r3 8002a34: 001a movs r2, r3 8002a36: 2328 movs r3, #40 @ 0x28 8002a38: 4013 ands r3, r2 8002a3a: 2b28 cmp r3, #40 @ 0x28 8002a3c: d003 beq.n 8002a46 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8002a3e: 68fb ldr r3, [r7, #12] 8002a40: 22b0 movs r2, #176 @ 0xb0 8002a42: 4313 orrs r3, r2 8002a44: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8002a46: 1cbb adds r3, r7, #2 8002a48: 2200 movs r2, #0 8002a4a: 5e9b ldrsh r3, [r3, r2] 8002a4c: 2b00 cmp r3, #0 8002a4e: da03 bge.n 8002a58 { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8002a50: 68fb ldr r3, [r7, #12] 8002a52: 22b8 movs r2, #184 @ 0xb8 8002a54: 4313 orrs r3, r2 8002a56: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8002a58: 1cbb adds r3, r7, #2 8002a5a: 881b ldrh r3, [r3, #0] 8002a5c: 2b10 cmp r3, #16 8002a5e: d103 bne.n 8002a68 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8002a60: 68fb ldr r3, [r7, #12] 8002a62: 2290 movs r2, #144 @ 0x90 8002a64: 4313 orrs r3, r2 8002a66: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8002a68: 1cbb adds r3, r7, #2 8002a6a: 881b ldrh r3, [r3, #0] 8002a6c: 2b20 cmp r3, #32 8002a6e: d103 bne.n 8002a78 { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8002a70: 68fb ldr r3, [r7, #12] 8002a72: 2220 movs r2, #32 8002a74: 4313 orrs r3, r2 8002a76: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8002a78: 1cbb adds r3, r7, #2 8002a7a: 881b ldrh r3, [r3, #0] 8002a7c: 2b40 cmp r3, #64 @ 0x40 8002a7e: d103 bne.n 8002a88 { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 8002a80: 68fb ldr r3, [r7, #12] 8002a82: 2240 movs r2, #64 @ 0x40 8002a84: 4313 orrs r3, r2 8002a86: 60fb str r3, [r7, #12] } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); 8002a88: 687b ldr r3, [r7, #4] 8002a8a: 681b ldr r3, [r3, #0] 8002a8c: 681a ldr r2, [r3, #0] 8002a8e: 68fb ldr r3, [r7, #12] 8002a90: 43d9 mvns r1, r3 8002a92: 687b ldr r3, [r7, #4] 8002a94: 681b ldr r3, [r3, #0] 8002a96: 400a ands r2, r1 8002a98: 601a str r2, [r3, #0] } 8002a9a: 46c0 nop @ (mov r8, r8) 8002a9c: 46bd mov sp, r7 8002a9e: b004 add sp, #16 8002aa0: bd80 pop {r7, pc} ... 08002aa4 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8002aa4: b580 push {r7, lr} 8002aa6: b082 sub sp, #8 8002aa8: af00 add r7, sp, #0 8002aaa: 6078 str r0, [r7, #4] 8002aac: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8002aae: 687b ldr r3, [r7, #4] 8002ab0: 2241 movs r2, #65 @ 0x41 8002ab2: 5c9b ldrb r3, [r3, r2] 8002ab4: b2db uxtb r3, r3 8002ab6: 2b20 cmp r3, #32 8002ab8: d138 bne.n 8002b2c { /* Process Locked */ __HAL_LOCK(hi2c); 8002aba: 687b ldr r3, [r7, #4] 8002abc: 2240 movs r2, #64 @ 0x40 8002abe: 5c9b ldrb r3, [r3, r2] 8002ac0: 2b01 cmp r3, #1 8002ac2: d101 bne.n 8002ac8 8002ac4: 2302 movs r3, #2 8002ac6: e032 b.n 8002b2e 8002ac8: 687b ldr r3, [r7, #4] 8002aca: 2240 movs r2, #64 @ 0x40 8002acc: 2101 movs r1, #1 8002ace: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8002ad0: 687b ldr r3, [r7, #4] 8002ad2: 2241 movs r2, #65 @ 0x41 8002ad4: 2124 movs r1, #36 @ 0x24 8002ad6: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002ad8: 687b ldr r3, [r7, #4] 8002ada: 681b ldr r3, [r3, #0] 8002adc: 681a ldr r2, [r3, #0] 8002ade: 687b ldr r3, [r7, #4] 8002ae0: 681b ldr r3, [r3, #0] 8002ae2: 2101 movs r1, #1 8002ae4: 438a bics r2, r1 8002ae6: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 8002ae8: 687b ldr r3, [r7, #4] 8002aea: 681b ldr r3, [r3, #0] 8002aec: 681a ldr r2, [r3, #0] 8002aee: 687b ldr r3, [r7, #4] 8002af0: 681b ldr r3, [r3, #0] 8002af2: 4911 ldr r1, [pc, #68] @ (8002b38 ) 8002af4: 400a ands r2, r1 8002af6: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 8002af8: 687b ldr r3, [r7, #4] 8002afa: 681b ldr r3, [r3, #0] 8002afc: 6819 ldr r1, [r3, #0] 8002afe: 687b ldr r3, [r7, #4] 8002b00: 681b ldr r3, [r3, #0] 8002b02: 683a ldr r2, [r7, #0] 8002b04: 430a orrs r2, r1 8002b06: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8002b08: 687b ldr r3, [r7, #4] 8002b0a: 681b ldr r3, [r3, #0] 8002b0c: 681a ldr r2, [r3, #0] 8002b0e: 687b ldr r3, [r7, #4] 8002b10: 681b ldr r3, [r3, #0] 8002b12: 2101 movs r1, #1 8002b14: 430a orrs r2, r1 8002b16: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8002b18: 687b ldr r3, [r7, #4] 8002b1a: 2241 movs r2, #65 @ 0x41 8002b1c: 2120 movs r1, #32 8002b1e: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002b20: 687b ldr r3, [r7, #4] 8002b22: 2240 movs r2, #64 @ 0x40 8002b24: 2100 movs r1, #0 8002b26: 5499 strb r1, [r3, r2] return HAL_OK; 8002b28: 2300 movs r3, #0 8002b2a: e000 b.n 8002b2e } else { return HAL_BUSY; 8002b2c: 2302 movs r3, #2 } } 8002b2e: 0018 movs r0, r3 8002b30: 46bd mov sp, r7 8002b32: b002 add sp, #8 8002b34: bd80 pop {r7, pc} 8002b36: 46c0 nop @ (mov r8, r8) 8002b38: ffffefff .word 0xffffefff 08002b3c : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8002b3c: b580 push {r7, lr} 8002b3e: b084 sub sp, #16 8002b40: af00 add r7, sp, #0 8002b42: 6078 str r0, [r7, #4] 8002b44: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8002b46: 687b ldr r3, [r7, #4] 8002b48: 2241 movs r2, #65 @ 0x41 8002b4a: 5c9b ldrb r3, [r3, r2] 8002b4c: b2db uxtb r3, r3 8002b4e: 2b20 cmp r3, #32 8002b50: d139 bne.n 8002bc6 { /* Process Locked */ __HAL_LOCK(hi2c); 8002b52: 687b ldr r3, [r7, #4] 8002b54: 2240 movs r2, #64 @ 0x40 8002b56: 5c9b ldrb r3, [r3, r2] 8002b58: 2b01 cmp r3, #1 8002b5a: d101 bne.n 8002b60 8002b5c: 2302 movs r3, #2 8002b5e: e033 b.n 8002bc8 8002b60: 687b ldr r3, [r7, #4] 8002b62: 2240 movs r2, #64 @ 0x40 8002b64: 2101 movs r1, #1 8002b66: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8002b68: 687b ldr r3, [r7, #4] 8002b6a: 2241 movs r2, #65 @ 0x41 8002b6c: 2124 movs r1, #36 @ 0x24 8002b6e: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8002b70: 687b ldr r3, [r7, #4] 8002b72: 681b ldr r3, [r3, #0] 8002b74: 681a ldr r2, [r3, #0] 8002b76: 687b ldr r3, [r7, #4] 8002b78: 681b ldr r3, [r3, #0] 8002b7a: 2101 movs r1, #1 8002b7c: 438a bics r2, r1 8002b7e: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 8002b80: 687b ldr r3, [r7, #4] 8002b82: 681b ldr r3, [r3, #0] 8002b84: 681b ldr r3, [r3, #0] 8002b86: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 8002b88: 68fb ldr r3, [r7, #12] 8002b8a: 4a11 ldr r2, [pc, #68] @ (8002bd0 ) 8002b8c: 4013 ands r3, r2 8002b8e: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 8002b90: 683b ldr r3, [r7, #0] 8002b92: 021b lsls r3, r3, #8 8002b94: 68fa ldr r2, [r7, #12] 8002b96: 4313 orrs r3, r2 8002b98: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 8002b9a: 687b ldr r3, [r7, #4] 8002b9c: 681b ldr r3, [r3, #0] 8002b9e: 68fa ldr r2, [r7, #12] 8002ba0: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8002ba2: 687b ldr r3, [r7, #4] 8002ba4: 681b ldr r3, [r3, #0] 8002ba6: 681a ldr r2, [r3, #0] 8002ba8: 687b ldr r3, [r7, #4] 8002baa: 681b ldr r3, [r3, #0] 8002bac: 2101 movs r1, #1 8002bae: 430a orrs r2, r1 8002bb0: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 2241 movs r2, #65 @ 0x41 8002bb6: 2120 movs r1, #32 8002bb8: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002bba: 687b ldr r3, [r7, #4] 8002bbc: 2240 movs r2, #64 @ 0x40 8002bbe: 2100 movs r1, #0 8002bc0: 5499 strb r1, [r3, r2] return HAL_OK; 8002bc2: 2300 movs r3, #0 8002bc4: e000 b.n 8002bc8 } else { return HAL_BUSY; 8002bc6: 2302 movs r3, #2 } } 8002bc8: 0018 movs r0, r3 8002bca: 46bd mov sp, r7 8002bcc: b004 add sp, #16 8002bce: bd80 pop {r7, pc} 8002bd0: fffff0ff .word 0xfffff0ff 08002bd4 : * cleared before returning the status. If the flag is not cleared within * 6 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8002bd4: b580 push {r7, lr} 8002bd6: b084 sub sp, #16 8002bd8: af00 add r7, sp, #0 8002bda: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* Modify voltage scaling range */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 8002bdc: 4b19 ldr r3, [pc, #100] @ (8002c44 ) 8002bde: 681b ldr r3, [r3, #0] 8002be0: 4a19 ldr r2, [pc, #100] @ (8002c48 ) 8002be2: 4013 ands r3, r2 8002be4: 0019 movs r1, r3 8002be6: 4b17 ldr r3, [pc, #92] @ (8002c44 ) 8002be8: 687a ldr r2, [r7, #4] 8002bea: 430a orrs r2, r1 8002bec: 601a str r2, [r3, #0] /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 8002bee: 687a ldr r2, [r7, #4] 8002bf0: 2380 movs r3, #128 @ 0x80 8002bf2: 009b lsls r3, r3, #2 8002bf4: 429a cmp r2, r3 8002bf6: d11f bne.n 8002c38 { /* Set timeout value */ wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; 8002bf8: 4b14 ldr r3, [pc, #80] @ (8002c4c ) 8002bfa: 681a ldr r2, [r3, #0] 8002bfc: 0013 movs r3, r2 8002bfe: 005b lsls r3, r3, #1 8002c00: 189b adds r3, r3, r2 8002c02: 005b lsls r3, r3, #1 8002c04: 4912 ldr r1, [pc, #72] @ (8002c50 ) 8002c06: 0018 movs r0, r3 8002c08: f7fd fa84 bl 8000114 <__udivsi3> 8002c0c: 0003 movs r3, r0 8002c0e: 3301 adds r3, #1 8002c10: 60fb str r3, [r7, #12] /* Wait until VOSF is reset */ while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8002c12: e008 b.n 8002c26 { if (wait_loop_index != 0U) 8002c14: 68fb ldr r3, [r7, #12] 8002c16: 2b00 cmp r3, #0 8002c18: d003 beq.n 8002c22 { wait_loop_index--; 8002c1a: 68fb ldr r3, [r7, #12] 8002c1c: 3b01 subs r3, #1 8002c1e: 60fb str r3, [r7, #12] 8002c20: e001 b.n 8002c26 } else { return HAL_TIMEOUT; 8002c22: 2303 movs r3, #3 8002c24: e009 b.n 8002c3a while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8002c26: 4b07 ldr r3, [pc, #28] @ (8002c44 ) 8002c28: 695a ldr r2, [r3, #20] 8002c2a: 2380 movs r3, #128 @ 0x80 8002c2c: 00db lsls r3, r3, #3 8002c2e: 401a ands r2, r3 8002c30: 2380 movs r3, #128 @ 0x80 8002c32: 00db lsls r3, r3, #3 8002c34: 429a cmp r2, r3 8002c36: d0ed beq.n 8002c14 } } } return HAL_OK; 8002c38: 2300 movs r3, #0 } 8002c3a: 0018 movs r0, r3 8002c3c: 46bd mov sp, r7 8002c3e: b004 add sp, #16 8002c40: bd80 pop {r7, pc} 8002c42: 46c0 nop @ (mov r8, r8) 8002c44: 40007000 .word 0x40007000 8002c48: fffff9ff .word 0xfffff9ff 8002c4c: 20000000 .word 0x20000000 8002c50: 000f4240 .word 0x000f4240 08002c54 : * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { 8002c54: b580 push {r7, lr} 8002c56: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); 8002c58: 4b03 ldr r3, [pc, #12] @ (8002c68 ) 8002c5a: 689a ldr r2, [r3, #8] 8002c5c: 23e0 movs r3, #224 @ 0xe0 8002c5e: 01db lsls r3, r3, #7 8002c60: 4013 ands r3, r2 } 8002c62: 0018 movs r0, r3 8002c64: 46bd mov sp, r7 8002c66: bd80 pop {r7, pc} 8002c68: 40021000 .word 0x40021000 08002c6c : * supported by this function. User should request a transition to LSE Off * first and then to LSE On or LSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8002c6c: b580 push {r7, lr} 8002c6e: b088 sub sp, #32 8002c70: af00 add r7, sp, #0 8002c72: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8002c74: 687b ldr r3, [r7, #4] 8002c76: 2b00 cmp r3, #0 8002c78: d101 bne.n 8002c7e { return HAL_ERROR; 8002c7a: 2301 movs r3, #1 8002c7c: e2f3 b.n 8003266 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8002c7e: 687b ldr r3, [r7, #4] 8002c80: 681b ldr r3, [r3, #0] 8002c82: 2201 movs r2, #1 8002c84: 4013 ands r3, r2 8002c86: d100 bne.n 8002c8a 8002c88: e07c b.n 8002d84 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002c8a: 4bc3 ldr r3, [pc, #780] @ (8002f98 ) 8002c8c: 689b ldr r3, [r3, #8] 8002c8e: 2238 movs r2, #56 @ 0x38 8002c90: 4013 ands r3, r2 8002c92: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002c94: 4bc0 ldr r3, [pc, #768] @ (8002f98 ) 8002c96: 68db ldr r3, [r3, #12] 8002c98: 2203 movs r2, #3 8002c9a: 4013 ands r3, r2 8002c9c: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) 8002c9e: 69bb ldr r3, [r7, #24] 8002ca0: 2b10 cmp r3, #16 8002ca2: d102 bne.n 8002caa 8002ca4: 697b ldr r3, [r7, #20] 8002ca6: 2b03 cmp r3, #3 8002ca8: d002 beq.n 8002cb0 || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) 8002caa: 69bb ldr r3, [r7, #24] 8002cac: 2b08 cmp r3, #8 8002cae: d10b bne.n 8002cc8 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002cb0: 4bb9 ldr r3, [pc, #740] @ (8002f98 ) 8002cb2: 681a ldr r2, [r3, #0] 8002cb4: 2380 movs r3, #128 @ 0x80 8002cb6: 029b lsls r3, r3, #10 8002cb8: 4013 ands r3, r2 8002cba: d062 beq.n 8002d82 8002cbc: 687b ldr r3, [r7, #4] 8002cbe: 685b ldr r3, [r3, #4] 8002cc0: 2b00 cmp r3, #0 8002cc2: d15e bne.n 8002d82 { return HAL_ERROR; 8002cc4: 2301 movs r3, #1 8002cc6: e2ce b.n 8003266 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8002cc8: 687b ldr r3, [r7, #4] 8002cca: 685a ldr r2, [r3, #4] 8002ccc: 2380 movs r3, #128 @ 0x80 8002cce: 025b lsls r3, r3, #9 8002cd0: 429a cmp r2, r3 8002cd2: d107 bne.n 8002ce4 8002cd4: 4bb0 ldr r3, [pc, #704] @ (8002f98 ) 8002cd6: 681a ldr r2, [r3, #0] 8002cd8: 4baf ldr r3, [pc, #700] @ (8002f98 ) 8002cda: 2180 movs r1, #128 @ 0x80 8002cdc: 0249 lsls r1, r1, #9 8002cde: 430a orrs r2, r1 8002ce0: 601a str r2, [r3, #0] 8002ce2: e020 b.n 8002d26 8002ce4: 687b ldr r3, [r7, #4] 8002ce6: 685a ldr r2, [r3, #4] 8002ce8: 23a0 movs r3, #160 @ 0xa0 8002cea: 02db lsls r3, r3, #11 8002cec: 429a cmp r2, r3 8002cee: d10e bne.n 8002d0e 8002cf0: 4ba9 ldr r3, [pc, #676] @ (8002f98 ) 8002cf2: 681a ldr r2, [r3, #0] 8002cf4: 4ba8 ldr r3, [pc, #672] @ (8002f98 ) 8002cf6: 2180 movs r1, #128 @ 0x80 8002cf8: 02c9 lsls r1, r1, #11 8002cfa: 430a orrs r2, r1 8002cfc: 601a str r2, [r3, #0] 8002cfe: 4ba6 ldr r3, [pc, #664] @ (8002f98 ) 8002d00: 681a ldr r2, [r3, #0] 8002d02: 4ba5 ldr r3, [pc, #660] @ (8002f98 ) 8002d04: 2180 movs r1, #128 @ 0x80 8002d06: 0249 lsls r1, r1, #9 8002d08: 430a orrs r2, r1 8002d0a: 601a str r2, [r3, #0] 8002d0c: e00b b.n 8002d26 8002d0e: 4ba2 ldr r3, [pc, #648] @ (8002f98 ) 8002d10: 681a ldr r2, [r3, #0] 8002d12: 4ba1 ldr r3, [pc, #644] @ (8002f98 ) 8002d14: 49a1 ldr r1, [pc, #644] @ (8002f9c ) 8002d16: 400a ands r2, r1 8002d18: 601a str r2, [r3, #0] 8002d1a: 4b9f ldr r3, [pc, #636] @ (8002f98 ) 8002d1c: 681a ldr r2, [r3, #0] 8002d1e: 4b9e ldr r3, [pc, #632] @ (8002f98 ) 8002d20: 499f ldr r1, [pc, #636] @ (8002fa0 ) 8002d22: 400a ands r2, r1 8002d24: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8002d26: 687b ldr r3, [r7, #4] 8002d28: 685b ldr r3, [r3, #4] 8002d2a: 2b00 cmp r3, #0 8002d2c: d014 beq.n 8002d58 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002d2e: f7fe fc9d bl 800166c 8002d32: 0003 movs r3, r0 8002d34: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002d36: e008 b.n 8002d4a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002d38: f7fe fc98 bl 800166c 8002d3c: 0002 movs r2, r0 8002d3e: 693b ldr r3, [r7, #16] 8002d40: 1ad3 subs r3, r2, r3 8002d42: 2b64 cmp r3, #100 @ 0x64 8002d44: d901 bls.n 8002d4a { return HAL_TIMEOUT; 8002d46: 2303 movs r3, #3 8002d48: e28d b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8002d4a: 4b93 ldr r3, [pc, #588] @ (8002f98 ) 8002d4c: 681a ldr r2, [r3, #0] 8002d4e: 2380 movs r3, #128 @ 0x80 8002d50: 029b lsls r3, r3, #10 8002d52: 4013 ands r3, r2 8002d54: d0f0 beq.n 8002d38 8002d56: e015 b.n 8002d84 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002d58: f7fe fc88 bl 800166c 8002d5c: 0003 movs r3, r0 8002d5e: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8002d60: e008 b.n 8002d74 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8002d62: f7fe fc83 bl 800166c 8002d66: 0002 movs r2, r0 8002d68: 693b ldr r3, [r7, #16] 8002d6a: 1ad3 subs r3, r2, r3 8002d6c: 2b64 cmp r3, #100 @ 0x64 8002d6e: d901 bls.n 8002d74 { return HAL_TIMEOUT; 8002d70: 2303 movs r3, #3 8002d72: e278 b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8002d74: 4b88 ldr r3, [pc, #544] @ (8002f98 ) 8002d76: 681a ldr r2, [r3, #0] 8002d78: 2380 movs r3, #128 @ 0x80 8002d7a: 029b lsls r3, r3, #10 8002d7c: 4013 ands r3, r2 8002d7e: d1f0 bne.n 8002d62 8002d80: e000 b.n 8002d84 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8002d82: 46c0 nop @ (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8002d84: 687b ldr r3, [r7, #4] 8002d86: 681b ldr r3, [r3, #0] 8002d88: 2202 movs r2, #2 8002d8a: 4013 ands r3, r2 8002d8c: d100 bne.n 8002d90 8002d8e: e099 b.n 8002ec4 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8002d90: 4b81 ldr r3, [pc, #516] @ (8002f98 ) 8002d92: 689b ldr r3, [r3, #8] 8002d94: 2238 movs r2, #56 @ 0x38 8002d96: 4013 ands r3, r2 8002d98: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 8002d9a: 4b7f ldr r3, [pc, #508] @ (8002f98 ) 8002d9c: 68db ldr r3, [r3, #12] 8002d9e: 2203 movs r2, #3 8002da0: 4013 ands r3, r2 8002da2: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) 8002da4: 69bb ldr r3, [r7, #24] 8002da6: 2b10 cmp r3, #16 8002da8: d102 bne.n 8002db0 8002daa: 697b ldr r3, [r7, #20] 8002dac: 2b02 cmp r3, #2 8002dae: d002 beq.n 8002db6 || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) 8002db0: 69bb ldr r3, [r7, #24] 8002db2: 2b00 cmp r3, #0 8002db4: d135 bne.n 8002e22 { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002db6: 4b78 ldr r3, [pc, #480] @ (8002f98 ) 8002db8: 681a ldr r2, [r3, #0] 8002dba: 2380 movs r3, #128 @ 0x80 8002dbc: 00db lsls r3, r3, #3 8002dbe: 4013 ands r3, r2 8002dc0: d005 beq.n 8002dce 8002dc2: 687b ldr r3, [r7, #4] 8002dc4: 68db ldr r3, [r3, #12] 8002dc6: 2b00 cmp r3, #0 8002dc8: d101 bne.n 8002dce { return HAL_ERROR; 8002dca: 2301 movs r3, #1 8002dcc: e24b b.n 8003266 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002dce: 4b72 ldr r3, [pc, #456] @ (8002f98 ) 8002dd0: 685b ldr r3, [r3, #4] 8002dd2: 4a74 ldr r2, [pc, #464] @ (8002fa4 ) 8002dd4: 4013 ands r3, r2 8002dd6: 0019 movs r1, r3 8002dd8: 687b ldr r3, [r7, #4] 8002dda: 695b ldr r3, [r3, #20] 8002ddc: 021a lsls r2, r3, #8 8002dde: 4b6e ldr r3, [pc, #440] @ (8002f98 ) 8002de0: 430a orrs r2, r1 8002de2: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 8002de4: 69bb ldr r3, [r7, #24] 8002de6: 2b00 cmp r3, #0 8002de8: d112 bne.n 8002e10 { /* Adjust the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8002dea: 4b6b ldr r3, [pc, #428] @ (8002f98 ) 8002dec: 681b ldr r3, [r3, #0] 8002dee: 4a6e ldr r2, [pc, #440] @ (8002fa8 ) 8002df0: 4013 ands r3, r2 8002df2: 0019 movs r1, r3 8002df4: 687b ldr r3, [r7, #4] 8002df6: 691a ldr r2, [r3, #16] 8002df8: 4b67 ldr r3, [pc, #412] @ (8002f98 ) 8002dfa: 430a orrs r2, r1 8002dfc: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 8002dfe: 4b66 ldr r3, [pc, #408] @ (8002f98 ) 8002e00: 681b ldr r3, [r3, #0] 8002e02: 0adb lsrs r3, r3, #11 8002e04: 2207 movs r2, #7 8002e06: 4013 ands r3, r2 8002e08: 4a68 ldr r2, [pc, #416] @ (8002fac ) 8002e0a: 40da lsrs r2, r3 8002e0c: 4b68 ldr r3, [pc, #416] @ (8002fb0 ) 8002e0e: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8002e10: 4b68 ldr r3, [pc, #416] @ (8002fb4 ) 8002e12: 681b ldr r3, [r3, #0] 8002e14: 0018 movs r0, r3 8002e16: f7fe fbcd bl 80015b4 8002e1a: 1e03 subs r3, r0, #0 8002e1c: d051 beq.n 8002ec2 { return HAL_ERROR; 8002e1e: 2301 movs r3, #1 8002e20: e221 b.n 8003266 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8002e22: 687b ldr r3, [r7, #4] 8002e24: 68db ldr r3, [r3, #12] 8002e26: 2b00 cmp r3, #0 8002e28: d030 beq.n 8002e8c { /* Configure the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8002e2a: 4b5b ldr r3, [pc, #364] @ (8002f98 ) 8002e2c: 681b ldr r3, [r3, #0] 8002e2e: 4a5e ldr r2, [pc, #376] @ (8002fa8 ) 8002e30: 4013 ands r3, r2 8002e32: 0019 movs r1, r3 8002e34: 687b ldr r3, [r7, #4] 8002e36: 691a ldr r2, [r3, #16] 8002e38: 4b57 ldr r3, [pc, #348] @ (8002f98 ) 8002e3a: 430a orrs r2, r1 8002e3c: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_ENABLE(); 8002e3e: 4b56 ldr r3, [pc, #344] @ (8002f98 ) 8002e40: 681a ldr r2, [r3, #0] 8002e42: 4b55 ldr r3, [pc, #340] @ (8002f98 ) 8002e44: 2180 movs r1, #128 @ 0x80 8002e46: 0049 lsls r1, r1, #1 8002e48: 430a orrs r2, r1 8002e4a: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002e4c: f7fe fc0e bl 800166c 8002e50: 0003 movs r3, r0 8002e52: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002e54: e008 b.n 8002e68 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002e56: f7fe fc09 bl 800166c 8002e5a: 0002 movs r2, r0 8002e5c: 693b ldr r3, [r7, #16] 8002e5e: 1ad3 subs r3, r2, r3 8002e60: 2b02 cmp r3, #2 8002e62: d901 bls.n 8002e68 { return HAL_TIMEOUT; 8002e64: 2303 movs r3, #3 8002e66: e1fe b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8002e68: 4b4b ldr r3, [pc, #300] @ (8002f98 ) 8002e6a: 681a ldr r2, [r3, #0] 8002e6c: 2380 movs r3, #128 @ 0x80 8002e6e: 00db lsls r3, r3, #3 8002e70: 4013 ands r3, r2 8002e72: d0f0 beq.n 8002e56 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8002e74: 4b48 ldr r3, [pc, #288] @ (8002f98 ) 8002e76: 685b ldr r3, [r3, #4] 8002e78: 4a4a ldr r2, [pc, #296] @ (8002fa4 ) 8002e7a: 4013 ands r3, r2 8002e7c: 0019 movs r1, r3 8002e7e: 687b ldr r3, [r7, #4] 8002e80: 695b ldr r3, [r3, #20] 8002e82: 021a lsls r2, r3, #8 8002e84: 4b44 ldr r3, [pc, #272] @ (8002f98 ) 8002e86: 430a orrs r2, r1 8002e88: 605a str r2, [r3, #4] 8002e8a: e01b b.n 8002ec4 } else { /* Disable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_DISABLE(); 8002e8c: 4b42 ldr r3, [pc, #264] @ (8002f98 ) 8002e8e: 681a ldr r2, [r3, #0] 8002e90: 4b41 ldr r3, [pc, #260] @ (8002f98 ) 8002e92: 4949 ldr r1, [pc, #292] @ (8002fb8 ) 8002e94: 400a ands r2, r1 8002e96: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002e98: f7fe fbe8 bl 800166c 8002e9c: 0003 movs r3, r0 8002e9e: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8002ea0: e008 b.n 8002eb4 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8002ea2: f7fe fbe3 bl 800166c 8002ea6: 0002 movs r2, r0 8002ea8: 693b ldr r3, [r7, #16] 8002eaa: 1ad3 subs r3, r2, r3 8002eac: 2b02 cmp r3, #2 8002eae: d901 bls.n 8002eb4 { return HAL_TIMEOUT; 8002eb0: 2303 movs r3, #3 8002eb2: e1d8 b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8002eb4: 4b38 ldr r3, [pc, #224] @ (8002f98 ) 8002eb6: 681a ldr r2, [r3, #0] 8002eb8: 2380 movs r3, #128 @ 0x80 8002eba: 00db lsls r3, r3, #3 8002ebc: 4013 ands r3, r2 8002ebe: d1f0 bne.n 8002ea2 8002ec0: e000 b.n 8002ec4 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8002ec2: 46c0 nop @ (mov r8, r8) } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8002ec4: 687b ldr r3, [r7, #4] 8002ec6: 681b ldr r3, [r3, #0] 8002ec8: 2208 movs r2, #8 8002eca: 4013 ands r3, r2 8002ecc: d047 beq.n 8002f5e { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8002ece: 4b32 ldr r3, [pc, #200] @ (8002f98 ) 8002ed0: 689b ldr r3, [r3, #8] 8002ed2: 2238 movs r2, #56 @ 0x38 8002ed4: 4013 ands r3, r2 8002ed6: 2b18 cmp r3, #24 8002ed8: d10a bne.n 8002ef0 { /* When LSI is used as system clock it will not be disabled */ if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) 8002eda: 4b2f ldr r3, [pc, #188] @ (8002f98 ) 8002edc: 6e1b ldr r3, [r3, #96] @ 0x60 8002ede: 2202 movs r2, #2 8002ee0: 4013 ands r3, r2 8002ee2: d03c beq.n 8002f5e 8002ee4: 687b ldr r3, [r7, #4] 8002ee6: 699b ldr r3, [r3, #24] 8002ee8: 2b00 cmp r3, #0 8002eea: d138 bne.n 8002f5e { return HAL_ERROR; 8002eec: 2301 movs r3, #1 8002eee: e1ba b.n 8003266 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8002ef0: 687b ldr r3, [r7, #4] 8002ef2: 699b ldr r3, [r3, #24] 8002ef4: 2b00 cmp r3, #0 8002ef6: d019 beq.n 8002f2c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8002ef8: 4b27 ldr r3, [pc, #156] @ (8002f98 ) 8002efa: 6e1a ldr r2, [r3, #96] @ 0x60 8002efc: 4b26 ldr r3, [pc, #152] @ (8002f98 ) 8002efe: 2101 movs r1, #1 8002f00: 430a orrs r2, r1 8002f02: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002f04: f7fe fbb2 bl 800166c 8002f08: 0003 movs r3, r0 8002f0a: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002f0c: e008 b.n 8002f20 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002f0e: f7fe fbad bl 800166c 8002f12: 0002 movs r2, r0 8002f14: 693b ldr r3, [r7, #16] 8002f16: 1ad3 subs r3, r2, r3 8002f18: 2b02 cmp r3, #2 8002f1a: d901 bls.n 8002f20 { return HAL_TIMEOUT; 8002f1c: 2303 movs r3, #3 8002f1e: e1a2 b.n 8003266 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8002f20: 4b1d ldr r3, [pc, #116] @ (8002f98 ) 8002f22: 6e1b ldr r3, [r3, #96] @ 0x60 8002f24: 2202 movs r2, #2 8002f26: 4013 ands r3, r2 8002f28: d0f1 beq.n 8002f0e 8002f2a: e018 b.n 8002f5e } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8002f2c: 4b1a ldr r3, [pc, #104] @ (8002f98 ) 8002f2e: 6e1a ldr r2, [r3, #96] @ 0x60 8002f30: 4b19 ldr r3, [pc, #100] @ (8002f98 ) 8002f32: 2101 movs r1, #1 8002f34: 438a bics r2, r1 8002f36: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8002f38: f7fe fb98 bl 800166c 8002f3c: 0003 movs r3, r0 8002f3e: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8002f40: e008 b.n 8002f54 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8002f42: f7fe fb93 bl 800166c 8002f46: 0002 movs r2, r0 8002f48: 693b ldr r3, [r7, #16] 8002f4a: 1ad3 subs r3, r2, r3 8002f4c: 2b02 cmp r3, #2 8002f4e: d901 bls.n 8002f54 { return HAL_TIMEOUT; 8002f50: 2303 movs r3, #3 8002f52: e188 b.n 8003266 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8002f54: 4b10 ldr r3, [pc, #64] @ (8002f98 ) 8002f56: 6e1b ldr r3, [r3, #96] @ 0x60 8002f58: 2202 movs r2, #2 8002f5a: 4013 ands r3, r2 8002f5c: d1f1 bne.n 8002f42 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8002f5e: 687b ldr r3, [r7, #4] 8002f60: 681b ldr r3, [r3, #0] 8002f62: 2204 movs r2, #4 8002f64: 4013 ands r3, r2 8002f66: d100 bne.n 8002f6a 8002f68: e0c6 b.n 80030f8 { FlagStatus pwrclkchanged = RESET; 8002f6a: 231f movs r3, #31 8002f6c: 18fb adds r3, r7, r3 8002f6e: 2200 movs r2, #0 8002f70: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8002f72: 4b09 ldr r3, [pc, #36] @ (8002f98 ) 8002f74: 689b ldr r3, [r3, #8] 8002f76: 2238 movs r2, #56 @ 0x38 8002f78: 4013 ands r3, r2 8002f7a: 2b20 cmp r3, #32 8002f7c: d11e bne.n 8002fbc { if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) 8002f7e: 4b06 ldr r3, [pc, #24] @ (8002f98 ) 8002f80: 6ddb ldr r3, [r3, #92] @ 0x5c 8002f82: 2202 movs r2, #2 8002f84: 4013 ands r3, r2 8002f86: d100 bne.n 8002f8a 8002f88: e0b6 b.n 80030f8 8002f8a: 687b ldr r3, [r7, #4] 8002f8c: 689b ldr r3, [r3, #8] 8002f8e: 2b00 cmp r3, #0 8002f90: d000 beq.n 8002f94 8002f92: e0b1 b.n 80030f8 { return HAL_ERROR; 8002f94: 2301 movs r3, #1 8002f96: e166 b.n 8003266 8002f98: 40021000 .word 0x40021000 8002f9c: fffeffff .word 0xfffeffff 8002fa0: fffbffff .word 0xfffbffff 8002fa4: ffff80ff .word 0xffff80ff 8002fa8: ffffc7ff .word 0xffffc7ff 8002fac: 00f42400 .word 0x00f42400 8002fb0: 20000000 .word 0x20000000 8002fb4: 20000004 .word 0x20000004 8002fb8: fffffeff .word 0xfffffeff } else { /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 8002fbc: 4bac ldr r3, [pc, #688] @ (8003270 ) 8002fbe: 6bda ldr r2, [r3, #60] @ 0x3c 8002fc0: 2380 movs r3, #128 @ 0x80 8002fc2: 055b lsls r3, r3, #21 8002fc4: 4013 ands r3, r2 8002fc6: d101 bne.n 8002fcc 8002fc8: 2301 movs r3, #1 8002fca: e000 b.n 8002fce 8002fcc: 2300 movs r3, #0 8002fce: 2b00 cmp r3, #0 8002fd0: d011 beq.n 8002ff6 { __HAL_RCC_PWR_CLK_ENABLE(); 8002fd2: 4ba7 ldr r3, [pc, #668] @ (8003270 ) 8002fd4: 6bda ldr r2, [r3, #60] @ 0x3c 8002fd6: 4ba6 ldr r3, [pc, #664] @ (8003270 ) 8002fd8: 2180 movs r1, #128 @ 0x80 8002fda: 0549 lsls r1, r1, #21 8002fdc: 430a orrs r2, r1 8002fde: 63da str r2, [r3, #60] @ 0x3c 8002fe0: 4ba3 ldr r3, [pc, #652] @ (8003270 ) 8002fe2: 6bda ldr r2, [r3, #60] @ 0x3c 8002fe4: 2380 movs r3, #128 @ 0x80 8002fe6: 055b lsls r3, r3, #21 8002fe8: 4013 ands r3, r2 8002fea: 60fb str r3, [r7, #12] 8002fec: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8002fee: 231f movs r3, #31 8002ff0: 18fb adds r3, r7, r3 8002ff2: 2201 movs r2, #1 8002ff4: 701a strb r2, [r3, #0] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8002ff6: 4b9f ldr r3, [pc, #636] @ (8003274 ) 8002ff8: 681a ldr r2, [r3, #0] 8002ffa: 2380 movs r3, #128 @ 0x80 8002ffc: 005b lsls r3, r3, #1 8002ffe: 4013 ands r3, r2 8003000: d11a bne.n 8003038 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003002: 4b9c ldr r3, [pc, #624] @ (8003274 ) 8003004: 681a ldr r2, [r3, #0] 8003006: 4b9b ldr r3, [pc, #620] @ (8003274 ) 8003008: 2180 movs r1, #128 @ 0x80 800300a: 0049 lsls r1, r1, #1 800300c: 430a orrs r2, r1 800300e: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003010: f7fe fb2c bl 800166c 8003014: 0003 movs r3, r0 8003016: 613b str r3, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003018: e008 b.n 800302c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800301a: f7fe fb27 bl 800166c 800301e: 0002 movs r2, r0 8003020: 693b ldr r3, [r7, #16] 8003022: 1ad3 subs r3, r2, r3 8003024: 2b02 cmp r3, #2 8003026: d901 bls.n 800302c { return HAL_TIMEOUT; 8003028: 2303 movs r3, #3 800302a: e11c b.n 8003266 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 800302c: 4b91 ldr r3, [pc, #580] @ (8003274 ) 800302e: 681a ldr r2, [r3, #0] 8003030: 2380 movs r3, #128 @ 0x80 8003032: 005b lsls r3, r3, #1 8003034: 4013 ands r3, r2 8003036: d0f0 beq.n 800301a } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003038: 687b ldr r3, [r7, #4] 800303a: 689b ldr r3, [r3, #8] 800303c: 2b01 cmp r3, #1 800303e: d106 bne.n 800304e 8003040: 4b8b ldr r3, [pc, #556] @ (8003270 ) 8003042: 6dda ldr r2, [r3, #92] @ 0x5c 8003044: 4b8a ldr r3, [pc, #552] @ (8003270 ) 8003046: 2101 movs r1, #1 8003048: 430a orrs r2, r1 800304a: 65da str r2, [r3, #92] @ 0x5c 800304c: e01c b.n 8003088 800304e: 687b ldr r3, [r7, #4] 8003050: 689b ldr r3, [r3, #8] 8003052: 2b05 cmp r3, #5 8003054: d10c bne.n 8003070 8003056: 4b86 ldr r3, [pc, #536] @ (8003270 ) 8003058: 6dda ldr r2, [r3, #92] @ 0x5c 800305a: 4b85 ldr r3, [pc, #532] @ (8003270 ) 800305c: 2104 movs r1, #4 800305e: 430a orrs r2, r1 8003060: 65da str r2, [r3, #92] @ 0x5c 8003062: 4b83 ldr r3, [pc, #524] @ (8003270 ) 8003064: 6dda ldr r2, [r3, #92] @ 0x5c 8003066: 4b82 ldr r3, [pc, #520] @ (8003270 ) 8003068: 2101 movs r1, #1 800306a: 430a orrs r2, r1 800306c: 65da str r2, [r3, #92] @ 0x5c 800306e: e00b b.n 8003088 8003070: 4b7f ldr r3, [pc, #508] @ (8003270 ) 8003072: 6dda ldr r2, [r3, #92] @ 0x5c 8003074: 4b7e ldr r3, [pc, #504] @ (8003270 ) 8003076: 2101 movs r1, #1 8003078: 438a bics r2, r1 800307a: 65da str r2, [r3, #92] @ 0x5c 800307c: 4b7c ldr r3, [pc, #496] @ (8003270 ) 800307e: 6dda ldr r2, [r3, #92] @ 0x5c 8003080: 4b7b ldr r3, [pc, #492] @ (8003270 ) 8003082: 2104 movs r1, #4 8003084: 438a bics r2, r1 8003086: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8003088: 687b ldr r3, [r7, #4] 800308a: 689b ldr r3, [r3, #8] 800308c: 2b00 cmp r3, #0 800308e: d014 beq.n 80030ba { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003090: f7fe faec bl 800166c 8003094: 0003 movs r3, r0 8003096: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003098: e009 b.n 80030ae { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800309a: f7fe fae7 bl 800166c 800309e: 0002 movs r2, r0 80030a0: 693b ldr r3, [r7, #16] 80030a2: 1ad3 subs r3, r2, r3 80030a4: 4a74 ldr r2, [pc, #464] @ (8003278 ) 80030a6: 4293 cmp r3, r2 80030a8: d901 bls.n 80030ae { return HAL_TIMEOUT; 80030aa: 2303 movs r3, #3 80030ac: e0db b.n 8003266 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80030ae: 4b70 ldr r3, [pc, #448] @ (8003270 ) 80030b0: 6ddb ldr r3, [r3, #92] @ 0x5c 80030b2: 2202 movs r2, #2 80030b4: 4013 ands r3, r2 80030b6: d0f0 beq.n 800309a 80030b8: e013 b.n 80030e2 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80030ba: f7fe fad7 bl 800166c 80030be: 0003 movs r3, r0 80030c0: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80030c2: e009 b.n 80030d8 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80030c4: f7fe fad2 bl 800166c 80030c8: 0002 movs r2, r0 80030ca: 693b ldr r3, [r7, #16] 80030cc: 1ad3 subs r3, r2, r3 80030ce: 4a6a ldr r2, [pc, #424] @ (8003278 ) 80030d0: 4293 cmp r3, r2 80030d2: d901 bls.n 80030d8 { return HAL_TIMEOUT; 80030d4: 2303 movs r3, #3 80030d6: e0c6 b.n 8003266 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80030d8: 4b65 ldr r3, [pc, #404] @ (8003270 ) 80030da: 6ddb ldr r3, [r3, #92] @ 0x5c 80030dc: 2202 movs r2, #2 80030de: 4013 ands r3, r2 80030e0: d1f0 bne.n 80030c4 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80030e2: 231f movs r3, #31 80030e4: 18fb adds r3, r7, r3 80030e6: 781b ldrb r3, [r3, #0] 80030e8: 2b01 cmp r3, #1 80030ea: d105 bne.n 80030f8 { __HAL_RCC_PWR_CLK_DISABLE(); 80030ec: 4b60 ldr r3, [pc, #384] @ (8003270 ) 80030ee: 6bda ldr r2, [r3, #60] @ 0x3c 80030f0: 4b5f ldr r3, [pc, #380] @ (8003270 ) 80030f2: 4962 ldr r1, [pc, #392] @ (800327c ) 80030f4: 400a ands r2, r1 80030f6: 63da str r2, [r3, #60] @ 0x3c #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 80030f8: 687b ldr r3, [r7, #4] 80030fa: 69db ldr r3, [r3, #28] 80030fc: 2b00 cmp r3, #0 80030fe: d100 bne.n 8003102 8003100: e0b0 b.n 8003264 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003102: 4b5b ldr r3, [pc, #364] @ (8003270 ) 8003104: 689b ldr r3, [r3, #8] 8003106: 2238 movs r2, #56 @ 0x38 8003108: 4013 ands r3, r2 800310a: 2b10 cmp r3, #16 800310c: d100 bne.n 8003110 800310e: e078 b.n 8003202 { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8003110: 687b ldr r3, [r7, #4] 8003112: 69db ldr r3, [r3, #28] 8003114: 2b02 cmp r3, #2 8003116: d153 bne.n 80031c0 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); #endif /* RCC_PLLQ_SUPPORT */ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003118: 4b55 ldr r3, [pc, #340] @ (8003270 ) 800311a: 681a ldr r2, [r3, #0] 800311c: 4b54 ldr r3, [pc, #336] @ (8003270 ) 800311e: 4958 ldr r1, [pc, #352] @ (8003280 ) 8003120: 400a ands r2, r1 8003122: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003124: f7fe faa2 bl 800166c 8003128: 0003 movs r3, r0 800312a: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800312c: e008 b.n 8003140 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800312e: f7fe fa9d bl 800166c 8003132: 0002 movs r2, r0 8003134: 693b ldr r3, [r7, #16] 8003136: 1ad3 subs r3, r2, r3 8003138: 2b02 cmp r3, #2 800313a: d901 bls.n 8003140 { return HAL_TIMEOUT; 800313c: 2303 movs r3, #3 800313e: e092 b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003140: 4b4b ldr r3, [pc, #300] @ (8003270 ) 8003142: 681a ldr r2, [r3, #0] 8003144: 2380 movs r3, #128 @ 0x80 8003146: 049b lsls r3, r3, #18 8003148: 4013 ands r3, r2 800314a: d1f0 bne.n 800312e RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); #else /* !RCC_PLLQ_SUPPORT */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800314c: 4b48 ldr r3, [pc, #288] @ (8003270 ) 800314e: 68db ldr r3, [r3, #12] 8003150: 4a4c ldr r2, [pc, #304] @ (8003284 ) 8003152: 4013 ands r3, r2 8003154: 0019 movs r1, r3 8003156: 687b ldr r3, [r7, #4] 8003158: 6a1a ldr r2, [r3, #32] 800315a: 687b ldr r3, [r7, #4] 800315c: 6a5b ldr r3, [r3, #36] @ 0x24 800315e: 431a orrs r2, r3 8003160: 687b ldr r3, [r7, #4] 8003162: 6a9b ldr r3, [r3, #40] @ 0x28 8003164: 021b lsls r3, r3, #8 8003166: 431a orrs r2, r3 8003168: 687b ldr r3, [r7, #4] 800316a: 6adb ldr r3, [r3, #44] @ 0x2c 800316c: 431a orrs r2, r3 800316e: 687b ldr r3, [r7, #4] 8003170: 6b1b ldr r3, [r3, #48] @ 0x30 8003172: 431a orrs r2, r3 8003174: 4b3e ldr r3, [pc, #248] @ (8003270 ) 8003176: 430a orrs r2, r1 8003178: 60da str r2, [r3, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLR); #endif /* RCC_PLLQ_SUPPORT */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800317a: 4b3d ldr r3, [pc, #244] @ (8003270 ) 800317c: 681a ldr r2, [r3, #0] 800317e: 4b3c ldr r3, [pc, #240] @ (8003270 ) 8003180: 2180 movs r1, #128 @ 0x80 8003182: 0449 lsls r1, r1, #17 8003184: 430a orrs r2, r1 8003186: 601a str r2, [r3, #0] /* Enable PLLR Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); 8003188: 4b39 ldr r3, [pc, #228] @ (8003270 ) 800318a: 68da ldr r2, [r3, #12] 800318c: 4b38 ldr r3, [pc, #224] @ (8003270 ) 800318e: 2180 movs r1, #128 @ 0x80 8003190: 0549 lsls r1, r1, #21 8003192: 430a orrs r2, r1 8003194: 60da str r2, [r3, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003196: f7fe fa69 bl 800166c 800319a: 0003 movs r3, r0 800319c: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800319e: e008 b.n 80031b2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80031a0: f7fe fa64 bl 800166c 80031a4: 0002 movs r2, r0 80031a6: 693b ldr r3, [r7, #16] 80031a8: 1ad3 subs r3, r2, r3 80031aa: 2b02 cmp r3, #2 80031ac: d901 bls.n 80031b2 { return HAL_TIMEOUT; 80031ae: 2303 movs r3, #3 80031b0: e059 b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80031b2: 4b2f ldr r3, [pc, #188] @ (8003270 ) 80031b4: 681a ldr r2, [r3, #0] 80031b6: 2380 movs r3, #128 @ 0x80 80031b8: 049b lsls r3, r3, #18 80031ba: 4013 ands r3, r2 80031bc: d0f0 beq.n 80031a0 80031be: e051 b.n 8003264 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80031c0: 4b2b ldr r3, [pc, #172] @ (8003270 ) 80031c2: 681a ldr r2, [r3, #0] 80031c4: 4b2a ldr r3, [pc, #168] @ (8003270 ) 80031c6: 492e ldr r1, [pc, #184] @ (8003280 ) 80031c8: 400a ands r2, r1 80031ca: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80031cc: f7fe fa4e bl 800166c 80031d0: 0003 movs r3, r0 80031d2: 613b str r3, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80031d4: e008 b.n 80031e8 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80031d6: f7fe fa49 bl 800166c 80031da: 0002 movs r2, r0 80031dc: 693b ldr r3, [r7, #16] 80031de: 1ad3 subs r3, r2, r3 80031e0: 2b02 cmp r3, #2 80031e2: d901 bls.n 80031e8 { return HAL_TIMEOUT; 80031e4: 2303 movs r3, #3 80031e6: e03e b.n 8003266 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80031e8: 4b21 ldr r3, [pc, #132] @ (8003270 ) 80031ea: 681a ldr r2, [r3, #0] 80031ec: 2380 movs r3, #128 @ 0x80 80031ee: 049b lsls r3, r3, #18 80031f0: 4013 ands r3, r2 80031f2: d1f0 bne.n 80031d6 } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLQ_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); #else RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); 80031f4: 4b1e ldr r3, [pc, #120] @ (8003270 ) 80031f6: 68da ldr r2, [r3, #12] 80031f8: 4b1d ldr r3, [pc, #116] @ (8003270 ) 80031fa: 4923 ldr r1, [pc, #140] @ (8003288 ) 80031fc: 400a ands r2, r1 80031fe: 60da str r2, [r3, #12] 8003200: e030 b.n 8003264 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003202: 687b ldr r3, [r7, #4] 8003204: 69db ldr r3, [r3, #28] 8003206: 2b01 cmp r3, #1 8003208: d101 bne.n 800320e { return HAL_ERROR; 800320a: 2301 movs r3, #1 800320c: e02b b.n 8003266 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 800320e: 4b18 ldr r3, [pc, #96] @ (8003270 ) 8003210: 68db ldr r3, [r3, #12] 8003212: 617b str r3, [r7, #20] if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003214: 697b ldr r3, [r7, #20] 8003216: 2203 movs r2, #3 8003218: 401a ands r2, r3 800321a: 687b ldr r3, [r7, #4] 800321c: 6a1b ldr r3, [r3, #32] 800321e: 429a cmp r2, r3 8003220: d11e bne.n 8003260 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003222: 697b ldr r3, [r7, #20] 8003224: 2270 movs r2, #112 @ 0x70 8003226: 401a ands r2, r3 8003228: 687b ldr r3, [r7, #4] 800322a: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800322c: 429a cmp r2, r3 800322e: d117 bne.n 8003260 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003230: 697a ldr r2, [r7, #20] 8003232: 23fe movs r3, #254 @ 0xfe 8003234: 01db lsls r3, r3, #7 8003236: 401a ands r2, r3 8003238: 687b ldr r3, [r7, #4] 800323a: 6a9b ldr r3, [r3, #40] @ 0x28 800323c: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 800323e: 429a cmp r2, r3 8003240: d10e bne.n 8003260 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003242: 697a ldr r2, [r7, #20] 8003244: 23f8 movs r3, #248 @ 0xf8 8003246: 039b lsls r3, r3, #14 8003248: 401a ands r2, r3 800324a: 687b ldr r3, [r7, #4] 800324c: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 800324e: 429a cmp r2, r3 8003250: d106 bne.n 8003260 #if defined (RCC_PLLQ_SUPPORT) (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || #endif /* RCC_PLLQ_SUPPORT */ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 8003252: 697b ldr r3, [r7, #20] 8003254: 0f5b lsrs r3, r3, #29 8003256: 075a lsls r2, r3, #29 8003258: 687b ldr r3, [r7, #4] 800325a: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 800325c: 429a cmp r2, r3 800325e: d001 beq.n 8003264 { return HAL_ERROR; 8003260: 2301 movs r3, #1 8003262: e000 b.n 8003266 } } } } return HAL_OK; 8003264: 2300 movs r3, #0 } 8003266: 0018 movs r0, r3 8003268: 46bd mov sp, r7 800326a: b008 add sp, #32 800326c: bd80 pop {r7, pc} 800326e: 46c0 nop @ (mov r8, r8) 8003270: 40021000 .word 0x40021000 8003274: 40007000 .word 0x40007000 8003278: 00001388 .word 0x00001388 800327c: efffffff .word 0xefffffff 8003280: feffffff .word 0xfeffffff 8003284: 1fc1808c .word 0x1fc1808c 8003288: effefffc .word 0xeffefffc 0800328c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800328c: b580 push {r7, lr} 800328e: b084 sub sp, #16 8003290: af00 add r7, sp, #0 8003292: 6078 str r0, [r7, #4] 8003294: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003296: 687b ldr r3, [r7, #4] 8003298: 2b00 cmp r3, #0 800329a: d101 bne.n 80032a0 { return HAL_ERROR; 800329c: 2301 movs r3, #1 800329e: e0e9 b.n 8003474 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 80032a0: 4b76 ldr r3, [pc, #472] @ (800347c ) 80032a2: 681b ldr r3, [r3, #0] 80032a4: 2207 movs r2, #7 80032a6: 4013 ands r3, r2 80032a8: 683a ldr r2, [r7, #0] 80032aa: 429a cmp r2, r3 80032ac: d91e bls.n 80032ec { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80032ae: 4b73 ldr r3, [pc, #460] @ (800347c ) 80032b0: 681b ldr r3, [r3, #0] 80032b2: 2207 movs r2, #7 80032b4: 4393 bics r3, r2 80032b6: 0019 movs r1, r3 80032b8: 4b70 ldr r3, [pc, #448] @ (800347c ) 80032ba: 683a ldr r2, [r7, #0] 80032bc: 430a orrs r2, r1 80032be: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 80032c0: f7fe f9d4 bl 800166c 80032c4: 0003 movs r3, r0 80032c6: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80032c8: e009 b.n 80032de { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80032ca: f7fe f9cf bl 800166c 80032ce: 0002 movs r2, r0 80032d0: 68fb ldr r3, [r7, #12] 80032d2: 1ad3 subs r3, r2, r3 80032d4: 4a6a ldr r2, [pc, #424] @ (8003480 ) 80032d6: 4293 cmp r3, r2 80032d8: d901 bls.n 80032de { return HAL_TIMEOUT; 80032da: 2303 movs r3, #3 80032dc: e0ca b.n 8003474 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80032de: 4b67 ldr r3, [pc, #412] @ (800347c ) 80032e0: 681b ldr r3, [r3, #0] 80032e2: 2207 movs r2, #7 80032e4: 4013 ands r3, r2 80032e6: 683a ldr r2, [r7, #0] 80032e8: 429a cmp r2, r3 80032ea: d1ee bne.n 80032ca } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80032ec: 687b ldr r3, [r7, #4] 80032ee: 681b ldr r3, [r3, #0] 80032f0: 2202 movs r2, #2 80032f2: 4013 ands r3, r2 80032f4: d015 beq.n 8003322 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80032f6: 687b ldr r3, [r7, #4] 80032f8: 681b ldr r3, [r3, #0] 80032fa: 2204 movs r2, #4 80032fc: 4013 ands r3, r2 80032fe: d006 beq.n 800330e { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8003300: 4b60 ldr r3, [pc, #384] @ (8003484 ) 8003302: 689a ldr r2, [r3, #8] 8003304: 4b5f ldr r3, [pc, #380] @ (8003484 ) 8003306: 21e0 movs r1, #224 @ 0xe0 8003308: 01c9 lsls r1, r1, #7 800330a: 430a orrs r2, r1 800330c: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800330e: 4b5d ldr r3, [pc, #372] @ (8003484 ) 8003310: 689b ldr r3, [r3, #8] 8003312: 4a5d ldr r2, [pc, #372] @ (8003488 ) 8003314: 4013 ands r3, r2 8003316: 0019 movs r1, r3 8003318: 687b ldr r3, [r7, #4] 800331a: 689a ldr r2, [r3, #8] 800331c: 4b59 ldr r3, [pc, #356] @ (8003484 ) 800331e: 430a orrs r2, r1 8003320: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003322: 687b ldr r3, [r7, #4] 8003324: 681b ldr r3, [r3, #0] 8003326: 2201 movs r2, #1 8003328: 4013 ands r3, r2 800332a: d057 beq.n 80033dc { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800332c: 687b ldr r3, [r7, #4] 800332e: 685b ldr r3, [r3, #4] 8003330: 2b01 cmp r3, #1 8003332: d107 bne.n 8003344 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003334: 4b53 ldr r3, [pc, #332] @ (8003484 ) 8003336: 681a ldr r2, [r3, #0] 8003338: 2380 movs r3, #128 @ 0x80 800333a: 029b lsls r3, r3, #10 800333c: 4013 ands r3, r2 800333e: d12b bne.n 8003398 { return HAL_ERROR; 8003340: 2301 movs r3, #1 8003342: e097 b.n 8003474 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003344: 687b ldr r3, [r7, #4] 8003346: 685b ldr r3, [r3, #4] 8003348: 2b02 cmp r3, #2 800334a: d107 bne.n 800335c { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 800334c: 4b4d ldr r3, [pc, #308] @ (8003484 ) 800334e: 681a ldr r2, [r3, #0] 8003350: 2380 movs r3, #128 @ 0x80 8003352: 049b lsls r3, r3, #18 8003354: 4013 ands r3, r2 8003356: d11f bne.n 8003398 { return HAL_ERROR; 8003358: 2301 movs r3, #1 800335a: e08b b.n 8003474 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 800335c: 687b ldr r3, [r7, #4] 800335e: 685b ldr r3, [r3, #4] 8003360: 2b00 cmp r3, #0 8003362: d107 bne.n 8003374 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003364: 4b47 ldr r3, [pc, #284] @ (8003484 ) 8003366: 681a ldr r2, [r3, #0] 8003368: 2380 movs r3, #128 @ 0x80 800336a: 00db lsls r3, r3, #3 800336c: 4013 ands r3, r2 800336e: d113 bne.n 8003398 { return HAL_ERROR; 8003370: 2301 movs r3, #1 8003372: e07f b.n 8003474 } } /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8003374: 687b ldr r3, [r7, #4] 8003376: 685b ldr r3, [r3, #4] 8003378: 2b03 cmp r3, #3 800337a: d106 bne.n 800338a { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 800337c: 4b41 ldr r3, [pc, #260] @ (8003484 ) 800337e: 6e1b ldr r3, [r3, #96] @ 0x60 8003380: 2202 movs r2, #2 8003382: 4013 ands r3, r2 8003384: d108 bne.n 8003398 { return HAL_ERROR; 8003386: 2301 movs r3, #1 8003388: e074 b.n 8003474 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 800338a: 4b3e ldr r3, [pc, #248] @ (8003484 ) 800338c: 6ddb ldr r3, [r3, #92] @ 0x5c 800338e: 2202 movs r2, #2 8003390: 4013 ands r3, r2 8003392: d101 bne.n 8003398 { return HAL_ERROR; 8003394: 2301 movs r3, #1 8003396: e06d b.n 8003474 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8003398: 4b3a ldr r3, [pc, #232] @ (8003484 ) 800339a: 689b ldr r3, [r3, #8] 800339c: 2207 movs r2, #7 800339e: 4393 bics r3, r2 80033a0: 0019 movs r1, r3 80033a2: 687b ldr r3, [r7, #4] 80033a4: 685a ldr r2, [r3, #4] 80033a6: 4b37 ldr r3, [pc, #220] @ (8003484 ) 80033a8: 430a orrs r2, r1 80033aa: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80033ac: f7fe f95e bl 800166c 80033b0: 0003 movs r3, r0 80033b2: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80033b4: e009 b.n 80033ca { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80033b6: f7fe f959 bl 800166c 80033ba: 0002 movs r2, r0 80033bc: 68fb ldr r3, [r7, #12] 80033be: 1ad3 subs r3, r2, r3 80033c0: 4a2f ldr r2, [pc, #188] @ (8003480 ) 80033c2: 4293 cmp r3, r2 80033c4: d901 bls.n 80033ca { return HAL_TIMEOUT; 80033c6: 2303 movs r3, #3 80033c8: e054 b.n 8003474 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 80033ca: 4b2e ldr r3, [pc, #184] @ (8003484 ) 80033cc: 689b ldr r3, [r3, #8] 80033ce: 2238 movs r2, #56 @ 0x38 80033d0: 401a ands r2, r3 80033d2: 687b ldr r3, [r7, #4] 80033d4: 685b ldr r3, [r3, #4] 80033d6: 00db lsls r3, r3, #3 80033d8: 429a cmp r2, r3 80033da: d1ec bne.n 80033b6 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80033dc: 4b27 ldr r3, [pc, #156] @ (800347c ) 80033de: 681b ldr r3, [r3, #0] 80033e0: 2207 movs r2, #7 80033e2: 4013 ands r3, r2 80033e4: 683a ldr r2, [r7, #0] 80033e6: 429a cmp r2, r3 80033e8: d21e bcs.n 8003428 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80033ea: 4b24 ldr r3, [pc, #144] @ (800347c ) 80033ec: 681b ldr r3, [r3, #0] 80033ee: 2207 movs r2, #7 80033f0: 4393 bics r3, r2 80033f2: 0019 movs r1, r3 80033f4: 4b21 ldr r3, [pc, #132] @ (800347c ) 80033f6: 683a ldr r2, [r7, #0] 80033f8: 430a orrs r2, r1 80033fa: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 80033fc: f7fe f936 bl 800166c 8003400: 0003 movs r3, r0 8003402: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003404: e009 b.n 800341a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003406: f7fe f931 bl 800166c 800340a: 0002 movs r2, r0 800340c: 68fb ldr r3, [r7, #12] 800340e: 1ad3 subs r3, r2, r3 8003410: 4a1b ldr r2, [pc, #108] @ (8003480 ) 8003412: 4293 cmp r3, r2 8003414: d901 bls.n 800341a { return HAL_TIMEOUT; 8003416: 2303 movs r3, #3 8003418: e02c b.n 8003474 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 800341a: 4b18 ldr r3, [pc, #96] @ (800347c ) 800341c: 681b ldr r3, [r3, #0] 800341e: 2207 movs r2, #7 8003420: 4013 ands r3, r2 8003422: 683a ldr r2, [r7, #0] 8003424: 429a cmp r2, r3 8003426: d1ee bne.n 8003406 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003428: 687b ldr r3, [r7, #4] 800342a: 681b ldr r3, [r3, #0] 800342c: 2204 movs r2, #4 800342e: 4013 ands r3, r2 8003430: d009 beq.n 8003446 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8003432: 4b14 ldr r3, [pc, #80] @ (8003484 ) 8003434: 689b ldr r3, [r3, #8] 8003436: 4a15 ldr r2, [pc, #84] @ (800348c ) 8003438: 4013 ands r3, r2 800343a: 0019 movs r1, r3 800343c: 687b ldr r3, [r7, #4] 800343e: 68da ldr r2, [r3, #12] 8003440: 4b10 ldr r3, [pc, #64] @ (8003484 ) 8003442: 430a orrs r2, r1 8003444: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8003446: f000 f829 bl 800349c 800344a: 0001 movs r1, r0 800344c: 4b0d ldr r3, [pc, #52] @ (8003484 ) 800344e: 689b ldr r3, [r3, #8] 8003450: 0a1b lsrs r3, r3, #8 8003452: 220f movs r2, #15 8003454: 401a ands r2, r3 8003456: 4b0e ldr r3, [pc, #56] @ (8003490 ) 8003458: 0092 lsls r2, r2, #2 800345a: 58d3 ldr r3, [r2, r3] 800345c: 221f movs r2, #31 800345e: 4013 ands r3, r2 8003460: 000a movs r2, r1 8003462: 40da lsrs r2, r3 8003464: 4b0b ldr r3, [pc, #44] @ (8003494 ) 8003466: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8003468: 4b0b ldr r3, [pc, #44] @ (8003498 ) 800346a: 681b ldr r3, [r3, #0] 800346c: 0018 movs r0, r3 800346e: f7fe f8a1 bl 80015b4 8003472: 0003 movs r3, r0 } 8003474: 0018 movs r0, r3 8003476: 46bd mov sp, r7 8003478: b004 add sp, #16 800347a: bd80 pop {r7, pc} 800347c: 40022000 .word 0x40022000 8003480: 00001388 .word 0x00001388 8003484: 40021000 .word 0x40021000 8003488: fffff0ff .word 0xfffff0ff 800348c: ffff8fff .word 0xffff8fff 8003490: 08006240 .word 0x08006240 8003494: 20000000 .word 0x20000000 8003498: 20000004 .word 0x20000004 0800349c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800349c: b580 push {r7, lr} 800349e: b086 sub sp, #24 80034a0: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm, hsidiv; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 80034a2: 4b3c ldr r3, [pc, #240] @ (8003594 ) 80034a4: 689b ldr r3, [r3, #8] 80034a6: 2238 movs r2, #56 @ 0x38 80034a8: 4013 ands r3, r2 80034aa: d10f bne.n 80034cc { /* HSISYS can be derived for HSI16 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 80034ac: 4b39 ldr r3, [pc, #228] @ (8003594 ) 80034ae: 681b ldr r3, [r3, #0] 80034b0: 0adb lsrs r3, r3, #11 80034b2: 2207 movs r2, #7 80034b4: 4013 ands r3, r2 80034b6: 2201 movs r2, #1 80034b8: 409a lsls r2, r3 80034ba: 0013 movs r3, r2 80034bc: 603b str r3, [r7, #0] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 80034be: 6839 ldr r1, [r7, #0] 80034c0: 4835 ldr r0, [pc, #212] @ (8003598 ) 80034c2: f7fc fe27 bl 8000114 <__udivsi3> 80034c6: 0003 movs r3, r0 80034c8: 613b str r3, [r7, #16] 80034ca: e05d b.n 8003588 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 80034cc: 4b31 ldr r3, [pc, #196] @ (8003594 ) 80034ce: 689b ldr r3, [r3, #8] 80034d0: 2238 movs r2, #56 @ 0x38 80034d2: 4013 ands r3, r2 80034d4: 2b08 cmp r3, #8 80034d6: d102 bne.n 80034de { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80034d8: 4b30 ldr r3, [pc, #192] @ (800359c ) 80034da: 613b str r3, [r7, #16] 80034dc: e054 b.n 8003588 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 80034de: 4b2d ldr r3, [pc, #180] @ (8003594 ) 80034e0: 689b ldr r3, [r3, #8] 80034e2: 2238 movs r2, #56 @ 0x38 80034e4: 4013 ands r3, r2 80034e6: 2b10 cmp r3, #16 80034e8: d138 bne.n 800355c /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 80034ea: 4b2a ldr r3, [pc, #168] @ (8003594 ) 80034ec: 68db ldr r3, [r3, #12] 80034ee: 2203 movs r2, #3 80034f0: 4013 ands r3, r2 80034f2: 60fb str r3, [r7, #12] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 80034f4: 4b27 ldr r3, [pc, #156] @ (8003594 ) 80034f6: 68db ldr r3, [r3, #12] 80034f8: 091b lsrs r3, r3, #4 80034fa: 2207 movs r2, #7 80034fc: 4013 ands r3, r2 80034fe: 3301 adds r3, #1 8003500: 60bb str r3, [r7, #8] switch (pllsource) 8003502: 68fb ldr r3, [r7, #12] 8003504: 2b03 cmp r3, #3 8003506: d10d bne.n 8003524 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003508: 68b9 ldr r1, [r7, #8] 800350a: 4824 ldr r0, [pc, #144] @ (800359c ) 800350c: f7fc fe02 bl 8000114 <__udivsi3> 8003510: 0003 movs r3, r0 8003512: 0019 movs r1, r3 8003514: 4b1f ldr r3, [pc, #124] @ (8003594 ) 8003516: 68db ldr r3, [r3, #12] 8003518: 0a1b lsrs r3, r3, #8 800351a: 227f movs r2, #127 @ 0x7f 800351c: 4013 ands r3, r2 800351e: 434b muls r3, r1 8003520: 617b str r3, [r7, #20] break; 8003522: e00d b.n 8003540 case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ default: /* HSI16 used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; 8003524: 68b9 ldr r1, [r7, #8] 8003526: 481c ldr r0, [pc, #112] @ (8003598 ) 8003528: f7fc fdf4 bl 8000114 <__udivsi3> 800352c: 0003 movs r3, r0 800352e: 0019 movs r1, r3 8003530: 4b18 ldr r3, [pc, #96] @ (8003594 ) 8003532: 68db ldr r3, [r3, #12] 8003534: 0a1b lsrs r3, r3, #8 8003536: 227f movs r2, #127 @ 0x7f 8003538: 4013 ands r3, r2 800353a: 434b muls r3, r1 800353c: 617b str r3, [r7, #20] break; 800353e: 46c0 nop @ (mov r8, r8) } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); 8003540: 4b14 ldr r3, [pc, #80] @ (8003594 ) 8003542: 68db ldr r3, [r3, #12] 8003544: 0f5b lsrs r3, r3, #29 8003546: 2207 movs r2, #7 8003548: 4013 ands r3, r2 800354a: 3301 adds r3, #1 800354c: 607b str r3, [r7, #4] sysclockfreq = pllvco / pllr; 800354e: 6879 ldr r1, [r7, #4] 8003550: 6978 ldr r0, [r7, #20] 8003552: f7fc fddf bl 8000114 <__udivsi3> 8003556: 0003 movs r3, r0 8003558: 613b str r3, [r7, #16] 800355a: e015 b.n 8003588 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 800355c: 4b0d ldr r3, [pc, #52] @ (8003594 ) 800355e: 689b ldr r3, [r3, #8] 8003560: 2238 movs r2, #56 @ 0x38 8003562: 4013 ands r3, r2 8003564: 2b20 cmp r3, #32 8003566: d103 bne.n 8003570 { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 8003568: 2380 movs r3, #128 @ 0x80 800356a: 021b lsls r3, r3, #8 800356c: 613b str r3, [r7, #16] 800356e: e00b b.n 8003588 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8003570: 4b08 ldr r3, [pc, #32] @ (8003594 ) 8003572: 689b ldr r3, [r3, #8] 8003574: 2238 movs r2, #56 @ 0x38 8003576: 4013 ands r3, r2 8003578: 2b18 cmp r3, #24 800357a: d103 bne.n 8003584 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 800357c: 23fa movs r3, #250 @ 0xfa 800357e: 01db lsls r3, r3, #7 8003580: 613b str r3, [r7, #16] 8003582: e001 b.n 8003588 } else { sysclockfreq = 0U; 8003584: 2300 movs r3, #0 8003586: 613b str r3, [r7, #16] } return sysclockfreq; 8003588: 693b ldr r3, [r7, #16] } 800358a: 0018 movs r0, r3 800358c: 46bd mov sp, r7 800358e: b006 add sp, #24 8003590: bd80 pop {r7, pc} 8003592: 46c0 nop @ (mov r8, r8) 8003594: 40021000 .word 0x40021000 8003598: 00f42400 .word 0x00f42400 800359c: 007a1200 .word 0x007a1200 080035a0 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80035a0: b580 push {r7, lr} 80035a2: af00 add r7, sp, #0 return SystemCoreClock; 80035a4: 4b02 ldr r3, [pc, #8] @ (80035b0 ) 80035a6: 681b ldr r3, [r3, #0] } 80035a8: 0018 movs r0, r3 80035aa: 46bd mov sp, r7 80035ac: bd80 pop {r7, pc} 80035ae: 46c0 nop @ (mov r8, r8) 80035b0: 20000000 .word 0x20000000 080035b4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80035b4: b5b0 push {r4, r5, r7, lr} 80035b6: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); 80035b8: f7ff fff2 bl 80035a0 80035bc: 0004 movs r4, r0 80035be: f7ff fb49 bl 8002c54 80035c2: 0003 movs r3, r0 80035c4: 0b1a lsrs r2, r3, #12 80035c6: 4b05 ldr r3, [pc, #20] @ (80035dc ) 80035c8: 0092 lsls r2, r2, #2 80035ca: 58d3 ldr r3, [r2, r3] 80035cc: 221f movs r2, #31 80035ce: 4013 ands r3, r2 80035d0: 40dc lsrs r4, r3 80035d2: 0023 movs r3, r4 } 80035d4: 0018 movs r0, r3 80035d6: 46bd mov sp, r7 80035d8: bdb0 pop {r4, r5, r7, pc} 80035da: 46c0 nop @ (mov r8, r8) 80035dc: 08006280 .word 0x08006280 080035e0 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80035e0: b580 push {r7, lr} 80035e2: b086 sub sp, #24 80035e4: af00 add r7, sp, #0 80035e6: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80035e8: 2313 movs r3, #19 80035ea: 18fb adds r3, r7, r3 80035ec: 2200 movs r2, #0 80035ee: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80035f0: 2312 movs r3, #18 80035f2: 18fb adds r3, r7, r3 80035f4: 2200 movs r2, #0 80035f6: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 80035f8: 687b ldr r3, [r7, #4] 80035fa: 681a ldr r2, [r3, #0] 80035fc: 2380 movs r3, #128 @ 0x80 80035fe: 029b lsls r3, r3, #10 8003600: 4013 ands r3, r2 8003602: d100 bne.n 8003606 8003604: e0a3 b.n 800374e { FlagStatus pwrclkchanged = RESET; 8003606: 2011 movs r0, #17 8003608: 183b adds r3, r7, r0 800360a: 2200 movs r2, #0 800360c: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800360e: 4b86 ldr r3, [pc, #536] @ (8003828 ) 8003610: 6bda ldr r2, [r3, #60] @ 0x3c 8003612: 2380 movs r3, #128 @ 0x80 8003614: 055b lsls r3, r3, #21 8003616: 4013 ands r3, r2 8003618: d110 bne.n 800363c { __HAL_RCC_PWR_CLK_ENABLE(); 800361a: 4b83 ldr r3, [pc, #524] @ (8003828 ) 800361c: 6bda ldr r2, [r3, #60] @ 0x3c 800361e: 4b82 ldr r3, [pc, #520] @ (8003828 ) 8003620: 2180 movs r1, #128 @ 0x80 8003622: 0549 lsls r1, r1, #21 8003624: 430a orrs r2, r1 8003626: 63da str r2, [r3, #60] @ 0x3c 8003628: 4b7f ldr r3, [pc, #508] @ (8003828 ) 800362a: 6bda ldr r2, [r3, #60] @ 0x3c 800362c: 2380 movs r3, #128 @ 0x80 800362e: 055b lsls r3, r3, #21 8003630: 4013 ands r3, r2 8003632: 60bb str r3, [r7, #8] 8003634: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003636: 183b adds r3, r7, r0 8003638: 2201 movs r2, #1 800363a: 701a strb r2, [r3, #0] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800363c: 4b7b ldr r3, [pc, #492] @ (800382c ) 800363e: 681a ldr r2, [r3, #0] 8003640: 4b7a ldr r3, [pc, #488] @ (800382c ) 8003642: 2180 movs r1, #128 @ 0x80 8003644: 0049 lsls r1, r1, #1 8003646: 430a orrs r2, r1 8003648: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800364a: f7fe f80f bl 800166c 800364e: 0003 movs r3, r0 8003650: 60fb str r3, [r7, #12] while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003652: e00b b.n 800366c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003654: f7fe f80a bl 800166c 8003658: 0002 movs r2, r0 800365a: 68fb ldr r3, [r7, #12] 800365c: 1ad3 subs r3, r2, r3 800365e: 2b02 cmp r3, #2 8003660: d904 bls.n 800366c { ret = HAL_TIMEOUT; 8003662: 2313 movs r3, #19 8003664: 18fb adds r3, r7, r3 8003666: 2203 movs r2, #3 8003668: 701a strb r2, [r3, #0] break; 800366a: e005 b.n 8003678 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800366c: 4b6f ldr r3, [pc, #444] @ (800382c ) 800366e: 681a ldr r2, [r3, #0] 8003670: 2380 movs r3, #128 @ 0x80 8003672: 005b lsls r3, r3, #1 8003674: 4013 ands r3, r2 8003676: d0ed beq.n 8003654 } } if (ret == HAL_OK) 8003678: 2313 movs r3, #19 800367a: 18fb adds r3, r7, r3 800367c: 781b ldrb r3, [r3, #0] 800367e: 2b00 cmp r3, #0 8003680: d154 bne.n 800372c { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8003682: 4b69 ldr r3, [pc, #420] @ (8003828 ) 8003684: 6dda ldr r2, [r3, #92] @ 0x5c 8003686: 23c0 movs r3, #192 @ 0xc0 8003688: 009b lsls r3, r3, #2 800368a: 4013 ands r3, r2 800368c: 617b str r3, [r7, #20] /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800368e: 697b ldr r3, [r7, #20] 8003690: 2b00 cmp r3, #0 8003692: d019 beq.n 80036c8 8003694: 687b ldr r3, [r7, #4] 8003696: 699b ldr r3, [r3, #24] 8003698: 697a ldr r2, [r7, #20] 800369a: 429a cmp r2, r3 800369c: d014 beq.n 80036c8 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 800369e: 4b62 ldr r3, [pc, #392] @ (8003828 ) 80036a0: 6ddb ldr r3, [r3, #92] @ 0x5c 80036a2: 4a63 ldr r2, [pc, #396] @ (8003830 ) 80036a4: 4013 ands r3, r2 80036a6: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80036a8: 4b5f ldr r3, [pc, #380] @ (8003828 ) 80036aa: 6dda ldr r2, [r3, #92] @ 0x5c 80036ac: 4b5e ldr r3, [pc, #376] @ (8003828 ) 80036ae: 2180 movs r1, #128 @ 0x80 80036b0: 0249 lsls r1, r1, #9 80036b2: 430a orrs r2, r1 80036b4: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); 80036b6: 4b5c ldr r3, [pc, #368] @ (8003828 ) 80036b8: 6dda ldr r2, [r3, #92] @ 0x5c 80036ba: 4b5b ldr r3, [pc, #364] @ (8003828 ) 80036bc: 495d ldr r1, [pc, #372] @ (8003834 ) 80036be: 400a ands r2, r1 80036c0: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 80036c2: 4b59 ldr r3, [pc, #356] @ (8003828 ) 80036c4: 697a ldr r2, [r7, #20] 80036c6: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80036c8: 697b ldr r3, [r7, #20] 80036ca: 2201 movs r2, #1 80036cc: 4013 ands r3, r2 80036ce: d016 beq.n 80036fe { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80036d0: f7fd ffcc bl 800166c 80036d4: 0003 movs r3, r0 80036d6: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80036d8: e00c b.n 80036f4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80036da: f7fd ffc7 bl 800166c 80036de: 0002 movs r2, r0 80036e0: 68fb ldr r3, [r7, #12] 80036e2: 1ad3 subs r3, r2, r3 80036e4: 4a54 ldr r2, [pc, #336] @ (8003838 ) 80036e6: 4293 cmp r3, r2 80036e8: d904 bls.n 80036f4 { ret = HAL_TIMEOUT; 80036ea: 2313 movs r3, #19 80036ec: 18fb adds r3, r7, r3 80036ee: 2203 movs r2, #3 80036f0: 701a strb r2, [r3, #0] break; 80036f2: e004 b.n 80036fe while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80036f4: 4b4c ldr r3, [pc, #304] @ (8003828 ) 80036f6: 6ddb ldr r3, [r3, #92] @ 0x5c 80036f8: 2202 movs r2, #2 80036fa: 4013 ands r3, r2 80036fc: d0ed beq.n 80036da } } } if (ret == HAL_OK) 80036fe: 2313 movs r3, #19 8003700: 18fb adds r3, r7, r3 8003702: 781b ldrb r3, [r3, #0] 8003704: 2b00 cmp r3, #0 8003706: d10a bne.n 800371e { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003708: 4b47 ldr r3, [pc, #284] @ (8003828 ) 800370a: 6ddb ldr r3, [r3, #92] @ 0x5c 800370c: 4a48 ldr r2, [pc, #288] @ (8003830 ) 800370e: 4013 ands r3, r2 8003710: 0019 movs r1, r3 8003712: 687b ldr r3, [r7, #4] 8003714: 699a ldr r2, [r3, #24] 8003716: 4b44 ldr r3, [pc, #272] @ (8003828 ) 8003718: 430a orrs r2, r1 800371a: 65da str r2, [r3, #92] @ 0x5c 800371c: e00c b.n 8003738 } else { /* set overall return value */ status = ret; 800371e: 2312 movs r3, #18 8003720: 18fb adds r3, r7, r3 8003722: 2213 movs r2, #19 8003724: 18ba adds r2, r7, r2 8003726: 7812 ldrb r2, [r2, #0] 8003728: 701a strb r2, [r3, #0] 800372a: e005 b.n 8003738 } } else { /* set overall return value */ status = ret; 800372c: 2312 movs r3, #18 800372e: 18fb adds r3, r7, r3 8003730: 2213 movs r2, #19 8003732: 18ba adds r2, r7, r2 8003734: 7812 ldrb r2, [r2, #0] 8003736: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8003738: 2311 movs r3, #17 800373a: 18fb adds r3, r7, r3 800373c: 781b ldrb r3, [r3, #0] 800373e: 2b01 cmp r3, #1 8003740: d105 bne.n 800374e { __HAL_RCC_PWR_CLK_DISABLE(); 8003742: 4b39 ldr r3, [pc, #228] @ (8003828 ) 8003744: 6bda ldr r2, [r3, #60] @ 0x3c 8003746: 4b38 ldr r3, [pc, #224] @ (8003828 ) 8003748: 493c ldr r1, [pc, #240] @ (800383c ) 800374a: 400a ands r2, r1 800374c: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 800374e: 687b ldr r3, [r7, #4] 8003750: 681b ldr r3, [r3, #0] 8003752: 2201 movs r2, #1 8003754: 4013 ands r3, r2 8003756: d009 beq.n 800376c { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003758: 4b33 ldr r3, [pc, #204] @ (8003828 ) 800375a: 6d5b ldr r3, [r3, #84] @ 0x54 800375c: 2203 movs r2, #3 800375e: 4393 bics r3, r2 8003760: 0019 movs r1, r3 8003762: 687b ldr r3, [r7, #4] 8003764: 685a ldr r2, [r3, #4] 8003766: 4b30 ldr r3, [pc, #192] @ (8003828 ) 8003768: 430a orrs r2, r1 800376a: 655a str r2, [r3, #84] @ 0x54 } #if defined(RCC_CCIPR_USART2SEL) /*-------------------------- USART2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 800376c: 687b ldr r3, [r7, #4] 800376e: 681b ldr r3, [r3, #0] 8003770: 2202 movs r2, #2 8003772: 4013 ands r3, r2 8003774: d009 beq.n 800378a { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8003776: 4b2c ldr r3, [pc, #176] @ (8003828 ) 8003778: 6d5b ldr r3, [r3, #84] @ 0x54 800377a: 220c movs r2, #12 800377c: 4393 bics r3, r2 800377e: 0019 movs r1, r3 8003780: 687b ldr r3, [r7, #4] 8003782: 689a ldr r2, [r3, #8] 8003784: 4b28 ldr r3, [pc, #160] @ (8003828 ) 8003786: 430a orrs r2, r1 8003788: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); } #endif /* RCC_CCIPR_LPTIM2SEL */ /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 800378a: 687b ldr r3, [r7, #4] 800378c: 681b ldr r3, [r3, #0] 800378e: 2220 movs r2, #32 8003790: 4013 ands r3, r2 8003792: d009 beq.n 80037a8 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003794: 4b24 ldr r3, [pc, #144] @ (8003828 ) 8003796: 6d5b ldr r3, [r3, #84] @ 0x54 8003798: 4a29 ldr r2, [pc, #164] @ (8003840 ) 800379a: 4013 ands r3, r2 800379c: 0019 movs r1, r3 800379e: 687b ldr r3, [r7, #4] 80037a0: 68da ldr r2, [r3, #12] 80037a2: 4b21 ldr r3, [pc, #132] @ (8003828 ) 80037a4: 430a orrs r2, r1 80037a6: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* RNG */ /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80037a8: 687b ldr r3, [r7, #4] 80037aa: 681a ldr r2, [r3, #0] 80037ac: 2380 movs r3, #128 @ 0x80 80037ae: 01db lsls r3, r3, #7 80037b0: 4013 ands r3, r2 80037b2: d015 beq.n 80037e0 { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80037b4: 4b1c ldr r3, [pc, #112] @ (8003828 ) 80037b6: 6d5b ldr r3, [r3, #84] @ 0x54 80037b8: 009b lsls r3, r3, #2 80037ba: 0899 lsrs r1, r3, #2 80037bc: 687b ldr r3, [r7, #4] 80037be: 695a ldr r2, [r3, #20] 80037c0: 4b19 ldr r3, [pc, #100] @ (8003828 ) 80037c2: 430a orrs r2, r1 80037c4: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) 80037c6: 687b ldr r3, [r7, #4] 80037c8: 695a ldr r2, [r3, #20] 80037ca: 2380 movs r3, #128 @ 0x80 80037cc: 05db lsls r3, r3, #23 80037ce: 429a cmp r2, r3 80037d0: d106 bne.n 80037e0 { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 80037d2: 4b15 ldr r3, [pc, #84] @ (8003828 ) 80037d4: 68da ldr r2, [r3, #12] 80037d6: 4b14 ldr r3, [pc, #80] @ (8003828 ) 80037d8: 2180 movs r1, #128 @ 0x80 80037da: 0249 lsls r1, r1, #9 80037dc: 430a orrs r2, r1 80037de: 60da str r2, [r3, #12] } } #endif /* RCC_CCIPR_TIM15SEL */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) 80037e0: 687b ldr r3, [r7, #4] 80037e2: 681a ldr r2, [r3, #0] 80037e4: 2380 movs r3, #128 @ 0x80 80037e6: 011b lsls r3, r3, #4 80037e8: 4013 ands r3, r2 80037ea: d016 beq.n 800381a { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); 80037ec: 4b0e ldr r3, [pc, #56] @ (8003828 ) 80037ee: 6d5b ldr r3, [r3, #84] @ 0x54 80037f0: 4a14 ldr r2, [pc, #80] @ (8003844 ) 80037f2: 4013 ands r3, r2 80037f4: 0019 movs r1, r3 80037f6: 687b ldr r3, [r7, #4] 80037f8: 691a ldr r2, [r3, #16] 80037fa: 4b0b ldr r3, [pc, #44] @ (8003828 ) 80037fc: 430a orrs r2, r1 80037fe: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) 8003800: 687b ldr r3, [r7, #4] 8003802: 691a ldr r2, [r3, #16] 8003804: 2380 movs r3, #128 @ 0x80 8003806: 01db lsls r3, r3, #7 8003808: 429a cmp r2, r3 800380a: d106 bne.n 800381a { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 800380c: 4b06 ldr r3, [pc, #24] @ (8003828 ) 800380e: 68da ldr r2, [r3, #12] 8003810: 4b05 ldr r3, [pc, #20] @ (8003828 ) 8003812: 2180 movs r1, #128 @ 0x80 8003814: 0249 lsls r1, r1, #9 8003816: 430a orrs r2, r1 8003818: 60da str r2, [r3, #12] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* FDCAN1 || FDCAN2 */ return status; 800381a: 2312 movs r3, #18 800381c: 18fb adds r3, r7, r3 800381e: 781b ldrb r3, [r3, #0] } 8003820: 0018 movs r0, r3 8003822: 46bd mov sp, r7 8003824: b006 add sp, #24 8003826: bd80 pop {r7, pc} 8003828: 40021000 .word 0x40021000 800382c: 40007000 .word 0x40007000 8003830: fffffcff .word 0xfffffcff 8003834: fffeffff .word 0xfffeffff 8003838: 00001388 .word 0x00001388 800383c: efffffff .word 0xefffffff 8003840: ffffcfff .word 0xffffcfff 8003844: ffff3fff .word 0xffff3fff 08003848 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 8003848: b580 push {r7, lr} 800384a: b084 sub sp, #16 800384c: af00 add r7, sp, #0 800384e: 6078 str r0, [r7, #4] uint32_t frxth; /* Check the SPI handle allocation */ if (hspi == NULL) 8003850: 687b ldr r3, [r7, #4] 8003852: 2b00 cmp r3, #0 8003854: d101 bne.n 800385a { return HAL_ERROR; 8003856: 2301 movs r3, #1 8003858: e0a8 b.n 80039ac assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 800385a: 687b ldr r3, [r7, #4] 800385c: 6a5b ldr r3, [r3, #36] @ 0x24 800385e: 2b00 cmp r3, #0 8003860: d109 bne.n 8003876 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8003862: 687b ldr r3, [r7, #4] 8003864: 685a ldr r2, [r3, #4] 8003866: 2382 movs r3, #130 @ 0x82 8003868: 005b lsls r3, r3, #1 800386a: 429a cmp r2, r3 800386c: d009 beq.n 8003882 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800386e: 687b ldr r3, [r7, #4] 8003870: 2200 movs r2, #0 8003872: 61da str r2, [r3, #28] 8003874: e005 b.n 8003882 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8003876: 687b ldr r3, [r7, #4] 8003878: 2200 movs r2, #0 800387a: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 800387c: 687b ldr r3, [r7, #4] 800387e: 2200 movs r2, #0 8003880: 615a str r2, [r3, #20] { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8003882: 687b ldr r3, [r7, #4] 8003884: 2200 movs r2, #0 8003886: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 8003888: 687b ldr r3, [r7, #4] 800388a: 225d movs r2, #93 @ 0x5d 800388c: 5c9b ldrb r3, [r3, r2] 800388e: b2db uxtb r3, r3 8003890: 2b00 cmp r3, #0 8003892: d107 bne.n 80038a4 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8003894: 687b ldr r3, [r7, #4] 8003896: 225c movs r2, #92 @ 0x5c 8003898: 2100 movs r1, #0 800389a: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800389c: 687b ldr r3, [r7, #4] 800389e: 0018 movs r0, r3 80038a0: f7fd fcc0 bl 8001224 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 80038a4: 687b ldr r3, [r7, #4] 80038a6: 225d movs r2, #93 @ 0x5d 80038a8: 2102 movs r1, #2 80038aa: 5499 strb r1, [r3, r2] /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80038ac: 687b ldr r3, [r7, #4] 80038ae: 681b ldr r3, [r3, #0] 80038b0: 681a ldr r2, [r3, #0] 80038b2: 687b ldr r3, [r7, #4] 80038b4: 681b ldr r3, [r3, #0] 80038b6: 2140 movs r1, #64 @ 0x40 80038b8: 438a bics r2, r1 80038ba: 601a str r2, [r3, #0] /* Align by default the rs fifo threshold on the data size */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 80038bc: 687b ldr r3, [r7, #4] 80038be: 68da ldr r2, [r3, #12] 80038c0: 23e0 movs r3, #224 @ 0xe0 80038c2: 00db lsls r3, r3, #3 80038c4: 429a cmp r2, r3 80038c6: d902 bls.n 80038ce { frxth = SPI_RXFIFO_THRESHOLD_HF; 80038c8: 2300 movs r3, #0 80038ca: 60fb str r3, [r7, #12] 80038cc: e002 b.n 80038d4 } else { frxth = SPI_RXFIFO_THRESHOLD_QF; 80038ce: 2380 movs r3, #128 @ 0x80 80038d0: 015b lsls r3, r3, #5 80038d2: 60fb str r3, [r7, #12] } /* CRC calculation is valid only for 16Bit and 8 Bit */ if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) 80038d4: 687b ldr r3, [r7, #4] 80038d6: 68da ldr r2, [r3, #12] 80038d8: 23f0 movs r3, #240 @ 0xf0 80038da: 011b lsls r3, r3, #4 80038dc: 429a cmp r2, r3 80038de: d008 beq.n 80038f2 80038e0: 687b ldr r3, [r7, #4] 80038e2: 68da ldr r2, [r3, #12] 80038e4: 23e0 movs r3, #224 @ 0xe0 80038e6: 00db lsls r3, r3, #3 80038e8: 429a cmp r2, r3 80038ea: d002 beq.n 80038f2 { /* CRC must be disabled */ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80038ec: 687b ldr r3, [r7, #4] 80038ee: 2200 movs r2, #0 80038f0: 629a str r2, [r3, #40] @ 0x28 } /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 80038f2: 687b ldr r3, [r7, #4] 80038f4: 685a ldr r2, [r3, #4] 80038f6: 2382 movs r3, #130 @ 0x82 80038f8: 005b lsls r3, r3, #1 80038fa: 401a ands r2, r3 80038fc: 687b ldr r3, [r7, #4] 80038fe: 6899 ldr r1, [r3, #8] 8003900: 2384 movs r3, #132 @ 0x84 8003902: 021b lsls r3, r3, #8 8003904: 400b ands r3, r1 8003906: 431a orrs r2, r3 8003908: 687b ldr r3, [r7, #4] 800390a: 691b ldr r3, [r3, #16] 800390c: 2102 movs r1, #2 800390e: 400b ands r3, r1 8003910: 431a orrs r2, r3 8003912: 687b ldr r3, [r7, #4] 8003914: 695b ldr r3, [r3, #20] 8003916: 2101 movs r1, #1 8003918: 400b ands r3, r1 800391a: 431a orrs r2, r3 800391c: 687b ldr r3, [r7, #4] 800391e: 6999 ldr r1, [r3, #24] 8003920: 2380 movs r3, #128 @ 0x80 8003922: 009b lsls r3, r3, #2 8003924: 400b ands r3, r1 8003926: 431a orrs r2, r3 8003928: 687b ldr r3, [r7, #4] 800392a: 69db ldr r3, [r3, #28] 800392c: 2138 movs r1, #56 @ 0x38 800392e: 400b ands r3, r1 8003930: 431a orrs r2, r3 8003932: 687b ldr r3, [r7, #4] 8003934: 6a1b ldr r3, [r3, #32] 8003936: 2180 movs r1, #128 @ 0x80 8003938: 400b ands r3, r1 800393a: 431a orrs r2, r3 800393c: 0011 movs r1, r2 800393e: 687b ldr r3, [r7, #4] 8003940: 6a9a ldr r2, [r3, #40] @ 0x28 8003942: 2380 movs r3, #128 @ 0x80 8003944: 019b lsls r3, r3, #6 8003946: 401a ands r2, r3 8003948: 687b ldr r3, [r7, #4] 800394a: 681b ldr r3, [r3, #0] 800394c: 430a orrs r2, r1 800394e: 601a str r2, [r3, #0] } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | 8003950: 687b ldr r3, [r7, #4] 8003952: 699b ldr r3, [r3, #24] 8003954: 0c1b lsrs r3, r3, #16 8003956: 2204 movs r2, #4 8003958: 401a ands r2, r3 800395a: 687b ldr r3, [r7, #4] 800395c: 6a5b ldr r3, [r3, #36] @ 0x24 800395e: 2110 movs r1, #16 8003960: 400b ands r3, r1 8003962: 431a orrs r2, r3 8003964: 687b ldr r3, [r7, #4] 8003966: 6b5b ldr r3, [r3, #52] @ 0x34 8003968: 2108 movs r1, #8 800396a: 400b ands r3, r1 800396c: 431a orrs r2, r3 800396e: 687b ldr r3, [r7, #4] 8003970: 68d9 ldr r1, [r3, #12] 8003972: 23f0 movs r3, #240 @ 0xf0 8003974: 011b lsls r3, r3, #4 8003976: 400b ands r3, r1 8003978: 431a orrs r2, r3 800397a: 0011 movs r1, r2 800397c: 68fa ldr r2, [r7, #12] 800397e: 2380 movs r3, #128 @ 0x80 8003980: 015b lsls r3, r3, #5 8003982: 401a ands r2, r3 8003984: 687b ldr r3, [r7, #4] 8003986: 681b ldr r3, [r3, #0] 8003988: 430a orrs r2, r1 800398a: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 800398c: 687b ldr r3, [r7, #4] 800398e: 681b ldr r3, [r3, #0] 8003990: 69da ldr r2, [r3, #28] 8003992: 687b ldr r3, [r7, #4] 8003994: 681b ldr r3, [r3, #0] 8003996: 4907 ldr r1, [pc, #28] @ (80039b4 ) 8003998: 400a ands r2, r1 800399a: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 800399c: 687b ldr r3, [r7, #4] 800399e: 2200 movs r2, #0 80039a0: 661a str r2, [r3, #96] @ 0x60 hspi->State = HAL_SPI_STATE_READY; 80039a2: 687b ldr r3, [r7, #4] 80039a4: 225d movs r2, #93 @ 0x5d 80039a6: 2101 movs r1, #1 80039a8: 5499 strb r1, [r3, r2] return HAL_OK; 80039aa: 2300 movs r3, #0 } 80039ac: 0018 movs r0, r3 80039ae: 46bd mov sp, r7 80039b0: b004 add sp, #16 80039b2: bd80 pop {r7, pc} 80039b4: fffff7ff .word 0xfffff7ff 080039b8 : * @param Size amount of data to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 80039b8: b580 push {r7, lr} 80039ba: b088 sub sp, #32 80039bc: af00 add r7, sp, #0 80039be: 60f8 str r0, [r7, #12] 80039c0: 60b9 str r1, [r7, #8] 80039c2: 603b str r3, [r7, #0] 80039c4: 1dbb adds r3, r7, #6 80039c6: 801a strh r2, [r3, #0] uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; 80039c8: 231f movs r3, #31 80039ca: 18fb adds r3, r7, r3 80039cc: 2200 movs r2, #0 80039ce: 701a strb r2, [r3, #0] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); 80039d0: 68fb ldr r3, [r7, #12] 80039d2: 225c movs r2, #92 @ 0x5c 80039d4: 5c9b ldrb r3, [r3, r2] 80039d6: 2b01 cmp r3, #1 80039d8: d101 bne.n 80039de 80039da: 2302 movs r3, #2 80039dc: e147 b.n 8003c6e 80039de: 68fb ldr r3, [r7, #12] 80039e0: 225c movs r2, #92 @ 0x5c 80039e2: 2101 movs r1, #1 80039e4: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 80039e6: f7fd fe41 bl 800166c 80039ea: 0003 movs r3, r0 80039ec: 61bb str r3, [r7, #24] initial_TxXferCount = Size; 80039ee: 2316 movs r3, #22 80039f0: 18fb adds r3, r7, r3 80039f2: 1dba adds r2, r7, #6 80039f4: 8812 ldrh r2, [r2, #0] 80039f6: 801a strh r2, [r3, #0] if (hspi->State != HAL_SPI_STATE_READY) 80039f8: 68fb ldr r3, [r7, #12] 80039fa: 225d movs r2, #93 @ 0x5d 80039fc: 5c9b ldrb r3, [r3, r2] 80039fe: b2db uxtb r3, r3 8003a00: 2b01 cmp r3, #1 8003a02: d004 beq.n 8003a0e { errorcode = HAL_BUSY; 8003a04: 231f movs r3, #31 8003a06: 18fb adds r3, r7, r3 8003a08: 2202 movs r2, #2 8003a0a: 701a strb r2, [r3, #0] goto error; 8003a0c: e128 b.n 8003c60 } if ((pData == NULL) || (Size == 0U)) 8003a0e: 68bb ldr r3, [r7, #8] 8003a10: 2b00 cmp r3, #0 8003a12: d003 beq.n 8003a1c 8003a14: 1dbb adds r3, r7, #6 8003a16: 881b ldrh r3, [r3, #0] 8003a18: 2b00 cmp r3, #0 8003a1a: d104 bne.n 8003a26 { errorcode = HAL_ERROR; 8003a1c: 231f movs r3, #31 8003a1e: 18fb adds r3, r7, r3 8003a20: 2201 movs r2, #1 8003a22: 701a strb r2, [r3, #0] goto error; 8003a24: e11c b.n 8003c60 } /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; 8003a26: 68fb ldr r3, [r7, #12] 8003a28: 225d movs r2, #93 @ 0x5d 8003a2a: 2103 movs r1, #3 8003a2c: 5499 strb r1, [r3, r2] hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8003a2e: 68fb ldr r3, [r7, #12] 8003a30: 2200 movs r2, #0 8003a32: 661a str r2, [r3, #96] @ 0x60 hspi->pTxBuffPtr = (uint8_t *)pData; 8003a34: 68fb ldr r3, [r7, #12] 8003a36: 68ba ldr r2, [r7, #8] 8003a38: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = Size; 8003a3a: 68fb ldr r3, [r7, #12] 8003a3c: 1dba adds r2, r7, #6 8003a3e: 8812 ldrh r2, [r2, #0] 8003a40: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = Size; 8003a42: 68fb ldr r3, [r7, #12] 8003a44: 1dba adds r2, r7, #6 8003a46: 8812 ldrh r2, [r2, #0] 8003a48: 87da strh r2, [r3, #62] @ 0x3e /*Init field not used in handle to zero */ hspi->pRxBuffPtr = (uint8_t *)NULL; 8003a4a: 68fb ldr r3, [r7, #12] 8003a4c: 2200 movs r2, #0 8003a4e: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = 0U; 8003a50: 68fb ldr r3, [r7, #12] 8003a52: 2244 movs r2, #68 @ 0x44 8003a54: 2100 movs r1, #0 8003a56: 5299 strh r1, [r3, r2] hspi->RxXferCount = 0U; 8003a58: 68fb ldr r3, [r7, #12] 8003a5a: 2246 movs r2, #70 @ 0x46 8003a5c: 2100 movs r1, #0 8003a5e: 5299 strh r1, [r3, r2] hspi->TxISR = NULL; 8003a60: 68fb ldr r3, [r7, #12] 8003a62: 2200 movs r2, #0 8003a64: 651a str r2, [r3, #80] @ 0x50 hspi->RxISR = NULL; 8003a66: 68fb ldr r3, [r7, #12] 8003a68: 2200 movs r2, #0 8003a6a: 64da str r2, [r3, #76] @ 0x4c /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 8003a6c: 68fb ldr r3, [r7, #12] 8003a6e: 689a ldr r2, [r3, #8] 8003a70: 2380 movs r3, #128 @ 0x80 8003a72: 021b lsls r3, r3, #8 8003a74: 429a cmp r2, r3 8003a76: d110 bne.n 8003a9a { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8003a78: 68fb ldr r3, [r7, #12] 8003a7a: 681b ldr r3, [r3, #0] 8003a7c: 681a ldr r2, [r3, #0] 8003a7e: 68fb ldr r3, [r7, #12] 8003a80: 681b ldr r3, [r3, #0] 8003a82: 2140 movs r1, #64 @ 0x40 8003a84: 438a bics r2, r1 8003a86: 601a str r2, [r3, #0] SPI_1LINE_TX(hspi); 8003a88: 68fb ldr r3, [r7, #12] 8003a8a: 681b ldr r3, [r3, #0] 8003a8c: 681a ldr r2, [r3, #0] 8003a8e: 68fb ldr r3, [r7, #12] 8003a90: 681b ldr r3, [r3, #0] 8003a92: 2180 movs r1, #128 @ 0x80 8003a94: 01c9 lsls r1, r1, #7 8003a96: 430a orrs r2, r1 8003a98: 601a str r2, [r3, #0] SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8003a9a: 68fb ldr r3, [r7, #12] 8003a9c: 681b ldr r3, [r3, #0] 8003a9e: 681b ldr r3, [r3, #0] 8003aa0: 2240 movs r2, #64 @ 0x40 8003aa2: 4013 ands r3, r2 8003aa4: 2b40 cmp r3, #64 @ 0x40 8003aa6: d007 beq.n 8003ab8 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8003aa8: 68fb ldr r3, [r7, #12] 8003aaa: 681b ldr r3, [r3, #0] 8003aac: 681a ldr r2, [r3, #0] 8003aae: 68fb ldr r3, [r7, #12] 8003ab0: 681b ldr r3, [r3, #0] 8003ab2: 2140 movs r1, #64 @ 0x40 8003ab4: 430a orrs r2, r1 8003ab6: 601a str r2, [r3, #0] } /* Transmit data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8003ab8: 68fb ldr r3, [r7, #12] 8003aba: 68da ldr r2, [r3, #12] 8003abc: 23e0 movs r3, #224 @ 0xe0 8003abe: 00db lsls r3, r3, #3 8003ac0: 429a cmp r2, r3 8003ac2: d952 bls.n 8003b6a { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8003ac4: 68fb ldr r3, [r7, #12] 8003ac6: 685b ldr r3, [r3, #4] 8003ac8: 2b00 cmp r3, #0 8003aca: d004 beq.n 8003ad6 8003acc: 2316 movs r3, #22 8003ace: 18fb adds r3, r7, r3 8003ad0: 881b ldrh r3, [r3, #0] 8003ad2: 2b01 cmp r3, #1 8003ad4: d143 bne.n 8003b5e { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8003ad6: 68fb ldr r3, [r7, #12] 8003ad8: 6b9b ldr r3, [r3, #56] @ 0x38 8003ada: 881a ldrh r2, [r3, #0] 8003adc: 68fb ldr r3, [r7, #12] 8003ade: 681b ldr r3, [r3, #0] 8003ae0: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8003ae2: 68fb ldr r3, [r7, #12] 8003ae4: 6b9b ldr r3, [r3, #56] @ 0x38 8003ae6: 1c9a adds r2, r3, #2 8003ae8: 68fb ldr r3, [r7, #12] 8003aea: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8003aec: 68fb ldr r3, [r7, #12] 8003aee: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003af0: b29b uxth r3, r3 8003af2: 3b01 subs r3, #1 8003af4: b29a uxth r2, r3 8003af6: 68fb ldr r3, [r7, #12] 8003af8: 87da strh r2, [r3, #62] @ 0x3e } /* Transmit data in 16 Bit mode */ while (hspi->TxXferCount > 0U) 8003afa: e030 b.n 8003b5e { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8003afc: 68fb ldr r3, [r7, #12] 8003afe: 681b ldr r3, [r3, #0] 8003b00: 689b ldr r3, [r3, #8] 8003b02: 2202 movs r2, #2 8003b04: 4013 ands r3, r2 8003b06: 2b02 cmp r3, #2 8003b08: d112 bne.n 8003b30 { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8003b0a: 68fb ldr r3, [r7, #12] 8003b0c: 6b9b ldr r3, [r3, #56] @ 0x38 8003b0e: 881a ldrh r2, [r3, #0] 8003b10: 68fb ldr r3, [r7, #12] 8003b12: 681b ldr r3, [r3, #0] 8003b14: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8003b16: 68fb ldr r3, [r7, #12] 8003b18: 6b9b ldr r3, [r3, #56] @ 0x38 8003b1a: 1c9a adds r2, r3, #2 8003b1c: 68fb ldr r3, [r7, #12] 8003b1e: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8003b20: 68fb ldr r3, [r7, #12] 8003b22: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003b24: b29b uxth r3, r3 8003b26: 3b01 subs r3, #1 8003b28: b29a uxth r2, r3 8003b2a: 68fb ldr r3, [r7, #12] 8003b2c: 87da strh r2, [r3, #62] @ 0x3e 8003b2e: e016 b.n 8003b5e } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8003b30: f7fd fd9c bl 800166c 8003b34: 0002 movs r2, r0 8003b36: 69bb ldr r3, [r7, #24] 8003b38: 1ad3 subs r3, r2, r3 8003b3a: 683a ldr r2, [r7, #0] 8003b3c: 429a cmp r2, r3 8003b3e: d802 bhi.n 8003b46 8003b40: 683b ldr r3, [r7, #0] 8003b42: 3301 adds r3, #1 8003b44: d102 bne.n 8003b4c 8003b46: 683b ldr r3, [r7, #0] 8003b48: 2b00 cmp r3, #0 8003b4a: d108 bne.n 8003b5e { errorcode = HAL_TIMEOUT; 8003b4c: 231f movs r3, #31 8003b4e: 18fb adds r3, r7, r3 8003b50: 2203 movs r2, #3 8003b52: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 8003b54: 68fb ldr r3, [r7, #12] 8003b56: 225d movs r2, #93 @ 0x5d 8003b58: 2101 movs r1, #1 8003b5a: 5499 strb r1, [r3, r2] goto error; 8003b5c: e080 b.n 8003c60 while (hspi->TxXferCount > 0U) 8003b5e: 68fb ldr r3, [r7, #12] 8003b60: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003b62: b29b uxth r3, r3 8003b64: 2b00 cmp r3, #0 8003b66: d1c9 bne.n 8003afc 8003b68: e053 b.n 8003c12 } } /* Transmit data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8003b6a: 68fb ldr r3, [r7, #12] 8003b6c: 685b ldr r3, [r3, #4] 8003b6e: 2b00 cmp r3, #0 8003b70: d004 beq.n 8003b7c 8003b72: 2316 movs r3, #22 8003b74: 18fb adds r3, r7, r3 8003b76: 881b ldrh r3, [r3, #0] 8003b78: 2b01 cmp r3, #1 8003b7a: d145 bne.n 8003c08 { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 8003b7c: 68fb ldr r3, [r7, #12] 8003b7e: 6b9a ldr r2, [r3, #56] @ 0x38 8003b80: 68fb ldr r3, [r7, #12] 8003b82: 681b ldr r3, [r3, #0] 8003b84: 330c adds r3, #12 8003b86: 7812 ldrb r2, [r2, #0] 8003b88: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8003b8a: 68fb ldr r3, [r7, #12] 8003b8c: 6b9b ldr r3, [r3, #56] @ 0x38 8003b8e: 1c5a adds r2, r3, #1 8003b90: 68fb ldr r3, [r7, #12] 8003b92: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8003b94: 68fb ldr r3, [r7, #12] 8003b96: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003b98: b29b uxth r3, r3 8003b9a: 3b01 subs r3, #1 8003b9c: b29a uxth r2, r3 8003b9e: 68fb ldr r3, [r7, #12] 8003ba0: 87da strh r2, [r3, #62] @ 0x3e } while (hspi->TxXferCount > 0U) 8003ba2: e031 b.n 8003c08 { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) 8003ba4: 68fb ldr r3, [r7, #12] 8003ba6: 681b ldr r3, [r3, #0] 8003ba8: 689b ldr r3, [r3, #8] 8003baa: 2202 movs r2, #2 8003bac: 4013 ands r3, r2 8003bae: 2b02 cmp r3, #2 8003bb0: d113 bne.n 8003bda { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 8003bb2: 68fb ldr r3, [r7, #12] 8003bb4: 6b9a ldr r2, [r3, #56] @ 0x38 8003bb6: 68fb ldr r3, [r7, #12] 8003bb8: 681b ldr r3, [r3, #0] 8003bba: 330c adds r3, #12 8003bbc: 7812 ldrb r2, [r2, #0] 8003bbe: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 8003bc0: 68fb ldr r3, [r7, #12] 8003bc2: 6b9b ldr r3, [r3, #56] @ 0x38 8003bc4: 1c5a adds r2, r3, #1 8003bc6: 68fb ldr r3, [r7, #12] 8003bc8: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 8003bca: 68fb ldr r3, [r7, #12] 8003bcc: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003bce: b29b uxth r3, r3 8003bd0: 3b01 subs r3, #1 8003bd2: b29a uxth r2, r3 8003bd4: 68fb ldr r3, [r7, #12] 8003bd6: 87da strh r2, [r3, #62] @ 0x3e 8003bd8: e016 b.n 8003c08 } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8003bda: f7fd fd47 bl 800166c 8003bde: 0002 movs r2, r0 8003be0: 69bb ldr r3, [r7, #24] 8003be2: 1ad3 subs r3, r2, r3 8003be4: 683a ldr r2, [r7, #0] 8003be6: 429a cmp r2, r3 8003be8: d802 bhi.n 8003bf0 8003bea: 683b ldr r3, [r7, #0] 8003bec: 3301 adds r3, #1 8003bee: d102 bne.n 8003bf6 8003bf0: 683b ldr r3, [r7, #0] 8003bf2: 2b00 cmp r3, #0 8003bf4: d108 bne.n 8003c08 { errorcode = HAL_TIMEOUT; 8003bf6: 231f movs r3, #31 8003bf8: 18fb adds r3, r7, r3 8003bfa: 2203 movs r2, #3 8003bfc: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 8003bfe: 68fb ldr r3, [r7, #12] 8003c00: 225d movs r2, #93 @ 0x5d 8003c02: 2101 movs r1, #1 8003c04: 5499 strb r1, [r3, r2] goto error; 8003c06: e02b b.n 8003c60 while (hspi->TxXferCount > 0U) 8003c08: 68fb ldr r3, [r7, #12] 8003c0a: 8fdb ldrh r3, [r3, #62] @ 0x3e 8003c0c: b29b uxth r3, r3 8003c0e: 2b00 cmp r3, #0 8003c10: d1c8 bne.n 8003ba4 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 8003c12: 69ba ldr r2, [r7, #24] 8003c14: 6839 ldr r1, [r7, #0] 8003c16: 68fb ldr r3, [r7, #12] 8003c18: 0018 movs r0, r3 8003c1a: f000 fcef bl 80045fc 8003c1e: 1e03 subs r3, r0, #0 8003c20: d002 beq.n 8003c28 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8003c22: 68fb ldr r3, [r7, #12] 8003c24: 2220 movs r2, #32 8003c26: 661a str r2, [r3, #96] @ 0x60 } /* Clear overrun flag in 2 Lines communication mode because received is not read */ if (hspi->Init.Direction == SPI_DIRECTION_2LINES) 8003c28: 68fb ldr r3, [r7, #12] 8003c2a: 689b ldr r3, [r3, #8] 8003c2c: 2b00 cmp r3, #0 8003c2e: d10a bne.n 8003c46 { __HAL_SPI_CLEAR_OVRFLAG(hspi); 8003c30: 2300 movs r3, #0 8003c32: 613b str r3, [r7, #16] 8003c34: 68fb ldr r3, [r7, #12] 8003c36: 681b ldr r3, [r3, #0] 8003c38: 68db ldr r3, [r3, #12] 8003c3a: 613b str r3, [r7, #16] 8003c3c: 68fb ldr r3, [r7, #12] 8003c3e: 681b ldr r3, [r3, #0] 8003c40: 689b ldr r3, [r3, #8] 8003c42: 613b str r3, [r7, #16] 8003c44: 693b ldr r3, [r7, #16] } if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8003c46: 68fb ldr r3, [r7, #12] 8003c48: 6e1b ldr r3, [r3, #96] @ 0x60 8003c4a: 2b00 cmp r3, #0 8003c4c: d004 beq.n 8003c58 { errorcode = HAL_ERROR; 8003c4e: 231f movs r3, #31 8003c50: 18fb adds r3, r7, r3 8003c52: 2201 movs r2, #1 8003c54: 701a strb r2, [r3, #0] 8003c56: e003 b.n 8003c60 } else { hspi->State = HAL_SPI_STATE_READY; 8003c58: 68fb ldr r3, [r7, #12] 8003c5a: 225d movs r2, #93 @ 0x5d 8003c5c: 2101 movs r1, #1 8003c5e: 5499 strb r1, [r3, r2] } error: /* Process Unlocked */ __HAL_UNLOCK(hspi); 8003c60: 68fb ldr r3, [r7, #12] 8003c62: 225c movs r2, #92 @ 0x5c 8003c64: 2100 movs r1, #0 8003c66: 5499 strb r1, [r3, r2] return errorcode; 8003c68: 231f movs r3, #31 8003c6a: 18fb adds r3, r7, r3 8003c6c: 781b ldrb r3, [r3, #0] } 8003c6e: 0018 movs r0, r3 8003c70: 46bd mov sp, r7 8003c72: b008 add sp, #32 8003c74: bd80 pop {r7, pc} ... 08003c78 : * @param Size amount of data to be received * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8003c78: b590 push {r4, r7, lr} 8003c7a: b089 sub sp, #36 @ 0x24 8003c7c: af02 add r7, sp, #8 8003c7e: 60f8 str r0, [r7, #12] 8003c80: 60b9 str r1, [r7, #8] 8003c82: 603b str r3, [r7, #0] 8003c84: 1dbb adds r3, r7, #6 8003c86: 801a strh r2, [r3, #0] __IO uint32_t tmpreg = 0U; __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; 8003c88: 2117 movs r1, #23 8003c8a: 187b adds r3, r7, r1 8003c8c: 2200 movs r2, #0 8003c8e: 701a strb r2, [r3, #0] if (hspi->State != HAL_SPI_STATE_READY) 8003c90: 68fb ldr r3, [r7, #12] 8003c92: 225d movs r2, #93 @ 0x5d 8003c94: 5c9b ldrb r3, [r3, r2] 8003c96: b2db uxtb r3, r3 8003c98: 2b01 cmp r3, #1 8003c9a: d003 beq.n 8003ca4 { errorcode = HAL_BUSY; 8003c9c: 187b adds r3, r7, r1 8003c9e: 2202 movs r2, #2 8003ca0: 701a strb r2, [r3, #0] goto error; 8003ca2: e12b b.n 8003efc } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) 8003ca4: 68fb ldr r3, [r7, #12] 8003ca6: 685a ldr r2, [r3, #4] 8003ca8: 2382 movs r3, #130 @ 0x82 8003caa: 005b lsls r3, r3, #1 8003cac: 429a cmp r2, r3 8003cae: d113 bne.n 8003cd8 8003cb0: 68fb ldr r3, [r7, #12] 8003cb2: 689b ldr r3, [r3, #8] 8003cb4: 2b00 cmp r3, #0 8003cb6: d10f bne.n 8003cd8 { hspi->State = HAL_SPI_STATE_BUSY_RX; 8003cb8: 68fb ldr r3, [r7, #12] 8003cba: 225d movs r2, #93 @ 0x5d 8003cbc: 2104 movs r1, #4 8003cbe: 5499 strb r1, [r3, r2] /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); 8003cc0: 1dbb adds r3, r7, #6 8003cc2: 881c ldrh r4, [r3, #0] 8003cc4: 68ba ldr r2, [r7, #8] 8003cc6: 68b9 ldr r1, [r7, #8] 8003cc8: 68f8 ldr r0, [r7, #12] 8003cca: 683b ldr r3, [r7, #0] 8003ccc: 9300 str r3, [sp, #0] 8003cce: 0023 movs r3, r4 8003cd0: f000 f924 bl 8003f1c 8003cd4: 0003 movs r3, r0 8003cd6: e118 b.n 8003f0a } /* Process Locked */ __HAL_LOCK(hspi); 8003cd8: 68fb ldr r3, [r7, #12] 8003cda: 225c movs r2, #92 @ 0x5c 8003cdc: 5c9b ldrb r3, [r3, r2] 8003cde: 2b01 cmp r3, #1 8003ce0: d101 bne.n 8003ce6 8003ce2: 2302 movs r3, #2 8003ce4: e111 b.n 8003f0a 8003ce6: 68fb ldr r3, [r7, #12] 8003ce8: 225c movs r2, #92 @ 0x5c 8003cea: 2101 movs r1, #1 8003cec: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003cee: f7fd fcbd bl 800166c 8003cf2: 0003 movs r3, r0 8003cf4: 613b str r3, [r7, #16] if ((pData == NULL) || (Size == 0U)) 8003cf6: 68bb ldr r3, [r7, #8] 8003cf8: 2b00 cmp r3, #0 8003cfa: d003 beq.n 8003d04 8003cfc: 1dbb adds r3, r7, #6 8003cfe: 881b ldrh r3, [r3, #0] 8003d00: 2b00 cmp r3, #0 8003d02: d104 bne.n 8003d0e { errorcode = HAL_ERROR; 8003d04: 2317 movs r3, #23 8003d06: 18fb adds r3, r7, r3 8003d08: 2201 movs r2, #1 8003d0a: 701a strb r2, [r3, #0] goto error; 8003d0c: e0f6 b.n 8003efc } /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; 8003d0e: 68fb ldr r3, [r7, #12] 8003d10: 225d movs r2, #93 @ 0x5d 8003d12: 2104 movs r1, #4 8003d14: 5499 strb r1, [r3, r2] hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8003d16: 68fb ldr r3, [r7, #12] 8003d18: 2200 movs r2, #0 8003d1a: 661a str r2, [r3, #96] @ 0x60 hspi->pRxBuffPtr = (uint8_t *)pData; 8003d1c: 68fb ldr r3, [r7, #12] 8003d1e: 68ba ldr r2, [r7, #8] 8003d20: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferSize = Size; 8003d22: 68fb ldr r3, [r7, #12] 8003d24: 1dba adds r2, r7, #6 8003d26: 2144 movs r1, #68 @ 0x44 8003d28: 8812 ldrh r2, [r2, #0] 8003d2a: 525a strh r2, [r3, r1] hspi->RxXferCount = Size; 8003d2c: 68fb ldr r3, [r7, #12] 8003d2e: 1dba adds r2, r7, #6 8003d30: 2146 movs r1, #70 @ 0x46 8003d32: 8812 ldrh r2, [r2, #0] 8003d34: 525a strh r2, [r3, r1] /*Init field not used in handle to zero */ hspi->pTxBuffPtr = (uint8_t *)NULL; 8003d36: 68fb ldr r3, [r7, #12] 8003d38: 2200 movs r2, #0 8003d3a: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferSize = 0U; 8003d3c: 68fb ldr r3, [r7, #12] 8003d3e: 2200 movs r2, #0 8003d40: 879a strh r2, [r3, #60] @ 0x3c hspi->TxXferCount = 0U; 8003d42: 68fb ldr r3, [r7, #12] 8003d44: 2200 movs r2, #0 8003d46: 87da strh r2, [r3, #62] @ 0x3e hspi->RxISR = NULL; 8003d48: 68fb ldr r3, [r7, #12] 8003d4a: 2200 movs r2, #0 8003d4c: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 8003d4e: 68fb ldr r3, [r7, #12] 8003d50: 2200 movs r2, #0 8003d52: 651a str r2, [r3, #80] @ 0x50 hspi->RxXferCount--; } #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8003d54: 68fb ldr r3, [r7, #12] 8003d56: 68da ldr r2, [r3, #12] 8003d58: 23e0 movs r3, #224 @ 0xe0 8003d5a: 00db lsls r3, r3, #3 8003d5c: 429a cmp r2, r3 8003d5e: d908 bls.n 8003d72 { /* Set RX Fifo threshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8003d60: 68fb ldr r3, [r7, #12] 8003d62: 681b ldr r3, [r3, #0] 8003d64: 685a ldr r2, [r3, #4] 8003d66: 68fb ldr r3, [r7, #12] 8003d68: 681b ldr r3, [r3, #0] 8003d6a: 496a ldr r1, [pc, #424] @ (8003f14 ) 8003d6c: 400a ands r2, r1 8003d6e: 605a str r2, [r3, #4] 8003d70: e008 b.n 8003d84 } else { /* Set RX Fifo threshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8003d72: 68fb ldr r3, [r7, #12] 8003d74: 681b ldr r3, [r3, #0] 8003d76: 685a ldr r2, [r3, #4] 8003d78: 68fb ldr r3, [r7, #12] 8003d7a: 681b ldr r3, [r3, #0] 8003d7c: 2180 movs r1, #128 @ 0x80 8003d7e: 0149 lsls r1, r1, #5 8003d80: 430a orrs r2, r1 8003d82: 605a str r2, [r3, #4] } /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) 8003d84: 68fb ldr r3, [r7, #12] 8003d86: 689a ldr r2, [r3, #8] 8003d88: 2380 movs r3, #128 @ 0x80 8003d8a: 021b lsls r3, r3, #8 8003d8c: 429a cmp r2, r3 8003d8e: d10f bne.n 8003db0 { /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ __HAL_SPI_DISABLE(hspi); 8003d90: 68fb ldr r3, [r7, #12] 8003d92: 681b ldr r3, [r3, #0] 8003d94: 681a ldr r2, [r3, #0] 8003d96: 68fb ldr r3, [r7, #12] 8003d98: 681b ldr r3, [r3, #0] 8003d9a: 2140 movs r1, #64 @ 0x40 8003d9c: 438a bics r2, r1 8003d9e: 601a str r2, [r3, #0] SPI_1LINE_RX(hspi); 8003da0: 68fb ldr r3, [r7, #12] 8003da2: 681b ldr r3, [r3, #0] 8003da4: 681a ldr r2, [r3, #0] 8003da6: 68fb ldr r3, [r7, #12] 8003da8: 681b ldr r3, [r3, #0] 8003daa: 495b ldr r1, [pc, #364] @ (8003f18 ) 8003dac: 400a ands r2, r1 8003dae: 601a str r2, [r3, #0] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8003db0: 68fb ldr r3, [r7, #12] 8003db2: 681b ldr r3, [r3, #0] 8003db4: 681b ldr r3, [r3, #0] 8003db6: 2240 movs r2, #64 @ 0x40 8003db8: 4013 ands r3, r2 8003dba: 2b40 cmp r3, #64 @ 0x40 8003dbc: d007 beq.n 8003dce { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8003dbe: 68fb ldr r3, [r7, #12] 8003dc0: 681b ldr r3, [r3, #0] 8003dc2: 681a ldr r2, [r3, #0] 8003dc4: 68fb ldr r3, [r7, #12] 8003dc6: 681b ldr r3, [r3, #0] 8003dc8: 2140 movs r1, #64 @ 0x40 8003dca: 430a orrs r2, r1 8003dcc: 601a str r2, [r3, #0] } /* Receive data in 8 Bit mode */ if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) 8003dce: 68fb ldr r3, [r7, #12] 8003dd0: 68da ldr r2, [r3, #12] 8003dd2: 23e0 movs r3, #224 @ 0xe0 8003dd4: 00db lsls r3, r3, #3 8003dd6: 429a cmp r2, r3 8003dd8: d900 bls.n 8003ddc 8003dda: e071 b.n 8003ec0 { /* Transfer loop */ while (hspi->RxXferCount > 0U) 8003ddc: e035 b.n 8003e4a { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 8003dde: 68fb ldr r3, [r7, #12] 8003de0: 681b ldr r3, [r3, #0] 8003de2: 689b ldr r3, [r3, #8] 8003de4: 2201 movs r2, #1 8003de6: 4013 ands r3, r2 8003de8: 2b01 cmp r3, #1 8003dea: d117 bne.n 8003e1c { /* read the received data */ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 8003dec: 68fb ldr r3, [r7, #12] 8003dee: 681b ldr r3, [r3, #0] 8003df0: 330c adds r3, #12 8003df2: 001a movs r2, r3 8003df4: 68fb ldr r3, [r7, #12] 8003df6: 6c1b ldr r3, [r3, #64] @ 0x40 8003df8: 7812 ldrb r2, [r2, #0] 8003dfa: b2d2 uxtb r2, r2 8003dfc: 701a strb r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint8_t); 8003dfe: 68fb ldr r3, [r7, #12] 8003e00: 6c1b ldr r3, [r3, #64] @ 0x40 8003e02: 1c5a adds r2, r3, #1 8003e04: 68fb ldr r3, [r7, #12] 8003e06: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 8003e08: 68fb ldr r3, [r7, #12] 8003e0a: 2246 movs r2, #70 @ 0x46 8003e0c: 5a9b ldrh r3, [r3, r2] 8003e0e: b29b uxth r3, r3 8003e10: 3b01 subs r3, #1 8003e12: b299 uxth r1, r3 8003e14: 68fb ldr r3, [r7, #12] 8003e16: 2246 movs r2, #70 @ 0x46 8003e18: 5299 strh r1, [r3, r2] 8003e1a: e016 b.n 8003e4a } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8003e1c: f7fd fc26 bl 800166c 8003e20: 0002 movs r2, r0 8003e22: 693b ldr r3, [r7, #16] 8003e24: 1ad3 subs r3, r2, r3 8003e26: 683a ldr r2, [r7, #0] 8003e28: 429a cmp r2, r3 8003e2a: d802 bhi.n 8003e32 8003e2c: 683b ldr r3, [r7, #0] 8003e2e: 3301 adds r3, #1 8003e30: d102 bne.n 8003e38 8003e32: 683b ldr r3, [r7, #0] 8003e34: 2b00 cmp r3, #0 8003e36: d108 bne.n 8003e4a { errorcode = HAL_TIMEOUT; 8003e38: 2317 movs r3, #23 8003e3a: 18fb adds r3, r7, r3 8003e3c: 2203 movs r2, #3 8003e3e: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 8003e40: 68fb ldr r3, [r7, #12] 8003e42: 225d movs r2, #93 @ 0x5d 8003e44: 2101 movs r1, #1 8003e46: 5499 strb r1, [r3, r2] goto error; 8003e48: e058 b.n 8003efc while (hspi->RxXferCount > 0U) 8003e4a: 68fb ldr r3, [r7, #12] 8003e4c: 2246 movs r2, #70 @ 0x46 8003e4e: 5a9b ldrh r3, [r3, r2] 8003e50: b29b uxth r3, r3 8003e52: 2b00 cmp r3, #0 8003e54: d1c3 bne.n 8003dde 8003e56: e039 b.n 8003ecc { /* Transfer loop */ while (hspi->RxXferCount > 0U) { /* Check the RXNE flag */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) 8003e58: 68fb ldr r3, [r7, #12] 8003e5a: 681b ldr r3, [r3, #0] 8003e5c: 689b ldr r3, [r3, #8] 8003e5e: 2201 movs r2, #1 8003e60: 4013 ands r3, r2 8003e62: 2b01 cmp r3, #1 8003e64: d115 bne.n 8003e92 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 8003e66: 68fb ldr r3, [r7, #12] 8003e68: 681b ldr r3, [r3, #0] 8003e6a: 68da ldr r2, [r3, #12] 8003e6c: 68fb ldr r3, [r7, #12] 8003e6e: 6c1b ldr r3, [r3, #64] @ 0x40 8003e70: b292 uxth r2, r2 8003e72: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8003e74: 68fb ldr r3, [r7, #12] 8003e76: 6c1b ldr r3, [r3, #64] @ 0x40 8003e78: 1c9a adds r2, r3, #2 8003e7a: 68fb ldr r3, [r7, #12] 8003e7c: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 8003e7e: 68fb ldr r3, [r7, #12] 8003e80: 2246 movs r2, #70 @ 0x46 8003e82: 5a9b ldrh r3, [r3, r2] 8003e84: b29b uxth r3, r3 8003e86: 3b01 subs r3, #1 8003e88: b299 uxth r1, r3 8003e8a: 68fb ldr r3, [r7, #12] 8003e8c: 2246 movs r2, #70 @ 0x46 8003e8e: 5299 strh r1, [r3, r2] 8003e90: e016 b.n 8003ec0 } else { /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) 8003e92: f7fd fbeb bl 800166c 8003e96: 0002 movs r2, r0 8003e98: 693b ldr r3, [r7, #16] 8003e9a: 1ad3 subs r3, r2, r3 8003e9c: 683a ldr r2, [r7, #0] 8003e9e: 429a cmp r2, r3 8003ea0: d802 bhi.n 8003ea8 8003ea2: 683b ldr r3, [r7, #0] 8003ea4: 3301 adds r3, #1 8003ea6: d102 bne.n 8003eae 8003ea8: 683b ldr r3, [r7, #0] 8003eaa: 2b00 cmp r3, #0 8003eac: d108 bne.n 8003ec0 { errorcode = HAL_TIMEOUT; 8003eae: 2317 movs r3, #23 8003eb0: 18fb adds r3, r7, r3 8003eb2: 2203 movs r2, #3 8003eb4: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 8003eb6: 68fb ldr r3, [r7, #12] 8003eb8: 225d movs r2, #93 @ 0x5d 8003eba: 2101 movs r1, #1 8003ebc: 5499 strb r1, [r3, r2] goto error; 8003ebe: e01d b.n 8003efc while (hspi->RxXferCount > 0U) 8003ec0: 68fb ldr r3, [r7, #12] 8003ec2: 2246 movs r2, #70 @ 0x46 8003ec4: 5a9b ldrh r3, [r3, r2] 8003ec6: b29b uxth r3, r3 8003ec8: 2b00 cmp r3, #0 8003eca: d1c5 bne.n 8003e58 } } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) 8003ecc: 693a ldr r2, [r7, #16] 8003ece: 6839 ldr r1, [r7, #0] 8003ed0: 68fb ldr r3, [r7, #12] 8003ed2: 0018 movs r0, r3 8003ed4: f000 fb34 bl 8004540 8003ed8: 1e03 subs r3, r0, #0 8003eda: d002 beq.n 8003ee2 { hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 8003edc: 68fb ldr r3, [r7, #12] 8003ede: 2220 movs r2, #32 8003ee0: 661a str r2, [r3, #96] @ 0x60 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } #endif /* USE_SPI_CRC */ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 8003ee2: 68fb ldr r3, [r7, #12] 8003ee4: 6e1b ldr r3, [r3, #96] @ 0x60 8003ee6: 2b00 cmp r3, #0 8003ee8: d004 beq.n 8003ef4 { errorcode = HAL_ERROR; 8003eea: 2317 movs r3, #23 8003eec: 18fb adds r3, r7, r3 8003eee: 2201 movs r2, #1 8003ef0: 701a strb r2, [r3, #0] 8003ef2: e003 b.n 8003efc } else { hspi->State = HAL_SPI_STATE_READY; 8003ef4: 68fb ldr r3, [r7, #12] 8003ef6: 225d movs r2, #93 @ 0x5d 8003ef8: 2101 movs r1, #1 8003efa: 5499 strb r1, [r3, r2] } error : __HAL_UNLOCK(hspi); 8003efc: 68fb ldr r3, [r7, #12] 8003efe: 225c movs r2, #92 @ 0x5c 8003f00: 2100 movs r1, #0 8003f02: 5499 strb r1, [r3, r2] return errorcode; 8003f04: 2317 movs r3, #23 8003f06: 18fb adds r3, r7, r3 8003f08: 781b ldrb r3, [r3, #0] } 8003f0a: 0018 movs r0, r3 8003f0c: 46bd mov sp, r7 8003f0e: b007 add sp, #28 8003f10: bd90 pop {r4, r7, pc} 8003f12: 46c0 nop @ (mov r8, r8) 8003f14: ffffefff .word 0xffffefff 8003f18: ffffbfff .word 0xffffbfff 08003f1c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { 8003f1c: b580 push {r7, lr} 8003f1e: b08a sub sp, #40 @ 0x28 8003f20: af00 add r7, sp, #0 8003f22: 60f8 str r0, [r7, #12] 8003f24: 60b9 str r1, [r7, #8] 8003f26: 607a str r2, [r7, #4] 8003f28: 001a movs r2, r3 8003f2a: 1cbb adds r3, r7, #2 8003f2c: 801a strh r2, [r3, #0] __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; 8003f2e: 2301 movs r3, #1 8003f30: 627b str r3, [r7, #36] @ 0x24 HAL_StatusTypeDef errorcode = HAL_OK; 8003f32: 2323 movs r3, #35 @ 0x23 8003f34: 18fb adds r3, r7, r3 8003f36: 2200 movs r2, #0 8003f38: 701a strb r2, [r3, #0] /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Process Locked */ __HAL_LOCK(hspi); 8003f3a: 68fb ldr r3, [r7, #12] 8003f3c: 225c movs r2, #92 @ 0x5c 8003f3e: 5c9b ldrb r3, [r3, r2] 8003f40: 2b01 cmp r3, #1 8003f42: d101 bne.n 8003f48 8003f44: 2302 movs r3, #2 8003f46: e1c4 b.n 80042d2 8003f48: 68fb ldr r3, [r7, #12] 8003f4a: 225c movs r2, #92 @ 0x5c 8003f4c: 2101 movs r1, #1 8003f4e: 5499 strb r1, [r3, r2] /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); 8003f50: f7fd fb8c bl 800166c 8003f54: 0003 movs r3, r0 8003f56: 61fb str r3, [r7, #28] /* Init temporary variables */ tmp_state = hspi->State; 8003f58: 201b movs r0, #27 8003f5a: 183b adds r3, r7, r0 8003f5c: 68fa ldr r2, [r7, #12] 8003f5e: 215d movs r1, #93 @ 0x5d 8003f60: 5c52 ldrb r2, [r2, r1] 8003f62: 701a strb r2, [r3, #0] tmp_mode = hspi->Init.Mode; 8003f64: 68fb ldr r3, [r7, #12] 8003f66: 685b ldr r3, [r3, #4] 8003f68: 617b str r3, [r7, #20] initial_TxXferCount = Size; 8003f6a: 2312 movs r3, #18 8003f6c: 18fb adds r3, r7, r3 8003f6e: 1cba adds r2, r7, #2 8003f70: 8812 ldrh r2, [r2, #0] 8003f72: 801a strh r2, [r3, #0] #if (USE_SPI_CRC != 0U) spi_cr1 = READ_REG(hspi->Instance->CR1); spi_cr2 = READ_REG(hspi->Instance->CR2); #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ 8003f74: 183b adds r3, r7, r0 8003f76: 781b ldrb r3, [r3, #0] 8003f78: 2b01 cmp r3, #1 8003f7a: d011 beq.n 8003fa0 8003f7c: 697a ldr r2, [r7, #20] 8003f7e: 2382 movs r3, #130 @ 0x82 8003f80: 005b lsls r3, r3, #1 8003f82: 429a cmp r2, r3 8003f84: d107 bne.n 8003f96 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) 8003f86: 68fb ldr r3, [r7, #12] 8003f88: 689b ldr r3, [r3, #8] 8003f8a: 2b00 cmp r3, #0 8003f8c: d103 bne.n 8003f96 8003f8e: 183b adds r3, r7, r0 8003f90: 781b ldrb r3, [r3, #0] 8003f92: 2b04 cmp r3, #4 8003f94: d004 beq.n 8003fa0 { errorcode = HAL_BUSY; 8003f96: 2323 movs r3, #35 @ 0x23 8003f98: 18fb adds r3, r7, r3 8003f9a: 2202 movs r2, #2 8003f9c: 701a strb r2, [r3, #0] goto error; 8003f9e: e191 b.n 80042c4 } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) 8003fa0: 68bb ldr r3, [r7, #8] 8003fa2: 2b00 cmp r3, #0 8003fa4: d006 beq.n 8003fb4 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 2b00 cmp r3, #0 8003faa: d003 beq.n 8003fb4 8003fac: 1cbb adds r3, r7, #2 8003fae: 881b ldrh r3, [r3, #0] 8003fb0: 2b00 cmp r3, #0 8003fb2: d104 bne.n 8003fbe { errorcode = HAL_ERROR; 8003fb4: 2323 movs r3, #35 @ 0x23 8003fb6: 18fb adds r3, r7, r3 8003fb8: 2201 movs r2, #1 8003fba: 701a strb r2, [r3, #0] goto error; 8003fbc: e182 b.n 80042c4 } /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) 8003fbe: 68fb ldr r3, [r7, #12] 8003fc0: 225d movs r2, #93 @ 0x5d 8003fc2: 5c9b ldrb r3, [r3, r2] 8003fc4: b2db uxtb r3, r3 8003fc6: 2b04 cmp r3, #4 8003fc8: d003 beq.n 8003fd2 { hspi->State = HAL_SPI_STATE_BUSY_TX_RX; 8003fca: 68fb ldr r3, [r7, #12] 8003fcc: 225d movs r2, #93 @ 0x5d 8003fce: 2105 movs r1, #5 8003fd0: 5499 strb r1, [r3, r2] } /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 8003fd2: 68fb ldr r3, [r7, #12] 8003fd4: 2200 movs r2, #0 8003fd6: 661a str r2, [r3, #96] @ 0x60 hspi->pRxBuffPtr = (uint8_t *)pRxData; 8003fd8: 68fb ldr r3, [r7, #12] 8003fda: 687a ldr r2, [r7, #4] 8003fdc: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount = Size; 8003fde: 68fb ldr r3, [r7, #12] 8003fe0: 1cba adds r2, r7, #2 8003fe2: 2146 movs r1, #70 @ 0x46 8003fe4: 8812 ldrh r2, [r2, #0] 8003fe6: 525a strh r2, [r3, r1] hspi->RxXferSize = Size; 8003fe8: 68fb ldr r3, [r7, #12] 8003fea: 1cba adds r2, r7, #2 8003fec: 2144 movs r1, #68 @ 0x44 8003fee: 8812 ldrh r2, [r2, #0] 8003ff0: 525a strh r2, [r3, r1] hspi->pTxBuffPtr = (uint8_t *)pTxData; 8003ff2: 68fb ldr r3, [r7, #12] 8003ff4: 68ba ldr r2, [r7, #8] 8003ff6: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount = Size; 8003ff8: 68fb ldr r3, [r7, #12] 8003ffa: 1cba adds r2, r7, #2 8003ffc: 8812 ldrh r2, [r2, #0] 8003ffe: 87da strh r2, [r3, #62] @ 0x3e hspi->TxXferSize = Size; 8004000: 68fb ldr r3, [r7, #12] 8004002: 1cba adds r2, r7, #2 8004004: 8812 ldrh r2, [r2, #0] 8004006: 879a strh r2, [r3, #60] @ 0x3c /*Init field not used in handle to zero */ hspi->RxISR = NULL; 8004008: 68fb ldr r3, [r7, #12] 800400a: 2200 movs r2, #0 800400c: 64da str r2, [r3, #76] @ 0x4c hspi->TxISR = NULL; 800400e: 68fb ldr r3, [r7, #12] 8004010: 2200 movs r2, #0 8004012: 651a str r2, [r3, #80] @ 0x50 SPI_RESET_CRC(hspi); } #endif /* USE_SPI_CRC */ /* Set the Rx Fifo threshold */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8004014: 68fb ldr r3, [r7, #12] 8004016: 68da ldr r2, [r3, #12] 8004018: 23e0 movs r3, #224 @ 0xe0 800401a: 00db lsls r3, r3, #3 800401c: 429a cmp r2, r3 800401e: d908 bls.n 8004032 { /* Set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8004020: 68fb ldr r3, [r7, #12] 8004022: 681b ldr r3, [r3, #0] 8004024: 685a ldr r2, [r3, #4] 8004026: 68fb ldr r3, [r7, #12] 8004028: 681b ldr r3, [r3, #0] 800402a: 49ac ldr r1, [pc, #688] @ (80042dc ) 800402c: 400a ands r2, r1 800402e: 605a str r2, [r3, #4] 8004030: e008 b.n 8004044 } else { /* Set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); 8004032: 68fb ldr r3, [r7, #12] 8004034: 681b ldr r3, [r3, #0] 8004036: 685a ldr r2, [r3, #4] 8004038: 68fb ldr r3, [r7, #12] 800403a: 681b ldr r3, [r3, #0] 800403c: 2180 movs r1, #128 @ 0x80 800403e: 0149 lsls r1, r1, #5 8004040: 430a orrs r2, r1 8004042: 605a str r2, [r3, #4] } /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) 8004044: 68fb ldr r3, [r7, #12] 8004046: 681b ldr r3, [r3, #0] 8004048: 681b ldr r3, [r3, #0] 800404a: 2240 movs r2, #64 @ 0x40 800404c: 4013 ands r3, r2 800404e: 2b40 cmp r3, #64 @ 0x40 8004050: d007 beq.n 8004062 { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); 8004052: 68fb ldr r3, [r7, #12] 8004054: 681b ldr r3, [r3, #0] 8004056: 681a ldr r2, [r3, #0] 8004058: 68fb ldr r3, [r7, #12] 800405a: 681b ldr r3, [r3, #0] 800405c: 2140 movs r1, #64 @ 0x40 800405e: 430a orrs r2, r1 8004060: 601a str r2, [r3, #0] } /* Transmit and Receive data in 16 Bit mode */ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) 8004062: 68fb ldr r3, [r7, #12] 8004064: 68da ldr r2, [r3, #12] 8004066: 23e0 movs r3, #224 @ 0xe0 8004068: 00db lsls r3, r3, #3 800406a: 429a cmp r2, r3 800406c: d800 bhi.n 8004070 800406e: e083 b.n 8004178 { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004070: 68fb ldr r3, [r7, #12] 8004072: 685b ldr r3, [r3, #4] 8004074: 2b00 cmp r3, #0 8004076: d005 beq.n 8004084 8004078: 2312 movs r3, #18 800407a: 18fb adds r3, r7, r3 800407c: 881b ldrh r3, [r3, #0] 800407e: 2b01 cmp r3, #1 8004080: d000 beq.n 8004084 8004082: e06d b.n 8004160 { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 8004084: 68fb ldr r3, [r7, #12] 8004086: 6b9b ldr r3, [r3, #56] @ 0x38 8004088: 881a ldrh r2, [r3, #0] 800408a: 68fb ldr r3, [r7, #12] 800408c: 681b ldr r3, [r3, #0] 800408e: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 8004090: 68fb ldr r3, [r7, #12] 8004092: 6b9b ldr r3, [r3, #56] @ 0x38 8004094: 1c9a adds r2, r3, #2 8004096: 68fb ldr r3, [r7, #12] 8004098: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 800409a: 68fb ldr r3, [r7, #12] 800409c: 8fdb ldrh r3, [r3, #62] @ 0x3e 800409e: b29b uxth r3, r3 80040a0: 3b01 subs r3, #1 80040a2: b29a uxth r2, r3 80040a4: 68fb ldr r3, [r7, #12] 80040a6: 87da strh r2, [r3, #62] @ 0x3e SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 80040a8: e05a b.n 8004160 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 80040aa: 68fb ldr r3, [r7, #12] 80040ac: 681b ldr r3, [r3, #0] 80040ae: 689b ldr r3, [r3, #8] 80040b0: 2202 movs r2, #2 80040b2: 4013 ands r3, r2 80040b4: 2b02 cmp r3, #2 80040b6: d11b bne.n 80040f0 80040b8: 68fb ldr r3, [r7, #12] 80040ba: 8fdb ldrh r3, [r3, #62] @ 0x3e 80040bc: b29b uxth r3, r3 80040be: 2b00 cmp r3, #0 80040c0: d016 beq.n 80040f0 80040c2: 6a7b ldr r3, [r7, #36] @ 0x24 80040c4: 2b01 cmp r3, #1 80040c6: d113 bne.n 80040f0 { hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); 80040c8: 68fb ldr r3, [r7, #12] 80040ca: 6b9b ldr r3, [r3, #56] @ 0x38 80040cc: 881a ldrh r2, [r3, #0] 80040ce: 68fb ldr r3, [r7, #12] 80040d0: 681b ldr r3, [r3, #0] 80040d2: 60da str r2, [r3, #12] hspi->pTxBuffPtr += sizeof(uint16_t); 80040d4: 68fb ldr r3, [r7, #12] 80040d6: 6b9b ldr r3, [r3, #56] @ 0x38 80040d8: 1c9a adds r2, r3, #2 80040da: 68fb ldr r3, [r7, #12] 80040dc: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 80040de: 68fb ldr r3, [r7, #12] 80040e0: 8fdb ldrh r3, [r3, #62] @ 0x3e 80040e2: b29b uxth r3, r3 80040e4: 3b01 subs r3, #1 80040e6: b29a uxth r2, r3 80040e8: 68fb ldr r3, [r7, #12] 80040ea: 87da strh r2, [r3, #62] @ 0x3e /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 80040ec: 2300 movs r3, #0 80040ee: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Check RXNE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 80040f0: 68fb ldr r3, [r7, #12] 80040f2: 681b ldr r3, [r3, #0] 80040f4: 689b ldr r3, [r3, #8] 80040f6: 2201 movs r2, #1 80040f8: 4013 ands r3, r2 80040fa: 2b01 cmp r3, #1 80040fc: d11c bne.n 8004138 80040fe: 68fb ldr r3, [r7, #12] 8004100: 2246 movs r2, #70 @ 0x46 8004102: 5a9b ldrh r3, [r3, r2] 8004104: b29b uxth r3, r3 8004106: 2b00 cmp r3, #0 8004108: d016 beq.n 8004138 { *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; 800410a: 68fb ldr r3, [r7, #12] 800410c: 681b ldr r3, [r3, #0] 800410e: 68da ldr r2, [r3, #12] 8004110: 68fb ldr r3, [r7, #12] 8004112: 6c1b ldr r3, [r3, #64] @ 0x40 8004114: b292 uxth r2, r2 8004116: 801a strh r2, [r3, #0] hspi->pRxBuffPtr += sizeof(uint16_t); 8004118: 68fb ldr r3, [r7, #12] 800411a: 6c1b ldr r3, [r3, #64] @ 0x40 800411c: 1c9a adds r2, r3, #2 800411e: 68fb ldr r3, [r7, #12] 8004120: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 8004122: 68fb ldr r3, [r7, #12] 8004124: 2246 movs r2, #70 @ 0x46 8004126: 5a9b ldrh r3, [r3, r2] 8004128: b29b uxth r3, r3 800412a: 3b01 subs r3, #1 800412c: b299 uxth r1, r3 800412e: 68fb ldr r3, [r7, #12] 8004130: 2246 movs r2, #70 @ 0x46 8004132: 5299 strh r1, [r3, r2] /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 8004134: 2301 movs r3, #1 8004136: 627b str r3, [r7, #36] @ 0x24 } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) 8004138: f7fd fa98 bl 800166c 800413c: 0002 movs r2, r0 800413e: 69fb ldr r3, [r7, #28] 8004140: 1ad3 subs r3, r2, r3 8004142: 6b3a ldr r2, [r7, #48] @ 0x30 8004144: 429a cmp r2, r3 8004146: d80b bhi.n 8004160 8004148: 6b3b ldr r3, [r7, #48] @ 0x30 800414a: 3301 adds r3, #1 800414c: d008 beq.n 8004160 { errorcode = HAL_TIMEOUT; 800414e: 2323 movs r3, #35 @ 0x23 8004150: 18fb adds r3, r7, r3 8004152: 2203 movs r2, #3 8004154: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 8004156: 68fb ldr r3, [r7, #12] 8004158: 225d movs r2, #93 @ 0x5d 800415a: 2101 movs r1, #1 800415c: 5499 strb r1, [r3, r2] goto error; 800415e: e0b1 b.n 80042c4 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004160: 68fb ldr r3, [r7, #12] 8004162: 8fdb ldrh r3, [r3, #62] @ 0x3e 8004164: b29b uxth r3, r3 8004166: 2b00 cmp r3, #0 8004168: d19f bne.n 80040aa 800416a: 68fb ldr r3, [r7, #12] 800416c: 2246 movs r2, #70 @ 0x46 800416e: 5a9b ldrh r3, [r3, r2] 8004170: b29b uxth r3, r3 8004172: 2b00 cmp r3, #0 8004174: d199 bne.n 80040aa 8004176: e089 b.n 800428c } } /* Transmit and Receive data in 8 Bit mode */ else { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) 8004178: 68fb ldr r3, [r7, #12] 800417a: 685b ldr r3, [r3, #4] 800417c: 2b00 cmp r3, #0 800417e: d005 beq.n 800418c 8004180: 2312 movs r3, #18 8004182: 18fb adds r3, r7, r3 8004184: 881b ldrh r3, [r3, #0] 8004186: 2b01 cmp r3, #1 8004188: d000 beq.n 800418c 800418a: e074 b.n 8004276 { *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); 800418c: 68fb ldr r3, [r7, #12] 800418e: 6b9a ldr r2, [r3, #56] @ 0x38 8004190: 68fb ldr r3, [r7, #12] 8004192: 681b ldr r3, [r3, #0] 8004194: 330c adds r3, #12 8004196: 7812 ldrb r2, [r2, #0] 8004198: 701a strb r2, [r3, #0] hspi->pTxBuffPtr += sizeof(uint8_t); 800419a: 68fb ldr r3, [r7, #12] 800419c: 6b9b ldr r3, [r3, #56] @ 0x38 800419e: 1c5a adds r2, r3, #1 80041a0: 68fb ldr r3, [r7, #12] 80041a2: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 80041a4: 68fb ldr r3, [r7, #12] 80041a6: 8fdb ldrh r3, [r3, #62] @ 0x3e 80041a8: b29b uxth r3, r3 80041aa: 3b01 subs r3, #1 80041ac: b29a uxth r2, r3 80041ae: 68fb ldr r3, [r7, #12] 80041b0: 87da strh r2, [r3, #62] @ 0x3e } SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } #endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 80041b2: e060 b.n 8004276 { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) 80041b4: 68fb ldr r3, [r7, #12] 80041b6: 681b ldr r3, [r3, #0] 80041b8: 689b ldr r3, [r3, #8] 80041ba: 2202 movs r2, #2 80041bc: 4013 ands r3, r2 80041be: 2b02 cmp r3, #2 80041c0: d11c bne.n 80041fc 80041c2: 68fb ldr r3, [r7, #12] 80041c4: 8fdb ldrh r3, [r3, #62] @ 0x3e 80041c6: b29b uxth r3, r3 80041c8: 2b00 cmp r3, #0 80041ca: d017 beq.n 80041fc 80041cc: 6a7b ldr r3, [r7, #36] @ 0x24 80041ce: 2b01 cmp r3, #1 80041d0: d114 bne.n 80041fc { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); 80041d2: 68fb ldr r3, [r7, #12] 80041d4: 6b9a ldr r2, [r3, #56] @ 0x38 80041d6: 68fb ldr r3, [r7, #12] 80041d8: 681b ldr r3, [r3, #0] 80041da: 330c adds r3, #12 80041dc: 7812 ldrb r2, [r2, #0] 80041de: 701a strb r2, [r3, #0] hspi->pTxBuffPtr++; 80041e0: 68fb ldr r3, [r7, #12] 80041e2: 6b9b ldr r3, [r3, #56] @ 0x38 80041e4: 1c5a adds r2, r3, #1 80041e6: 68fb ldr r3, [r7, #12] 80041e8: 639a str r2, [r3, #56] @ 0x38 hspi->TxXferCount--; 80041ea: 68fb ldr r3, [r7, #12] 80041ec: 8fdb ldrh r3, [r3, #62] @ 0x3e 80041ee: b29b uxth r3, r3 80041f0: 3b01 subs r3, #1 80041f2: b29a uxth r2, r3 80041f4: 68fb ldr r3, [r7, #12] 80041f6: 87da strh r2, [r3, #62] @ 0x3e /* Next Data is a reception (Rx). Tx not allowed */ txallowed = 0U; 80041f8: 2300 movs r3, #0 80041fa: 627b str r3, [r7, #36] @ 0x24 } #endif /* USE_SPI_CRC */ } /* Wait until RXNE flag is reset */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) 80041fc: 68fb ldr r3, [r7, #12] 80041fe: 681b ldr r3, [r3, #0] 8004200: 689b ldr r3, [r3, #8] 8004202: 2201 movs r2, #1 8004204: 4013 ands r3, r2 8004206: 2b01 cmp r3, #1 8004208: d11e bne.n 8004248 800420a: 68fb ldr r3, [r7, #12] 800420c: 2246 movs r2, #70 @ 0x46 800420e: 5a9b ldrh r3, [r3, r2] 8004210: b29b uxth r3, r3 8004212: 2b00 cmp r3, #0 8004214: d018 beq.n 8004248 { (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; 8004216: 68fb ldr r3, [r7, #12] 8004218: 681b ldr r3, [r3, #0] 800421a: 330c adds r3, #12 800421c: 001a movs r2, r3 800421e: 68fb ldr r3, [r7, #12] 8004220: 6c1b ldr r3, [r3, #64] @ 0x40 8004222: 7812 ldrb r2, [r2, #0] 8004224: b2d2 uxtb r2, r2 8004226: 701a strb r2, [r3, #0] hspi->pRxBuffPtr++; 8004228: 68fb ldr r3, [r7, #12] 800422a: 6c1b ldr r3, [r3, #64] @ 0x40 800422c: 1c5a adds r2, r3, #1 800422e: 68fb ldr r3, [r7, #12] 8004230: 641a str r2, [r3, #64] @ 0x40 hspi->RxXferCount--; 8004232: 68fb ldr r3, [r7, #12] 8004234: 2246 movs r2, #70 @ 0x46 8004236: 5a9b ldrh r3, [r3, r2] 8004238: b29b uxth r3, r3 800423a: 3b01 subs r3, #1 800423c: b299 uxth r1, r3 800423e: 68fb ldr r3, [r7, #12] 8004240: 2246 movs r2, #70 @ 0x46 8004242: 5299 strh r1, [r3, r2] /* Next Data is a Transmission (Tx). Tx is allowed */ txallowed = 1U; 8004244: 2301 movs r3, #1 8004246: 627b str r3, [r7, #36] @ 0x24 } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) 8004248: f7fd fa10 bl 800166c 800424c: 0002 movs r2, r0 800424e: 69fb ldr r3, [r7, #28] 8004250: 1ad3 subs r3, r2, r3 8004252: 6b3a ldr r2, [r7, #48] @ 0x30 8004254: 429a cmp r2, r3 8004256: d802 bhi.n 800425e 8004258: 6b3b ldr r3, [r7, #48] @ 0x30 800425a: 3301 adds r3, #1 800425c: d102 bne.n 8004264 800425e: 6b3b ldr r3, [r7, #48] @ 0x30 8004260: 2b00 cmp r3, #0 8004262: d108 bne.n 8004276 { errorcode = HAL_TIMEOUT; 8004264: 2323 movs r3, #35 @ 0x23 8004266: 18fb adds r3, r7, r3 8004268: 2203 movs r2, #3 800426a: 701a strb r2, [r3, #0] hspi->State = HAL_SPI_STATE_READY; 800426c: 68fb ldr r3, [r7, #12] 800426e: 225d movs r2, #93 @ 0x5d 8004270: 2101 movs r1, #1 8004272: 5499 strb r1, [r3, r2] goto error; 8004274: e026 b.n 80042c4 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) 8004276: 68fb ldr r3, [r7, #12] 8004278: 8fdb ldrh r3, [r3, #62] @ 0x3e 800427a: b29b uxth r3, r3 800427c: 2b00 cmp r3, #0 800427e: d199 bne.n 80041b4 8004280: 68fb ldr r3, [r7, #12] 8004282: 2246 movs r2, #70 @ 0x46 8004284: 5a9b ldrh r3, [r3, r2] 8004286: b29b uxth r3, r3 8004288: 2b00 cmp r3, #0 800428a: d193 bne.n 80041b4 errorcode = HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) 800428c: 69fa ldr r2, [r7, #28] 800428e: 6b39 ldr r1, [r7, #48] @ 0x30 8004290: 68fb ldr r3, [r7, #12] 8004292: 0018 movs r0, r3 8004294: f000 f9b2 bl 80045fc 8004298: 1e03 subs r3, r0, #0 800429a: d006 beq.n 80042aa { errorcode = HAL_ERROR; 800429c: 2323 movs r3, #35 @ 0x23 800429e: 18fb adds r3, r7, r3 80042a0: 2201 movs r2, #1 80042a2: 701a strb r2, [r3, #0] hspi->ErrorCode = HAL_SPI_ERROR_FLAG; 80042a4: 68fb ldr r3, [r7, #12] 80042a6: 2220 movs r2, #32 80042a8: 661a str r2, [r3, #96] @ 0x60 } if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) 80042aa: 68fb ldr r3, [r7, #12] 80042ac: 6e1b ldr r3, [r3, #96] @ 0x60 80042ae: 2b00 cmp r3, #0 80042b0: d004 beq.n 80042bc { errorcode = HAL_ERROR; 80042b2: 2323 movs r3, #35 @ 0x23 80042b4: 18fb adds r3, r7, r3 80042b6: 2201 movs r2, #1 80042b8: 701a strb r2, [r3, #0] 80042ba: e003 b.n 80042c4 } else { hspi->State = HAL_SPI_STATE_READY; 80042bc: 68fb ldr r3, [r7, #12] 80042be: 225d movs r2, #93 @ 0x5d 80042c0: 2101 movs r1, #1 80042c2: 5499 strb r1, [r3, r2] } error : __HAL_UNLOCK(hspi); 80042c4: 68fb ldr r3, [r7, #12] 80042c6: 225c movs r2, #92 @ 0x5c 80042c8: 2100 movs r1, #0 80042ca: 5499 strb r1, [r3, r2] return errorcode; 80042cc: 2323 movs r3, #35 @ 0x23 80042ce: 18fb adds r3, r7, r3 80042d0: 781b ldrb r3, [r3, #0] } 80042d2: 0018 movs r0, r3 80042d4: 46bd mov sp, r7 80042d6: b00a add sp, #40 @ 0x28 80042d8: bd80 pop {r7, pc} 80042da: 46c0 nop @ (mov r8, r8) 80042dc: ffffefff .word 0xffffefff 080042e0 : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { 80042e0: b580 push {r7, lr} 80042e2: b088 sub sp, #32 80042e4: af00 add r7, sp, #0 80042e6: 60f8 str r0, [r7, #12] 80042e8: 60b9 str r1, [r7, #8] 80042ea: 603b str r3, [r7, #0] 80042ec: 1dfb adds r3, r7, #7 80042ee: 701a strb r2, [r3, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 80042f0: f7fd f9bc bl 800166c 80042f4: 0002 movs r2, r0 80042f6: 6abb ldr r3, [r7, #40] @ 0x28 80042f8: 1a9b subs r3, r3, r2 80042fa: 683a ldr r2, [r7, #0] 80042fc: 18d3 adds r3, r2, r3 80042fe: 61fb str r3, [r7, #28] tmp_tickstart = HAL_GetTick(); 8004300: f7fd f9b4 bl 800166c 8004304: 0003 movs r3, r0 8004306: 61bb str r3, [r7, #24] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); 8004308: 4b3a ldr r3, [pc, #232] @ (80043f4 ) 800430a: 681b ldr r3, [r3, #0] 800430c: 015b lsls r3, r3, #5 800430e: 0d1b lsrs r3, r3, #20 8004310: 69fa ldr r2, [r7, #28] 8004312: 4353 muls r3, r2 8004314: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 8004316: e058 b.n 80043ca { if (Timeout != HAL_MAX_DELAY) 8004318: 683b ldr r3, [r7, #0] 800431a: 3301 adds r3, #1 800431c: d055 beq.n 80043ca { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 800431e: f7fd f9a5 bl 800166c 8004322: 0002 movs r2, r0 8004324: 69bb ldr r3, [r7, #24] 8004326: 1ad3 subs r3, r2, r3 8004328: 69fa ldr r2, [r7, #28] 800432a: 429a cmp r2, r3 800432c: d902 bls.n 8004334 800432e: 69fb ldr r3, [r7, #28] 8004330: 2b00 cmp r3, #0 8004332: d142 bne.n 80043ba /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8004334: 68fb ldr r3, [r7, #12] 8004336: 681b ldr r3, [r3, #0] 8004338: 685a ldr r2, [r3, #4] 800433a: 68fb ldr r3, [r7, #12] 800433c: 681b ldr r3, [r3, #0] 800433e: 21e0 movs r1, #224 @ 0xe0 8004340: 438a bics r2, r1 8004342: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8004344: 68fb ldr r3, [r7, #12] 8004346: 685a ldr r2, [r3, #4] 8004348: 2382 movs r3, #130 @ 0x82 800434a: 005b lsls r3, r3, #1 800434c: 429a cmp r2, r3 800434e: d113 bne.n 8004378 8004350: 68fb ldr r3, [r7, #12] 8004352: 689a ldr r2, [r3, #8] 8004354: 2380 movs r3, #128 @ 0x80 8004356: 021b lsls r3, r3, #8 8004358: 429a cmp r2, r3 800435a: d005 beq.n 8004368 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 800435c: 68fb ldr r3, [r7, #12] 800435e: 689a ldr r2, [r3, #8] 8004360: 2380 movs r3, #128 @ 0x80 8004362: 00db lsls r3, r3, #3 8004364: 429a cmp r2, r3 8004366: d107 bne.n 8004378 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8004368: 68fb ldr r3, [r7, #12] 800436a: 681b ldr r3, [r3, #0] 800436c: 681a ldr r2, [r3, #0] 800436e: 68fb ldr r3, [r7, #12] 8004370: 681b ldr r3, [r3, #0] 8004372: 2140 movs r1, #64 @ 0x40 8004374: 438a bics r2, r1 8004376: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 8004378: 68fb ldr r3, [r7, #12] 800437a: 6a9a ldr r2, [r3, #40] @ 0x28 800437c: 2380 movs r3, #128 @ 0x80 800437e: 019b lsls r3, r3, #6 8004380: 429a cmp r2, r3 8004382: d110 bne.n 80043a6 { SPI_RESET_CRC(hspi); 8004384: 68fb ldr r3, [r7, #12] 8004386: 681b ldr r3, [r3, #0] 8004388: 681a ldr r2, [r3, #0] 800438a: 68fb ldr r3, [r7, #12] 800438c: 681b ldr r3, [r3, #0] 800438e: 491a ldr r1, [pc, #104] @ (80043f8 ) 8004390: 400a ands r2, r1 8004392: 601a str r2, [r3, #0] 8004394: 68fb ldr r3, [r7, #12] 8004396: 681b ldr r3, [r3, #0] 8004398: 681a ldr r2, [r3, #0] 800439a: 68fb ldr r3, [r7, #12] 800439c: 681b ldr r3, [r3, #0] 800439e: 2180 movs r1, #128 @ 0x80 80043a0: 0189 lsls r1, r1, #6 80043a2: 430a orrs r2, r1 80043a4: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 80043a6: 68fb ldr r3, [r7, #12] 80043a8: 225d movs r2, #93 @ 0x5d 80043aa: 2101 movs r1, #1 80043ac: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hspi); 80043ae: 68fb ldr r3, [r7, #12] 80043b0: 225c movs r2, #92 @ 0x5c 80043b2: 2100 movs r1, #0 80043b4: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 80043b6: 2303 movs r3, #3 80043b8: e017 b.n 80043ea } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 80043ba: 697b ldr r3, [r7, #20] 80043bc: 2b00 cmp r3, #0 80043be: d101 bne.n 80043c4 { tmp_timeout = 0U; 80043c0: 2300 movs r3, #0 80043c2: 61fb str r3, [r7, #28] } count--; 80043c4: 697b ldr r3, [r7, #20] 80043c6: 3b01 subs r3, #1 80043c8: 617b str r3, [r7, #20] while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) 80043ca: 68fb ldr r3, [r7, #12] 80043cc: 681b ldr r3, [r3, #0] 80043ce: 689b ldr r3, [r3, #8] 80043d0: 68ba ldr r2, [r7, #8] 80043d2: 4013 ands r3, r2 80043d4: 68ba ldr r2, [r7, #8] 80043d6: 1ad3 subs r3, r2, r3 80043d8: 425a negs r2, r3 80043da: 4153 adcs r3, r2 80043dc: b2db uxtb r3, r3 80043de: 001a movs r2, r3 80043e0: 1dfb adds r3, r7, #7 80043e2: 781b ldrb r3, [r3, #0] 80043e4: 429a cmp r2, r3 80043e6: d197 bne.n 8004318 } } return HAL_OK; 80043e8: 2300 movs r3, #0 } 80043ea: 0018 movs r0, r3 80043ec: 46bd mov sp, r7 80043ee: b008 add sp, #32 80043f0: bd80 pop {r7, pc} 80043f2: 46c0 nop @ (mov r8, r8) 80043f4: 20000000 .word 0x20000000 80043f8: ffffdfff .word 0xffffdfff 080043fc : * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { 80043fc: b580 push {r7, lr} 80043fe: b08a sub sp, #40 @ 0x28 8004400: af00 add r7, sp, #0 8004402: 60f8 str r0, [r7, #12] 8004404: 60b9 str r1, [r7, #8] 8004406: 607a str r2, [r7, #4] 8004408: 603b str r3, [r7, #0] __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; __IO uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; 800440a: 2317 movs r3, #23 800440c: 18fb adds r3, r7, r3 800440e: 2200 movs r2, #0 8004410: 701a strb r2, [r3, #0] /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); 8004412: f7fd f92b bl 800166c 8004416: 0002 movs r2, r0 8004418: 6b3b ldr r3, [r7, #48] @ 0x30 800441a: 1a9b subs r3, r3, r2 800441c: 683a ldr r2, [r7, #0] 800441e: 18d3 adds r3, r2, r3 8004420: 627b str r3, [r7, #36] @ 0x24 tmp_tickstart = HAL_GetTick(); 8004422: f7fd f923 bl 800166c 8004426: 0003 movs r3, r0 8004428: 623b str r3, [r7, #32] /* Initialize the 8bit temporary pointer */ ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; 800442a: 68fb ldr r3, [r7, #12] 800442c: 681b ldr r3, [r3, #0] 800442e: 330c adds r3, #12 8004430: 61fb str r3, [r7, #28] /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); 8004432: 4b41 ldr r3, [pc, #260] @ (8004538 ) 8004434: 681a ldr r2, [r3, #0] 8004436: 0013 movs r3, r2 8004438: 009b lsls r3, r3, #2 800443a: 189b adds r3, r3, r2 800443c: 00da lsls r2, r3, #3 800443e: 1ad3 subs r3, r2, r3 8004440: 0d1b lsrs r3, r3, #20 8004442: 6a7a ldr r2, [r7, #36] @ 0x24 8004444: 4353 muls r3, r2 8004446: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 8004448: e068 b.n 800451c { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) 800444a: 68ba ldr r2, [r7, #8] 800444c: 23c0 movs r3, #192 @ 0xc0 800444e: 00db lsls r3, r3, #3 8004450: 429a cmp r2, r3 8004452: d10a bne.n 800446a 8004454: 687b ldr r3, [r7, #4] 8004456: 2b00 cmp r3, #0 8004458: d107 bne.n 800446a { /* Flush Data Register by a blank read */ tmpreg8 = *ptmpreg8; 800445a: 69fb ldr r3, [r7, #28] 800445c: 781b ldrb r3, [r3, #0] 800445e: b2da uxtb r2, r3 8004460: 2117 movs r1, #23 8004462: 187b adds r3, r7, r1 8004464: 701a strb r2, [r3, #0] /* To avoid GCC warning */ UNUSED(tmpreg8); 8004466: 187b adds r3, r7, r1 8004468: 781b ldrb r3, [r3, #0] } if (Timeout != HAL_MAX_DELAY) 800446a: 683b ldr r3, [r7, #0] 800446c: 3301 adds r3, #1 800446e: d055 beq.n 800451c { if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) 8004470: f7fd f8fc bl 800166c 8004474: 0002 movs r2, r0 8004476: 6a3b ldr r3, [r7, #32] 8004478: 1ad3 subs r3, r2, r3 800447a: 6a7a ldr r2, [r7, #36] @ 0x24 800447c: 429a cmp r2, r3 800447e: d902 bls.n 8004486 8004480: 6a7b ldr r3, [r7, #36] @ 0x24 8004482: 2b00 cmp r3, #0 8004484: d142 bne.n 800450c /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); 8004486: 68fb ldr r3, [r7, #12] 8004488: 681b ldr r3, [r3, #0] 800448a: 685a ldr r2, [r3, #4] 800448c: 68fb ldr r3, [r7, #12] 800448e: 681b ldr r3, [r3, #0] 8004490: 21e0 movs r1, #224 @ 0xe0 8004492: 438a bics r2, r1 8004494: 605a str r2, [r3, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 8004496: 68fb ldr r3, [r7, #12] 8004498: 685a ldr r2, [r3, #4] 800449a: 2382 movs r3, #130 @ 0x82 800449c: 005b lsls r3, r3, #1 800449e: 429a cmp r2, r3 80044a0: d113 bne.n 80044ca 80044a2: 68fb ldr r3, [r7, #12] 80044a4: 689a ldr r2, [r3, #8] 80044a6: 2380 movs r3, #128 @ 0x80 80044a8: 021b lsls r3, r3, #8 80044aa: 429a cmp r2, r3 80044ac: d005 beq.n 80044ba || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 80044ae: 68fb ldr r3, [r7, #12] 80044b0: 689a ldr r2, [r3, #8] 80044b2: 2380 movs r3, #128 @ 0x80 80044b4: 00db lsls r3, r3, #3 80044b6: 429a cmp r2, r3 80044b8: d107 bne.n 80044ca { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 80044ba: 68fb ldr r3, [r7, #12] 80044bc: 681b ldr r3, [r3, #0] 80044be: 681a ldr r2, [r3, #0] 80044c0: 68fb ldr r3, [r7, #12] 80044c2: 681b ldr r3, [r3, #0] 80044c4: 2140 movs r1, #64 @ 0x40 80044c6: 438a bics r2, r1 80044c8: 601a str r2, [r3, #0] } /* Reset CRC Calculation */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) 80044ca: 68fb ldr r3, [r7, #12] 80044cc: 6a9a ldr r2, [r3, #40] @ 0x28 80044ce: 2380 movs r3, #128 @ 0x80 80044d0: 019b lsls r3, r3, #6 80044d2: 429a cmp r2, r3 80044d4: d110 bne.n 80044f8 { SPI_RESET_CRC(hspi); 80044d6: 68fb ldr r3, [r7, #12] 80044d8: 681b ldr r3, [r3, #0] 80044da: 681a ldr r2, [r3, #0] 80044dc: 68fb ldr r3, [r7, #12] 80044de: 681b ldr r3, [r3, #0] 80044e0: 4916 ldr r1, [pc, #88] @ (800453c ) 80044e2: 400a ands r2, r1 80044e4: 601a str r2, [r3, #0] 80044e6: 68fb ldr r3, [r7, #12] 80044e8: 681b ldr r3, [r3, #0] 80044ea: 681a ldr r2, [r3, #0] 80044ec: 68fb ldr r3, [r7, #12] 80044ee: 681b ldr r3, [r3, #0] 80044f0: 2180 movs r1, #128 @ 0x80 80044f2: 0189 lsls r1, r1, #6 80044f4: 430a orrs r2, r1 80044f6: 601a str r2, [r3, #0] } hspi->State = HAL_SPI_STATE_READY; 80044f8: 68fb ldr r3, [r7, #12] 80044fa: 225d movs r2, #93 @ 0x5d 80044fc: 2101 movs r1, #1 80044fe: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hspi); 8004500: 68fb ldr r3, [r7, #12] 8004502: 225c movs r2, #92 @ 0x5c 8004504: 2100 movs r1, #0 8004506: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 8004508: 2303 movs r3, #3 800450a: e010 b.n 800452e } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ if (count == 0U) 800450c: 69bb ldr r3, [r7, #24] 800450e: 2b00 cmp r3, #0 8004510: d101 bne.n 8004516 { tmp_timeout = 0U; 8004512: 2300 movs r3, #0 8004514: 627b str r3, [r7, #36] @ 0x24 } count--; 8004516: 69bb ldr r3, [r7, #24] 8004518: 3b01 subs r3, #1 800451a: 61bb str r3, [r7, #24] while ((hspi->Instance->SR & Fifo) != State) 800451c: 68fb ldr r3, [r7, #12] 800451e: 681b ldr r3, [r3, #0] 8004520: 689b ldr r3, [r3, #8] 8004522: 68ba ldr r2, [r7, #8] 8004524: 4013 ands r3, r2 8004526: 687a ldr r2, [r7, #4] 8004528: 429a cmp r2, r3 800452a: d18e bne.n 800444a } } return HAL_OK; 800452c: 2300 movs r3, #0 } 800452e: 0018 movs r0, r3 8004530: 46bd mov sp, r7 8004532: b00a add sp, #40 @ 0x28 8004534: bd80 pop {r7, pc} 8004536: 46c0 nop @ (mov r8, r8) 8004538: 20000000 .word 0x20000000 800453c: ffffdfff .word 0xffffdfff 08004540 : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 8004540: b580 push {r7, lr} 8004542: b086 sub sp, #24 8004544: af02 add r7, sp, #8 8004546: 60f8 str r0, [r7, #12] 8004548: 60b9 str r1, [r7, #8] 800454a: 607a str r2, [r7, #4] if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 800454c: 68fb ldr r3, [r7, #12] 800454e: 685a ldr r2, [r3, #4] 8004550: 2382 movs r3, #130 @ 0x82 8004552: 005b lsls r3, r3, #1 8004554: 429a cmp r2, r3 8004556: d113 bne.n 8004580 8004558: 68fb ldr r3, [r7, #12] 800455a: 689a ldr r2, [r3, #8] 800455c: 2380 movs r3, #128 @ 0x80 800455e: 021b lsls r3, r3, #8 8004560: 429a cmp r2, r3 8004562: d005 beq.n 8004570 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 8004564: 68fb ldr r3, [r7, #12] 8004566: 689a ldr r2, [r3, #8] 8004568: 2380 movs r3, #128 @ 0x80 800456a: 00db lsls r3, r3, #3 800456c: 429a cmp r2, r3 800456e: d107 bne.n 8004580 { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8004570: 68fb ldr r3, [r7, #12] 8004572: 681b ldr r3, [r3, #0] 8004574: 681a ldr r2, [r3, #0] 8004576: 68fb ldr r3, [r7, #12] 8004578: 681b ldr r3, [r3, #0] 800457a: 2140 movs r1, #64 @ 0x40 800457c: 438a bics r2, r1 800457e: 601a str r2, [r3, #0] } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 8004580: 68ba ldr r2, [r7, #8] 8004582: 68f8 ldr r0, [r7, #12] 8004584: 687b ldr r3, [r7, #4] 8004586: 9300 str r3, [sp, #0] 8004588: 0013 movs r3, r2 800458a: 2200 movs r2, #0 800458c: 2180 movs r1, #128 @ 0x80 800458e: f7ff fea7 bl 80042e0 8004592: 1e03 subs r3, r0, #0 8004594: d007 beq.n 80045a6 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8004596: 68fb ldr r3, [r7, #12] 8004598: 6e1b ldr r3, [r3, #96] @ 0x60 800459a: 2220 movs r2, #32 800459c: 431a orrs r2, r3 800459e: 68fb ldr r3, [r7, #12] 80045a0: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 80045a2: 2303 movs r3, #3 80045a4: e026 b.n 80045f4 } if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) 80045a6: 68fb ldr r3, [r7, #12] 80045a8: 685a ldr r2, [r3, #4] 80045aa: 2382 movs r3, #130 @ 0x82 80045ac: 005b lsls r3, r3, #1 80045ae: 429a cmp r2, r3 80045b0: d11f bne.n 80045f2 80045b2: 68fb ldr r3, [r7, #12] 80045b4: 689a ldr r2, [r3, #8] 80045b6: 2380 movs r3, #128 @ 0x80 80045b8: 021b lsls r3, r3, #8 80045ba: 429a cmp r2, r3 80045bc: d005 beq.n 80045ca || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) 80045be: 68fb ldr r3, [r7, #12] 80045c0: 689a ldr r2, [r3, #8] 80045c2: 2380 movs r3, #128 @ 0x80 80045c4: 00db lsls r3, r3, #3 80045c6: 429a cmp r2, r3 80045c8: d113 bne.n 80045f2 { /* Empty the FRLVL fifo */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 80045ca: 68ba ldr r2, [r7, #8] 80045cc: 23c0 movs r3, #192 @ 0xc0 80045ce: 00d9 lsls r1, r3, #3 80045d0: 68f8 ldr r0, [r7, #12] 80045d2: 687b ldr r3, [r7, #4] 80045d4: 9300 str r3, [sp, #0] 80045d6: 0013 movs r3, r2 80045d8: 2200 movs r2, #0 80045da: f7ff ff0f bl 80043fc 80045de: 1e03 subs r3, r0, #0 80045e0: d007 beq.n 80045f2 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 80045e2: 68fb ldr r3, [r7, #12] 80045e4: 6e1b ldr r3, [r3, #96] @ 0x60 80045e6: 2220 movs r2, #32 80045e8: 431a orrs r2, r3 80045ea: 68fb ldr r3, [r7, #12] 80045ec: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 80045ee: 2303 movs r3, #3 80045f0: e000 b.n 80045f4 } } return HAL_OK; 80045f2: 2300 movs r3, #0 } 80045f4: 0018 movs r0, r3 80045f6: 46bd mov sp, r7 80045f8: b004 add sp, #16 80045fa: bd80 pop {r7, pc} 080045fc : * @param Timeout Timeout duration * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { 80045fc: b580 push {r7, lr} 80045fe: b086 sub sp, #24 8004600: af02 add r7, sp, #8 8004602: 60f8 str r0, [r7, #12] 8004604: 60b9 str r1, [r7, #8] 8004606: 607a str r2, [r7, #4] /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 8004608: 68ba ldr r2, [r7, #8] 800460a: 23c0 movs r3, #192 @ 0xc0 800460c: 0159 lsls r1, r3, #5 800460e: 68f8 ldr r0, [r7, #12] 8004610: 687b ldr r3, [r7, #4] 8004612: 9300 str r3, [sp, #0] 8004614: 0013 movs r3, r2 8004616: 2200 movs r2, #0 8004618: f7ff fef0 bl 80043fc 800461c: 1e03 subs r3, r0, #0 800461e: d007 beq.n 8004630 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8004620: 68fb ldr r3, [r7, #12] 8004622: 6e1b ldr r3, [r3, #96] @ 0x60 8004624: 2220 movs r2, #32 8004626: 431a orrs r2, r3 8004628: 68fb ldr r3, [r7, #12] 800462a: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800462c: 2303 movs r3, #3 800462e: e027 b.n 8004680 } /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) 8004630: 68ba ldr r2, [r7, #8] 8004632: 68f8 ldr r0, [r7, #12] 8004634: 687b ldr r3, [r7, #4] 8004636: 9300 str r3, [sp, #0] 8004638: 0013 movs r3, r2 800463a: 2200 movs r2, #0 800463c: 2180 movs r1, #128 @ 0x80 800463e: f7ff fe4f bl 80042e0 8004642: 1e03 subs r3, r0, #0 8004644: d007 beq.n 8004656 { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 8004646: 68fb ldr r3, [r7, #12] 8004648: 6e1b ldr r3, [r3, #96] @ 0x60 800464a: 2220 movs r2, #32 800464c: 431a orrs r2, r3 800464e: 68fb ldr r3, [r7, #12] 8004650: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 8004652: 2303 movs r3, #3 8004654: e014 b.n 8004680 } /* Control if the RX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) 8004656: 68ba ldr r2, [r7, #8] 8004658: 23c0 movs r3, #192 @ 0xc0 800465a: 00d9 lsls r1, r3, #3 800465c: 68f8 ldr r0, [r7, #12] 800465e: 687b ldr r3, [r7, #4] 8004660: 9300 str r3, [sp, #0] 8004662: 0013 movs r3, r2 8004664: 2200 movs r2, #0 8004666: f7ff fec9 bl 80043fc 800466a: 1e03 subs r3, r0, #0 800466c: d007 beq.n 800467e { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); 800466e: 68fb ldr r3, [r7, #12] 8004670: 6e1b ldr r3, [r3, #96] @ 0x60 8004672: 2220 movs r2, #32 8004674: 431a orrs r2, r3 8004676: 68fb ldr r3, [r7, #12] 8004678: 661a str r2, [r3, #96] @ 0x60 return HAL_TIMEOUT; 800467a: 2303 movs r3, #3 800467c: e000 b.n 8004680 } return HAL_OK; 800467e: 2300 movs r3, #0 } 8004680: 0018 movs r0, r3 8004682: 46bd mov sp, r7 8004684: b004 add sp, #16 8004686: bd80 pop {r7, pc} 08004688 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004688: b580 push {r7, lr} 800468a: b082 sub sp, #8 800468c: af00 add r7, sp, #0 800468e: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8004690: 687b ldr r3, [r7, #4] 8004692: 2b00 cmp r3, #0 8004694: d101 bne.n 800469a { return HAL_ERROR; 8004696: 2301 movs r3, #1 8004698: e046 b.n 8004728 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800469a: 687b ldr r3, [r7, #4] 800469c: 2288 movs r2, #136 @ 0x88 800469e: 589b ldr r3, [r3, r2] 80046a0: 2b00 cmp r3, #0 80046a2: d107 bne.n 80046b4 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80046a4: 687b ldr r3, [r7, #4] 80046a6: 2284 movs r2, #132 @ 0x84 80046a8: 2100 movs r1, #0 80046aa: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80046ac: 687b ldr r3, [r7, #4] 80046ae: 0018 movs r0, r3 80046b0: f7fc fe02 bl 80012b8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80046b4: 687b ldr r3, [r7, #4] 80046b6: 2288 movs r2, #136 @ 0x88 80046b8: 2124 movs r1, #36 @ 0x24 80046ba: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); 80046bc: 687b ldr r3, [r7, #4] 80046be: 681b ldr r3, [r3, #0] 80046c0: 681a ldr r2, [r3, #0] 80046c2: 687b ldr r3, [r7, #4] 80046c4: 681b ldr r3, [r3, #0] 80046c6: 2101 movs r1, #1 80046c8: 438a bics r2, r1 80046ca: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80046cc: 687b ldr r3, [r7, #4] 80046ce: 6a9b ldr r3, [r3, #40] @ 0x28 80046d0: 2b00 cmp r3, #0 80046d2: d003 beq.n 80046dc { UART_AdvFeatureConfig(huart); 80046d4: 687b ldr r3, [r7, #4] 80046d6: 0018 movs r0, r3 80046d8: f000 fa74 bl 8004bc4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80046dc: 687b ldr r3, [r7, #4] 80046de: 0018 movs r0, r3 80046e0: f000 f8cc bl 800487c 80046e4: 0003 movs r3, r0 80046e6: 2b01 cmp r3, #1 80046e8: d101 bne.n 80046ee { return HAL_ERROR; 80046ea: 2301 movs r3, #1 80046ec: e01c b.n 8004728 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80046ee: 687b ldr r3, [r7, #4] 80046f0: 681b ldr r3, [r3, #0] 80046f2: 685a ldr r2, [r3, #4] 80046f4: 687b ldr r3, [r7, #4] 80046f6: 681b ldr r3, [r3, #0] 80046f8: 490d ldr r1, [pc, #52] @ (8004730 ) 80046fa: 400a ands r2, r1 80046fc: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80046fe: 687b ldr r3, [r7, #4] 8004700: 681b ldr r3, [r3, #0] 8004702: 689a ldr r2, [r3, #8] 8004704: 687b ldr r3, [r7, #4] 8004706: 681b ldr r3, [r3, #0] 8004708: 212a movs r1, #42 @ 0x2a 800470a: 438a bics r2, r1 800470c: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800470e: 687b ldr r3, [r7, #4] 8004710: 681b ldr r3, [r3, #0] 8004712: 681a ldr r2, [r3, #0] 8004714: 687b ldr r3, [r7, #4] 8004716: 681b ldr r3, [r3, #0] 8004718: 2101 movs r1, #1 800471a: 430a orrs r2, r1 800471c: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800471e: 687b ldr r3, [r7, #4] 8004720: 0018 movs r0, r3 8004722: f000 fb03 bl 8004d2c 8004726: 0003 movs r3, r0 } 8004728: 0018 movs r0, r3 800472a: 46bd mov sp, r7 800472c: b002 add sp, #8 800472e: bd80 pop {r7, pc} 8004730: ffffb7ff .word 0xffffb7ff 08004734 : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8004734: b580 push {r7, lr} 8004736: b08a sub sp, #40 @ 0x28 8004738: af02 add r7, sp, #8 800473a: 60f8 str r0, [r7, #12] 800473c: 60b9 str r1, [r7, #8] 800473e: 603b str r3, [r7, #0] 8004740: 1dbb adds r3, r7, #6 8004742: 801a strh r2, [r3, #0] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8004744: 68fb ldr r3, [r7, #12] 8004746: 2288 movs r2, #136 @ 0x88 8004748: 589b ldr r3, [r3, r2] 800474a: 2b20 cmp r3, #32 800474c: d000 beq.n 8004750 800474e: e090 b.n 8004872 { if ((pData == NULL) || (Size == 0U)) 8004750: 68bb ldr r3, [r7, #8] 8004752: 2b00 cmp r3, #0 8004754: d003 beq.n 800475e 8004756: 1dbb adds r3, r7, #6 8004758: 881b ldrh r3, [r3, #0] 800475a: 2b00 cmp r3, #0 800475c: d101 bne.n 8004762 { return HAL_ERROR; 800475e: 2301 movs r3, #1 8004760: e088 b.n 8004874 } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a u16 frontier, as data to be filled into TDR will be handled through a u16 cast. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8004762: 68fb ldr r3, [r7, #12] 8004764: 689a ldr r2, [r3, #8] 8004766: 2380 movs r3, #128 @ 0x80 8004768: 015b lsls r3, r3, #5 800476a: 429a cmp r2, r3 800476c: d109 bne.n 8004782 800476e: 68fb ldr r3, [r7, #12] 8004770: 691b ldr r3, [r3, #16] 8004772: 2b00 cmp r3, #0 8004774: d105 bne.n 8004782 { if ((((uint32_t)pData) & 1U) != 0U) 8004776: 68bb ldr r3, [r7, #8] 8004778: 2201 movs r2, #1 800477a: 4013 ands r3, r2 800477c: d001 beq.n 8004782 { return HAL_ERROR; 800477e: 2301 movs r3, #1 8004780: e078 b.n 8004874 } } huart->ErrorCode = HAL_UART_ERROR_NONE; 8004782: 68fb ldr r3, [r7, #12] 8004784: 2290 movs r2, #144 @ 0x90 8004786: 2100 movs r1, #0 8004788: 5099 str r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY_TX; 800478a: 68fb ldr r3, [r7, #12] 800478c: 2288 movs r2, #136 @ 0x88 800478e: 2121 movs r1, #33 @ 0x21 8004790: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8004792: f7fc ff6b bl 800166c 8004796: 0003 movs r3, r0 8004798: 617b str r3, [r7, #20] huart->TxXferSize = Size; 800479a: 68fb ldr r3, [r7, #12] 800479c: 1dba adds r2, r7, #6 800479e: 2154 movs r1, #84 @ 0x54 80047a0: 8812 ldrh r2, [r2, #0] 80047a2: 525a strh r2, [r3, r1] huart->TxXferCount = Size; 80047a4: 68fb ldr r3, [r7, #12] 80047a6: 1dba adds r2, r7, #6 80047a8: 2156 movs r1, #86 @ 0x56 80047aa: 8812 ldrh r2, [r2, #0] 80047ac: 525a strh r2, [r3, r1] /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80047ae: 68fb ldr r3, [r7, #12] 80047b0: 689a ldr r2, [r3, #8] 80047b2: 2380 movs r3, #128 @ 0x80 80047b4: 015b lsls r3, r3, #5 80047b6: 429a cmp r2, r3 80047b8: d108 bne.n 80047cc 80047ba: 68fb ldr r3, [r7, #12] 80047bc: 691b ldr r3, [r3, #16] 80047be: 2b00 cmp r3, #0 80047c0: d104 bne.n 80047cc { pdata8bits = NULL; 80047c2: 2300 movs r3, #0 80047c4: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 80047c6: 68bb ldr r3, [r7, #8] 80047c8: 61bb str r3, [r7, #24] 80047ca: e003 b.n 80047d4 } else { pdata8bits = pData; 80047cc: 68bb ldr r3, [r7, #8] 80047ce: 61fb str r3, [r7, #28] pdata16bits = NULL; 80047d0: 2300 movs r3, #0 80047d2: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 80047d4: e030 b.n 8004838 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80047d6: 697a ldr r2, [r7, #20] 80047d8: 68f8 ldr r0, [r7, #12] 80047da: 683b ldr r3, [r7, #0] 80047dc: 9300 str r3, [sp, #0] 80047de: 0013 movs r3, r2 80047e0: 2200 movs r2, #0 80047e2: 2180 movs r1, #128 @ 0x80 80047e4: f000 fb4c bl 8004e80 80047e8: 1e03 subs r3, r0, #0 80047ea: d005 beq.n 80047f8 { huart->gState = HAL_UART_STATE_READY; 80047ec: 68fb ldr r3, [r7, #12] 80047ee: 2288 movs r2, #136 @ 0x88 80047f0: 2120 movs r1, #32 80047f2: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 80047f4: 2303 movs r3, #3 80047f6: e03d b.n 8004874 } if (pdata8bits == NULL) 80047f8: 69fb ldr r3, [r7, #28] 80047fa: 2b00 cmp r3, #0 80047fc: d10b bne.n 8004816 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 80047fe: 69bb ldr r3, [r7, #24] 8004800: 881b ldrh r3, [r3, #0] 8004802: 001a movs r2, r3 8004804: 68fb ldr r3, [r7, #12] 8004806: 681b ldr r3, [r3, #0] 8004808: 05d2 lsls r2, r2, #23 800480a: 0dd2 lsrs r2, r2, #23 800480c: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 800480e: 69bb ldr r3, [r7, #24] 8004810: 3302 adds r3, #2 8004812: 61bb str r3, [r7, #24] 8004814: e007 b.n 8004826 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 8004816: 69fb ldr r3, [r7, #28] 8004818: 781a ldrb r2, [r3, #0] 800481a: 68fb ldr r3, [r7, #12] 800481c: 681b ldr r3, [r3, #0] 800481e: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 8004820: 69fb ldr r3, [r7, #28] 8004822: 3301 adds r3, #1 8004824: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8004826: 68fb ldr r3, [r7, #12] 8004828: 2256 movs r2, #86 @ 0x56 800482a: 5a9b ldrh r3, [r3, r2] 800482c: b29b uxth r3, r3 800482e: 3b01 subs r3, #1 8004830: b299 uxth r1, r3 8004832: 68fb ldr r3, [r7, #12] 8004834: 2256 movs r2, #86 @ 0x56 8004836: 5299 strh r1, [r3, r2] while (huart->TxXferCount > 0U) 8004838: 68fb ldr r3, [r7, #12] 800483a: 2256 movs r2, #86 @ 0x56 800483c: 5a9b ldrh r3, [r3, r2] 800483e: b29b uxth r3, r3 8004840: 2b00 cmp r3, #0 8004842: d1c8 bne.n 80047d6 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8004844: 697a ldr r2, [r7, #20] 8004846: 68f8 ldr r0, [r7, #12] 8004848: 683b ldr r3, [r7, #0] 800484a: 9300 str r3, [sp, #0] 800484c: 0013 movs r3, r2 800484e: 2200 movs r2, #0 8004850: 2140 movs r1, #64 @ 0x40 8004852: f000 fb15 bl 8004e80 8004856: 1e03 subs r3, r0, #0 8004858: d005 beq.n 8004866 { huart->gState = HAL_UART_STATE_READY; 800485a: 68fb ldr r3, [r7, #12] 800485c: 2288 movs r2, #136 @ 0x88 800485e: 2120 movs r1, #32 8004860: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 8004862: 2303 movs r3, #3 8004864: e006 b.n 8004874 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8004866: 68fb ldr r3, [r7, #12] 8004868: 2288 movs r2, #136 @ 0x88 800486a: 2120 movs r1, #32 800486c: 5099 str r1, [r3, r2] return HAL_OK; 800486e: 2300 movs r3, #0 8004870: e000 b.n 8004874 } else { return HAL_BUSY; 8004872: 2302 movs r3, #2 } } 8004874: 0018 movs r0, r3 8004876: 46bd mov sp, r7 8004878: b008 add sp, #32 800487a: bd80 pop {r7, pc} 0800487c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 800487c: b580 push {r7, lr} 800487e: b088 sub sp, #32 8004880: af00 add r7, sp, #0 8004882: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8004884: 231a movs r3, #26 8004886: 18fb adds r3, r7, r3 8004888: 2200 movs r2, #0 800488a: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800488c: 687b ldr r3, [r7, #4] 800488e: 689a ldr r2, [r3, #8] 8004890: 687b ldr r3, [r7, #4] 8004892: 691b ldr r3, [r3, #16] 8004894: 431a orrs r2, r3 8004896: 687b ldr r3, [r7, #4] 8004898: 695b ldr r3, [r3, #20] 800489a: 431a orrs r2, r3 800489c: 687b ldr r3, [r7, #4] 800489e: 69db ldr r3, [r3, #28] 80048a0: 4313 orrs r3, r2 80048a2: 61fb str r3, [r7, #28] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 80048a4: 687b ldr r3, [r7, #4] 80048a6: 681b ldr r3, [r3, #0] 80048a8: 681b ldr r3, [r3, #0] 80048aa: 4abc ldr r2, [pc, #752] @ (8004b9c ) 80048ac: 4013 ands r3, r2 80048ae: 0019 movs r1, r3 80048b0: 687b ldr r3, [r7, #4] 80048b2: 681b ldr r3, [r3, #0] 80048b4: 69fa ldr r2, [r7, #28] 80048b6: 430a orrs r2, r1 80048b8: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80048ba: 687b ldr r3, [r7, #4] 80048bc: 681b ldr r3, [r3, #0] 80048be: 685b ldr r3, [r3, #4] 80048c0: 4ab7 ldr r2, [pc, #732] @ (8004ba0 ) 80048c2: 4013 ands r3, r2 80048c4: 0019 movs r1, r3 80048c6: 687b ldr r3, [r7, #4] 80048c8: 68da ldr r2, [r3, #12] 80048ca: 687b ldr r3, [r7, #4] 80048cc: 681b ldr r3, [r3, #0] 80048ce: 430a orrs r2, r1 80048d0: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80048d2: 687b ldr r3, [r7, #4] 80048d4: 699b ldr r3, [r3, #24] 80048d6: 61fb str r3, [r7, #28] if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; 80048d8: 687b ldr r3, [r7, #4] 80048da: 6a1b ldr r3, [r3, #32] 80048dc: 69fa ldr r2, [r7, #28] 80048de: 4313 orrs r3, r2 80048e0: 61fb str r3, [r7, #28] } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 80048e2: 687b ldr r3, [r7, #4] 80048e4: 681b ldr r3, [r3, #0] 80048e6: 689b ldr r3, [r3, #8] 80048e8: 4aae ldr r2, [pc, #696] @ (8004ba4 ) 80048ea: 4013 ands r3, r2 80048ec: 0019 movs r1, r3 80048ee: 687b ldr r3, [r7, #4] 80048f0: 681b ldr r3, [r3, #0] 80048f2: 69fa ldr r2, [r7, #28] 80048f4: 430a orrs r2, r1 80048f6: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 80048f8: 687b ldr r3, [r7, #4] 80048fa: 681b ldr r3, [r3, #0] 80048fc: 6adb ldr r3, [r3, #44] @ 0x2c 80048fe: 220f movs r2, #15 8004900: 4393 bics r3, r2 8004902: 0019 movs r1, r3 8004904: 687b ldr r3, [r7, #4] 8004906: 6a5a ldr r2, [r3, #36] @ 0x24 8004908: 687b ldr r3, [r7, #4] 800490a: 681b ldr r3, [r3, #0] 800490c: 430a orrs r2, r1 800490e: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8004910: 687b ldr r3, [r7, #4] 8004912: 681b ldr r3, [r3, #0] 8004914: 4aa4 ldr r2, [pc, #656] @ (8004ba8 ) 8004916: 4293 cmp r3, r2 8004918: d127 bne.n 800496a 800491a: 4ba4 ldr r3, [pc, #656] @ (8004bac ) 800491c: 6d5b ldr r3, [r3, #84] @ 0x54 800491e: 2203 movs r2, #3 8004920: 4013 ands r3, r2 8004922: 2b03 cmp r3, #3 8004924: d017 beq.n 8004956 8004926: d81b bhi.n 8004960 8004928: 2b02 cmp r3, #2 800492a: d00a beq.n 8004942 800492c: d818 bhi.n 8004960 800492e: 2b00 cmp r3, #0 8004930: d002 beq.n 8004938 8004932: 2b01 cmp r3, #1 8004934: d00a beq.n 800494c 8004936: e013 b.n 8004960 8004938: 231b movs r3, #27 800493a: 18fb adds r3, r7, r3 800493c: 2200 movs r2, #0 800493e: 701a strb r2, [r3, #0] 8004940: e058 b.n 80049f4 8004942: 231b movs r3, #27 8004944: 18fb adds r3, r7, r3 8004946: 2202 movs r2, #2 8004948: 701a strb r2, [r3, #0] 800494a: e053 b.n 80049f4 800494c: 231b movs r3, #27 800494e: 18fb adds r3, r7, r3 8004950: 2204 movs r2, #4 8004952: 701a strb r2, [r3, #0] 8004954: e04e b.n 80049f4 8004956: 231b movs r3, #27 8004958: 18fb adds r3, r7, r3 800495a: 2208 movs r2, #8 800495c: 701a strb r2, [r3, #0] 800495e: e049 b.n 80049f4 8004960: 231b movs r3, #27 8004962: 18fb adds r3, r7, r3 8004964: 2210 movs r2, #16 8004966: 701a strb r2, [r3, #0] 8004968: e044 b.n 80049f4 800496a: 687b ldr r3, [r7, #4] 800496c: 681b ldr r3, [r3, #0] 800496e: 4a90 ldr r2, [pc, #576] @ (8004bb0 ) 8004970: 4293 cmp r3, r2 8004972: d127 bne.n 80049c4 8004974: 4b8d ldr r3, [pc, #564] @ (8004bac ) 8004976: 6d5b ldr r3, [r3, #84] @ 0x54 8004978: 220c movs r2, #12 800497a: 4013 ands r3, r2 800497c: 2b0c cmp r3, #12 800497e: d017 beq.n 80049b0 8004980: d81b bhi.n 80049ba 8004982: 2b08 cmp r3, #8 8004984: d00a beq.n 800499c 8004986: d818 bhi.n 80049ba 8004988: 2b00 cmp r3, #0 800498a: d002 beq.n 8004992 800498c: 2b04 cmp r3, #4 800498e: d00a beq.n 80049a6 8004990: e013 b.n 80049ba 8004992: 231b movs r3, #27 8004994: 18fb adds r3, r7, r3 8004996: 2200 movs r2, #0 8004998: 701a strb r2, [r3, #0] 800499a: e02b b.n 80049f4 800499c: 231b movs r3, #27 800499e: 18fb adds r3, r7, r3 80049a0: 2202 movs r2, #2 80049a2: 701a strb r2, [r3, #0] 80049a4: e026 b.n 80049f4 80049a6: 231b movs r3, #27 80049a8: 18fb adds r3, r7, r3 80049aa: 2204 movs r2, #4 80049ac: 701a strb r2, [r3, #0] 80049ae: e021 b.n 80049f4 80049b0: 231b movs r3, #27 80049b2: 18fb adds r3, r7, r3 80049b4: 2208 movs r2, #8 80049b6: 701a strb r2, [r3, #0] 80049b8: e01c b.n 80049f4 80049ba: 231b movs r3, #27 80049bc: 18fb adds r3, r7, r3 80049be: 2210 movs r2, #16 80049c0: 701a strb r2, [r3, #0] 80049c2: e017 b.n 80049f4 80049c4: 687b ldr r3, [r7, #4] 80049c6: 681b ldr r3, [r3, #0] 80049c8: 4a7a ldr r2, [pc, #488] @ (8004bb4 ) 80049ca: 4293 cmp r3, r2 80049cc: d104 bne.n 80049d8 80049ce: 231b movs r3, #27 80049d0: 18fb adds r3, r7, r3 80049d2: 2200 movs r2, #0 80049d4: 701a strb r2, [r3, #0] 80049d6: e00d b.n 80049f4 80049d8: 687b ldr r3, [r7, #4] 80049da: 681b ldr r3, [r3, #0] 80049dc: 4a76 ldr r2, [pc, #472] @ (8004bb8 ) 80049de: 4293 cmp r3, r2 80049e0: d104 bne.n 80049ec 80049e2: 231b movs r3, #27 80049e4: 18fb adds r3, r7, r3 80049e6: 2200 movs r2, #0 80049e8: 701a strb r2, [r3, #0] 80049ea: e003 b.n 80049f4 80049ec: 231b movs r3, #27 80049ee: 18fb adds r3, r7, r3 80049f0: 2210 movs r2, #16 80049f2: 701a strb r2, [r3, #0] } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80049f4: 687b ldr r3, [r7, #4] 80049f6: 69da ldr r2, [r3, #28] 80049f8: 2380 movs r3, #128 @ 0x80 80049fa: 021b lsls r3, r3, #8 80049fc: 429a cmp r2, r3 80049fe: d000 beq.n 8004a02 8004a00: e065 b.n 8004ace { switch (clocksource) 8004a02: 231b movs r3, #27 8004a04: 18fb adds r3, r7, r3 8004a06: 781b ldrb r3, [r3, #0] 8004a08: 2b08 cmp r3, #8 8004a0a: d015 beq.n 8004a38 8004a0c: dc18 bgt.n 8004a40 8004a0e: 2b04 cmp r3, #4 8004a10: d00d beq.n 8004a2e 8004a12: dc15 bgt.n 8004a40 8004a14: 2b00 cmp r3, #0 8004a16: d002 beq.n 8004a1e 8004a18: 2b02 cmp r3, #2 8004a1a: d005 beq.n 8004a28 8004a1c: e010 b.n 8004a40 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8004a1e: f7fe fdc9 bl 80035b4 8004a22: 0003 movs r3, r0 8004a24: 617b str r3, [r7, #20] break; 8004a26: e012 b.n 8004a4e case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8004a28: 4b64 ldr r3, [pc, #400] @ (8004bbc ) 8004a2a: 617b str r3, [r7, #20] break; 8004a2c: e00f b.n 8004a4e case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8004a2e: f7fe fd35 bl 800349c 8004a32: 0003 movs r3, r0 8004a34: 617b str r3, [r7, #20] break; 8004a36: e00a b.n 8004a4e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8004a38: 2380 movs r3, #128 @ 0x80 8004a3a: 021b lsls r3, r3, #8 8004a3c: 617b str r3, [r7, #20] break; 8004a3e: e006 b.n 8004a4e default: pclk = 0U; 8004a40: 2300 movs r3, #0 8004a42: 617b str r3, [r7, #20] ret = HAL_ERROR; 8004a44: 231a movs r3, #26 8004a46: 18fb adds r3, r7, r3 8004a48: 2201 movs r2, #1 8004a4a: 701a strb r2, [r3, #0] break; 8004a4c: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8004a4e: 697b ldr r3, [r7, #20] 8004a50: 2b00 cmp r3, #0 8004a52: d100 bne.n 8004a56 8004a54: e08d b.n 8004b72 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8004a56: 687b ldr r3, [r7, #4] 8004a58: 6a5a ldr r2, [r3, #36] @ 0x24 8004a5a: 4b59 ldr r3, [pc, #356] @ (8004bc0 ) 8004a5c: 0052 lsls r2, r2, #1 8004a5e: 5ad3 ldrh r3, [r2, r3] 8004a60: 0019 movs r1, r3 8004a62: 6978 ldr r0, [r7, #20] 8004a64: f7fb fb56 bl 8000114 <__udivsi3> 8004a68: 0003 movs r3, r0 8004a6a: 005a lsls r2, r3, #1 8004a6c: 687b ldr r3, [r7, #4] 8004a6e: 685b ldr r3, [r3, #4] 8004a70: 085b lsrs r3, r3, #1 8004a72: 18d2 adds r2, r2, r3 8004a74: 687b ldr r3, [r7, #4] 8004a76: 685b ldr r3, [r3, #4] 8004a78: 0019 movs r1, r3 8004a7a: 0010 movs r0, r2 8004a7c: f7fb fb4a bl 8000114 <__udivsi3> 8004a80: 0003 movs r3, r0 8004a82: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8004a84: 693b ldr r3, [r7, #16] 8004a86: 2b0f cmp r3, #15 8004a88: d91c bls.n 8004ac4 8004a8a: 693a ldr r2, [r7, #16] 8004a8c: 2380 movs r3, #128 @ 0x80 8004a8e: 025b lsls r3, r3, #9 8004a90: 429a cmp r2, r3 8004a92: d217 bcs.n 8004ac4 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8004a94: 693b ldr r3, [r7, #16] 8004a96: b29a uxth r2, r3 8004a98: 200e movs r0, #14 8004a9a: 183b adds r3, r7, r0 8004a9c: 210f movs r1, #15 8004a9e: 438a bics r2, r1 8004aa0: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8004aa2: 693b ldr r3, [r7, #16] 8004aa4: 085b lsrs r3, r3, #1 8004aa6: b29b uxth r3, r3 8004aa8: 2207 movs r2, #7 8004aaa: 4013 ands r3, r2 8004aac: b299 uxth r1, r3 8004aae: 183b adds r3, r7, r0 8004ab0: 183a adds r2, r7, r0 8004ab2: 8812 ldrh r2, [r2, #0] 8004ab4: 430a orrs r2, r1 8004ab6: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; 8004ab8: 687b ldr r3, [r7, #4] 8004aba: 681b ldr r3, [r3, #0] 8004abc: 183a adds r2, r7, r0 8004abe: 8812 ldrh r2, [r2, #0] 8004ac0: 60da str r2, [r3, #12] 8004ac2: e056 b.n 8004b72 } else { ret = HAL_ERROR; 8004ac4: 231a movs r3, #26 8004ac6: 18fb adds r3, r7, r3 8004ac8: 2201 movs r2, #1 8004aca: 701a strb r2, [r3, #0] 8004acc: e051 b.n 8004b72 } } } else { switch (clocksource) 8004ace: 231b movs r3, #27 8004ad0: 18fb adds r3, r7, r3 8004ad2: 781b ldrb r3, [r3, #0] 8004ad4: 2b08 cmp r3, #8 8004ad6: d015 beq.n 8004b04 8004ad8: dc18 bgt.n 8004b0c 8004ada: 2b04 cmp r3, #4 8004adc: d00d beq.n 8004afa 8004ade: dc15 bgt.n 8004b0c 8004ae0: 2b00 cmp r3, #0 8004ae2: d002 beq.n 8004aea 8004ae4: 2b02 cmp r3, #2 8004ae6: d005 beq.n 8004af4 8004ae8: e010 b.n 8004b0c { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8004aea: f7fe fd63 bl 80035b4 8004aee: 0003 movs r3, r0 8004af0: 617b str r3, [r7, #20] break; 8004af2: e012 b.n 8004b1a case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8004af4: 4b31 ldr r3, [pc, #196] @ (8004bbc ) 8004af6: 617b str r3, [r7, #20] break; 8004af8: e00f b.n 8004b1a case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8004afa: f7fe fccf bl 800349c 8004afe: 0003 movs r3, r0 8004b00: 617b str r3, [r7, #20] break; 8004b02: e00a b.n 8004b1a case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8004b04: 2380 movs r3, #128 @ 0x80 8004b06: 021b lsls r3, r3, #8 8004b08: 617b str r3, [r7, #20] break; 8004b0a: e006 b.n 8004b1a default: pclk = 0U; 8004b0c: 2300 movs r3, #0 8004b0e: 617b str r3, [r7, #20] ret = HAL_ERROR; 8004b10: 231a movs r3, #26 8004b12: 18fb adds r3, r7, r3 8004b14: 2201 movs r2, #1 8004b16: 701a strb r2, [r3, #0] break; 8004b18: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) 8004b1a: 697b ldr r3, [r7, #20] 8004b1c: 2b00 cmp r3, #0 8004b1e: d028 beq.n 8004b72 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8004b20: 687b ldr r3, [r7, #4] 8004b22: 6a5a ldr r2, [r3, #36] @ 0x24 8004b24: 4b26 ldr r3, [pc, #152] @ (8004bc0 ) 8004b26: 0052 lsls r2, r2, #1 8004b28: 5ad3 ldrh r3, [r2, r3] 8004b2a: 0019 movs r1, r3 8004b2c: 6978 ldr r0, [r7, #20] 8004b2e: f7fb faf1 bl 8000114 <__udivsi3> 8004b32: 0003 movs r3, r0 8004b34: 001a movs r2, r3 8004b36: 687b ldr r3, [r7, #4] 8004b38: 685b ldr r3, [r3, #4] 8004b3a: 085b lsrs r3, r3, #1 8004b3c: 18d2 adds r2, r2, r3 8004b3e: 687b ldr r3, [r7, #4] 8004b40: 685b ldr r3, [r3, #4] 8004b42: 0019 movs r1, r3 8004b44: 0010 movs r0, r2 8004b46: f7fb fae5 bl 8000114 <__udivsi3> 8004b4a: 0003 movs r3, r0 8004b4c: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8004b4e: 693b ldr r3, [r7, #16] 8004b50: 2b0f cmp r3, #15 8004b52: d90a bls.n 8004b6a 8004b54: 693a ldr r2, [r7, #16] 8004b56: 2380 movs r3, #128 @ 0x80 8004b58: 025b lsls r3, r3, #9 8004b5a: 429a cmp r2, r3 8004b5c: d205 bcs.n 8004b6a { huart->Instance->BRR = (uint16_t)usartdiv; 8004b5e: 693b ldr r3, [r7, #16] 8004b60: b29a uxth r2, r3 8004b62: 687b ldr r3, [r7, #4] 8004b64: 681b ldr r3, [r3, #0] 8004b66: 60da str r2, [r3, #12] 8004b68: e003 b.n 8004b72 } else { ret = HAL_ERROR; 8004b6a: 231a movs r3, #26 8004b6c: 18fb adds r3, r7, r3 8004b6e: 2201 movs r2, #1 8004b70: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8004b72: 687b ldr r3, [r7, #4] 8004b74: 226a movs r2, #106 @ 0x6a 8004b76: 2101 movs r1, #1 8004b78: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; 8004b7a: 687b ldr r3, [r7, #4] 8004b7c: 2268 movs r2, #104 @ 0x68 8004b7e: 2101 movs r1, #1 8004b80: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; 8004b82: 687b ldr r3, [r7, #4] 8004b84: 2200 movs r2, #0 8004b86: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8004b88: 687b ldr r3, [r7, #4] 8004b8a: 2200 movs r2, #0 8004b8c: 679a str r2, [r3, #120] @ 0x78 return ret; 8004b8e: 231a movs r3, #26 8004b90: 18fb adds r3, r7, r3 8004b92: 781b ldrb r3, [r3, #0] } 8004b94: 0018 movs r0, r3 8004b96: 46bd mov sp, r7 8004b98: b008 add sp, #32 8004b9a: bd80 pop {r7, pc} 8004b9c: cfff69f3 .word 0xcfff69f3 8004ba0: ffffcfff .word 0xffffcfff 8004ba4: 11fff4ff .word 0x11fff4ff 8004ba8: 40013800 .word 0x40013800 8004bac: 40021000 .word 0x40021000 8004bb0: 40004400 .word 0x40004400 8004bb4: 40004800 .word 0x40004800 8004bb8: 40004c00 .word 0x40004c00 8004bbc: 00f42400 .word 0x00f42400 8004bc0: 080062a0 .word 0x080062a0 08004bc4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8004bc4: b580 push {r7, lr} 8004bc6: b082 sub sp, #8 8004bc8: af00 add r7, sp, #0 8004bca: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8004bcc: 687b ldr r3, [r7, #4] 8004bce: 6a9b ldr r3, [r3, #40] @ 0x28 8004bd0: 2208 movs r2, #8 8004bd2: 4013 ands r3, r2 8004bd4: d00b beq.n 8004bee { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 681b ldr r3, [r3, #0] 8004bda: 685b ldr r3, [r3, #4] 8004bdc: 4a4a ldr r2, [pc, #296] @ (8004d08 ) 8004bde: 4013 ands r3, r2 8004be0: 0019 movs r1, r3 8004be2: 687b ldr r3, [r7, #4] 8004be4: 6b9a ldr r2, [r3, #56] @ 0x38 8004be6: 687b ldr r3, [r7, #4] 8004be8: 681b ldr r3, [r3, #0] 8004bea: 430a orrs r2, r1 8004bec: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8004bee: 687b ldr r3, [r7, #4] 8004bf0: 6a9b ldr r3, [r3, #40] @ 0x28 8004bf2: 2201 movs r2, #1 8004bf4: 4013 ands r3, r2 8004bf6: d00b beq.n 8004c10 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8004bf8: 687b ldr r3, [r7, #4] 8004bfa: 681b ldr r3, [r3, #0] 8004bfc: 685b ldr r3, [r3, #4] 8004bfe: 4a43 ldr r2, [pc, #268] @ (8004d0c ) 8004c00: 4013 ands r3, r2 8004c02: 0019 movs r1, r3 8004c04: 687b ldr r3, [r7, #4] 8004c06: 6ada ldr r2, [r3, #44] @ 0x2c 8004c08: 687b ldr r3, [r7, #4] 8004c0a: 681b ldr r3, [r3, #0] 8004c0c: 430a orrs r2, r1 8004c0e: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8004c10: 687b ldr r3, [r7, #4] 8004c12: 6a9b ldr r3, [r3, #40] @ 0x28 8004c14: 2202 movs r2, #2 8004c16: 4013 ands r3, r2 8004c18: d00b beq.n 8004c32 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8004c1a: 687b ldr r3, [r7, #4] 8004c1c: 681b ldr r3, [r3, #0] 8004c1e: 685b ldr r3, [r3, #4] 8004c20: 4a3b ldr r2, [pc, #236] @ (8004d10 ) 8004c22: 4013 ands r3, r2 8004c24: 0019 movs r1, r3 8004c26: 687b ldr r3, [r7, #4] 8004c28: 6b1a ldr r2, [r3, #48] @ 0x30 8004c2a: 687b ldr r3, [r7, #4] 8004c2c: 681b ldr r3, [r3, #0] 8004c2e: 430a orrs r2, r1 8004c30: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8004c32: 687b ldr r3, [r7, #4] 8004c34: 6a9b ldr r3, [r3, #40] @ 0x28 8004c36: 2204 movs r2, #4 8004c38: 4013 ands r3, r2 8004c3a: d00b beq.n 8004c54 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8004c3c: 687b ldr r3, [r7, #4] 8004c3e: 681b ldr r3, [r3, #0] 8004c40: 685b ldr r3, [r3, #4] 8004c42: 4a34 ldr r2, [pc, #208] @ (8004d14 ) 8004c44: 4013 ands r3, r2 8004c46: 0019 movs r1, r3 8004c48: 687b ldr r3, [r7, #4] 8004c4a: 6b5a ldr r2, [r3, #52] @ 0x34 8004c4c: 687b ldr r3, [r7, #4] 8004c4e: 681b ldr r3, [r3, #0] 8004c50: 430a orrs r2, r1 8004c52: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8004c54: 687b ldr r3, [r7, #4] 8004c56: 6a9b ldr r3, [r3, #40] @ 0x28 8004c58: 2210 movs r2, #16 8004c5a: 4013 ands r3, r2 8004c5c: d00b beq.n 8004c76 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8004c5e: 687b ldr r3, [r7, #4] 8004c60: 681b ldr r3, [r3, #0] 8004c62: 689b ldr r3, [r3, #8] 8004c64: 4a2c ldr r2, [pc, #176] @ (8004d18 ) 8004c66: 4013 ands r3, r2 8004c68: 0019 movs r1, r3 8004c6a: 687b ldr r3, [r7, #4] 8004c6c: 6bda ldr r2, [r3, #60] @ 0x3c 8004c6e: 687b ldr r3, [r7, #4] 8004c70: 681b ldr r3, [r3, #0] 8004c72: 430a orrs r2, r1 8004c74: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8004c76: 687b ldr r3, [r7, #4] 8004c78: 6a9b ldr r3, [r3, #40] @ 0x28 8004c7a: 2220 movs r2, #32 8004c7c: 4013 ands r3, r2 8004c7e: d00b beq.n 8004c98 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8004c80: 687b ldr r3, [r7, #4] 8004c82: 681b ldr r3, [r3, #0] 8004c84: 689b ldr r3, [r3, #8] 8004c86: 4a25 ldr r2, [pc, #148] @ (8004d1c ) 8004c88: 4013 ands r3, r2 8004c8a: 0019 movs r1, r3 8004c8c: 687b ldr r3, [r7, #4] 8004c8e: 6c1a ldr r2, [r3, #64] @ 0x40 8004c90: 687b ldr r3, [r7, #4] 8004c92: 681b ldr r3, [r3, #0] 8004c94: 430a orrs r2, r1 8004c96: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8004c98: 687b ldr r3, [r7, #4] 8004c9a: 6a9b ldr r3, [r3, #40] @ 0x28 8004c9c: 2240 movs r2, #64 @ 0x40 8004c9e: 4013 ands r3, r2 8004ca0: d01d beq.n 8004cde { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8004ca2: 687b ldr r3, [r7, #4] 8004ca4: 681b ldr r3, [r3, #0] 8004ca6: 685b ldr r3, [r3, #4] 8004ca8: 4a1d ldr r2, [pc, #116] @ (8004d20 ) 8004caa: 4013 ands r3, r2 8004cac: 0019 movs r1, r3 8004cae: 687b ldr r3, [r7, #4] 8004cb0: 6c5a ldr r2, [r3, #68] @ 0x44 8004cb2: 687b ldr r3, [r7, #4] 8004cb4: 681b ldr r3, [r3, #0] 8004cb6: 430a orrs r2, r1 8004cb8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8004cba: 687b ldr r3, [r7, #4] 8004cbc: 6c5a ldr r2, [r3, #68] @ 0x44 8004cbe: 2380 movs r3, #128 @ 0x80 8004cc0: 035b lsls r3, r3, #13 8004cc2: 429a cmp r2, r3 8004cc4: d10b bne.n 8004cde { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8004cc6: 687b ldr r3, [r7, #4] 8004cc8: 681b ldr r3, [r3, #0] 8004cca: 685b ldr r3, [r3, #4] 8004ccc: 4a15 ldr r2, [pc, #84] @ (8004d24 ) 8004cce: 4013 ands r3, r2 8004cd0: 0019 movs r1, r3 8004cd2: 687b ldr r3, [r7, #4] 8004cd4: 6c9a ldr r2, [r3, #72] @ 0x48 8004cd6: 687b ldr r3, [r7, #4] 8004cd8: 681b ldr r3, [r3, #0] 8004cda: 430a orrs r2, r1 8004cdc: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8004cde: 687b ldr r3, [r7, #4] 8004ce0: 6a9b ldr r3, [r3, #40] @ 0x28 8004ce2: 2280 movs r2, #128 @ 0x80 8004ce4: 4013 ands r3, r2 8004ce6: d00b beq.n 8004d00 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8004ce8: 687b ldr r3, [r7, #4] 8004cea: 681b ldr r3, [r3, #0] 8004cec: 685b ldr r3, [r3, #4] 8004cee: 4a0e ldr r2, [pc, #56] @ (8004d28 ) 8004cf0: 4013 ands r3, r2 8004cf2: 0019 movs r1, r3 8004cf4: 687b ldr r3, [r7, #4] 8004cf6: 6cda ldr r2, [r3, #76] @ 0x4c 8004cf8: 687b ldr r3, [r7, #4] 8004cfa: 681b ldr r3, [r3, #0] 8004cfc: 430a orrs r2, r1 8004cfe: 605a str r2, [r3, #4] } } 8004d00: 46c0 nop @ (mov r8, r8) 8004d02: 46bd mov sp, r7 8004d04: b002 add sp, #8 8004d06: bd80 pop {r7, pc} 8004d08: ffff7fff .word 0xffff7fff 8004d0c: fffdffff .word 0xfffdffff 8004d10: fffeffff .word 0xfffeffff 8004d14: fffbffff .word 0xfffbffff 8004d18: ffffefff .word 0xffffefff 8004d1c: ffffdfff .word 0xffffdfff 8004d20: ffefffff .word 0xffefffff 8004d24: ff9fffff .word 0xff9fffff 8004d28: fff7ffff .word 0xfff7ffff 08004d2c : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8004d2c: b580 push {r7, lr} 8004d2e: b092 sub sp, #72 @ 0x48 8004d30: af02 add r7, sp, #8 8004d32: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8004d34: 687b ldr r3, [r7, #4] 8004d36: 2290 movs r2, #144 @ 0x90 8004d38: 2100 movs r1, #0 8004d3a: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8004d3c: f7fc fc96 bl 800166c 8004d40: 0003 movs r3, r0 8004d42: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8004d44: 687b ldr r3, [r7, #4] 8004d46: 681b ldr r3, [r3, #0] 8004d48: 681b ldr r3, [r3, #0] 8004d4a: 2208 movs r2, #8 8004d4c: 4013 ands r3, r2 8004d4e: 2b08 cmp r3, #8 8004d50: d12d bne.n 8004dae { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8004d52: 6bfb ldr r3, [r7, #60] @ 0x3c 8004d54: 2280 movs r2, #128 @ 0x80 8004d56: 0391 lsls r1, r2, #14 8004d58: 6878 ldr r0, [r7, #4] 8004d5a: 4a47 ldr r2, [pc, #284] @ (8004e78 ) 8004d5c: 9200 str r2, [sp, #0] 8004d5e: 2200 movs r2, #0 8004d60: f000 f88e bl 8004e80 8004d64: 1e03 subs r3, r0, #0 8004d66: d022 beq.n 8004dae */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004d68: f3ef 8310 mrs r3, PRIMASK 8004d6c: 627b str r3, [r7, #36] @ 0x24 return(result); 8004d6e: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8004d70: 63bb str r3, [r7, #56] @ 0x38 8004d72: 2301 movs r3, #1 8004d74: 62bb str r3, [r7, #40] @ 0x28 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004d76: 6abb ldr r3, [r7, #40] @ 0x28 8004d78: f383 8810 msr PRIMASK, r3 } 8004d7c: 46c0 nop @ (mov r8, r8) 8004d7e: 687b ldr r3, [r7, #4] 8004d80: 681b ldr r3, [r3, #0] 8004d82: 681a ldr r2, [r3, #0] 8004d84: 687b ldr r3, [r7, #4] 8004d86: 681b ldr r3, [r3, #0] 8004d88: 2180 movs r1, #128 @ 0x80 8004d8a: 438a bics r2, r1 8004d8c: 601a str r2, [r3, #0] 8004d8e: 6bbb ldr r3, [r7, #56] @ 0x38 8004d90: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004d92: 6afb ldr r3, [r7, #44] @ 0x2c 8004d94: f383 8810 msr PRIMASK, r3 } 8004d98: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; 8004d9a: 687b ldr r3, [r7, #4] 8004d9c: 2288 movs r2, #136 @ 0x88 8004d9e: 2120 movs r1, #32 8004da0: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 8004da2: 687b ldr r3, [r7, #4] 8004da4: 2284 movs r2, #132 @ 0x84 8004da6: 2100 movs r1, #0 8004da8: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 8004daa: 2303 movs r3, #3 8004dac: e060 b.n 8004e70 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8004dae: 687b ldr r3, [r7, #4] 8004db0: 681b ldr r3, [r3, #0] 8004db2: 681b ldr r3, [r3, #0] 8004db4: 2204 movs r2, #4 8004db6: 4013 ands r3, r2 8004db8: 2b04 cmp r3, #4 8004dba: d146 bne.n 8004e4a { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8004dbc: 6bfb ldr r3, [r7, #60] @ 0x3c 8004dbe: 2280 movs r2, #128 @ 0x80 8004dc0: 03d1 lsls r1, r2, #15 8004dc2: 6878 ldr r0, [r7, #4] 8004dc4: 4a2c ldr r2, [pc, #176] @ (8004e78 ) 8004dc6: 9200 str r2, [sp, #0] 8004dc8: 2200 movs r2, #0 8004dca: f000 f859 bl 8004e80 8004dce: 1e03 subs r3, r0, #0 8004dd0: d03b beq.n 8004e4a __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004dd2: f3ef 8310 mrs r3, PRIMASK 8004dd6: 60fb str r3, [r7, #12] return(result); 8004dd8: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8004dda: 637b str r3, [r7, #52] @ 0x34 8004ddc: 2301 movs r3, #1 8004dde: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004de0: 693b ldr r3, [r7, #16] 8004de2: f383 8810 msr PRIMASK, r3 } 8004de6: 46c0 nop @ (mov r8, r8) 8004de8: 687b ldr r3, [r7, #4] 8004dea: 681b ldr r3, [r3, #0] 8004dec: 681a ldr r2, [r3, #0] 8004dee: 687b ldr r3, [r7, #4] 8004df0: 681b ldr r3, [r3, #0] 8004df2: 4922 ldr r1, [pc, #136] @ (8004e7c ) 8004df4: 400a ands r2, r1 8004df6: 601a str r2, [r3, #0] 8004df8: 6b7b ldr r3, [r7, #52] @ 0x34 8004dfa: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004dfc: 697b ldr r3, [r7, #20] 8004dfe: f383 8810 msr PRIMASK, r3 } 8004e02: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004e04: f3ef 8310 mrs r3, PRIMASK 8004e08: 61bb str r3, [r7, #24] return(result); 8004e0a: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8004e0c: 633b str r3, [r7, #48] @ 0x30 8004e0e: 2301 movs r3, #1 8004e10: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004e12: 69fb ldr r3, [r7, #28] 8004e14: f383 8810 msr PRIMASK, r3 } 8004e18: 46c0 nop @ (mov r8, r8) 8004e1a: 687b ldr r3, [r7, #4] 8004e1c: 681b ldr r3, [r3, #0] 8004e1e: 689a ldr r2, [r3, #8] 8004e20: 687b ldr r3, [r7, #4] 8004e22: 681b ldr r3, [r3, #0] 8004e24: 2101 movs r1, #1 8004e26: 438a bics r2, r1 8004e28: 609a str r2, [r3, #8] 8004e2a: 6b3b ldr r3, [r7, #48] @ 0x30 8004e2c: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004e2e: 6a3b ldr r3, [r7, #32] 8004e30: f383 8810 msr PRIMASK, r3 } 8004e34: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; 8004e36: 687b ldr r3, [r7, #4] 8004e38: 228c movs r2, #140 @ 0x8c 8004e3a: 2120 movs r1, #32 8004e3c: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 8004e3e: 687b ldr r3, [r7, #4] 8004e40: 2284 movs r2, #132 @ 0x84 8004e42: 2100 movs r1, #0 8004e44: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 8004e46: 2303 movs r3, #3 8004e48: e012 b.n 8004e70 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8004e4a: 687b ldr r3, [r7, #4] 8004e4c: 2288 movs r2, #136 @ 0x88 8004e4e: 2120 movs r1, #32 8004e50: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; 8004e52: 687b ldr r3, [r7, #4] 8004e54: 228c movs r2, #140 @ 0x8c 8004e56: 2120 movs r1, #32 8004e58: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8004e5a: 687b ldr r3, [r7, #4] 8004e5c: 2200 movs r2, #0 8004e5e: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8004e60: 687b ldr r3, [r7, #4] 8004e62: 2200 movs r2, #0 8004e64: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8004e66: 687b ldr r3, [r7, #4] 8004e68: 2284 movs r2, #132 @ 0x84 8004e6a: 2100 movs r1, #0 8004e6c: 5499 strb r1, [r3, r2] return HAL_OK; 8004e6e: 2300 movs r3, #0 } 8004e70: 0018 movs r0, r3 8004e72: 46bd mov sp, r7 8004e74: b010 add sp, #64 @ 0x40 8004e76: bd80 pop {r7, pc} 8004e78: 01ffffff .word 0x01ffffff 8004e7c: fffffedf .word 0xfffffedf 08004e80 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004e80: b580 push {r7, lr} 8004e82: b084 sub sp, #16 8004e84: af00 add r7, sp, #0 8004e86: 60f8 str r0, [r7, #12] 8004e88: 60b9 str r1, [r7, #8] 8004e8a: 603b str r3, [r7, #0] 8004e8c: 1dfb adds r3, r7, #7 8004e8e: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004e90: e051 b.n 8004f36 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004e92: 69bb ldr r3, [r7, #24] 8004e94: 3301 adds r3, #1 8004e96: d04e beq.n 8004f36 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8004e98: f7fc fbe8 bl 800166c 8004e9c: 0002 movs r2, r0 8004e9e: 683b ldr r3, [r7, #0] 8004ea0: 1ad3 subs r3, r2, r3 8004ea2: 69ba ldr r2, [r7, #24] 8004ea4: 429a cmp r2, r3 8004ea6: d302 bcc.n 8004eae 8004ea8: 69bb ldr r3, [r7, #24] 8004eaa: 2b00 cmp r3, #0 8004eac: d101 bne.n 8004eb2 { return HAL_TIMEOUT; 8004eae: 2303 movs r3, #3 8004eb0: e051 b.n 8004f56 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8004eb2: 68fb ldr r3, [r7, #12] 8004eb4: 681b ldr r3, [r3, #0] 8004eb6: 681b ldr r3, [r3, #0] 8004eb8: 2204 movs r2, #4 8004eba: 4013 ands r3, r2 8004ebc: d03b beq.n 8004f36 8004ebe: 68bb ldr r3, [r7, #8] 8004ec0: 2b80 cmp r3, #128 @ 0x80 8004ec2: d038 beq.n 8004f36 8004ec4: 68bb ldr r3, [r7, #8] 8004ec6: 2b40 cmp r3, #64 @ 0x40 8004ec8: d035 beq.n 8004f36 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8004eca: 68fb ldr r3, [r7, #12] 8004ecc: 681b ldr r3, [r3, #0] 8004ece: 69db ldr r3, [r3, #28] 8004ed0: 2208 movs r2, #8 8004ed2: 4013 ands r3, r2 8004ed4: 2b08 cmp r3, #8 8004ed6: d111 bne.n 8004efc { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8004ed8: 68fb ldr r3, [r7, #12] 8004eda: 681b ldr r3, [r3, #0] 8004edc: 2208 movs r2, #8 8004ede: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004ee0: 68fb ldr r3, [r7, #12] 8004ee2: 0018 movs r0, r3 8004ee4: f000 f83c bl 8004f60 huart->ErrorCode = HAL_UART_ERROR_ORE; 8004ee8: 68fb ldr r3, [r7, #12] 8004eea: 2290 movs r2, #144 @ 0x90 8004eec: 2108 movs r1, #8 8004eee: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004ef0: 68fb ldr r3, [r7, #12] 8004ef2: 2284 movs r2, #132 @ 0x84 8004ef4: 2100 movs r1, #0 8004ef6: 5499 strb r1, [r3, r2] return HAL_ERROR; 8004ef8: 2301 movs r3, #1 8004efa: e02c b.n 8004f56 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8004efc: 68fb ldr r3, [r7, #12] 8004efe: 681b ldr r3, [r3, #0] 8004f00: 69da ldr r2, [r3, #28] 8004f02: 2380 movs r3, #128 @ 0x80 8004f04: 011b lsls r3, r3, #4 8004f06: 401a ands r2, r3 8004f08: 2380 movs r3, #128 @ 0x80 8004f0a: 011b lsls r3, r3, #4 8004f0c: 429a cmp r2, r3 8004f0e: d112 bne.n 8004f36 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8004f10: 68fb ldr r3, [r7, #12] 8004f12: 681b ldr r3, [r3, #0] 8004f14: 2280 movs r2, #128 @ 0x80 8004f16: 0112 lsls r2, r2, #4 8004f18: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004f1a: 68fb ldr r3, [r7, #12] 8004f1c: 0018 movs r0, r3 8004f1e: f000 f81f bl 8004f60 huart->ErrorCode = HAL_UART_ERROR_RTO; 8004f22: 68fb ldr r3, [r7, #12] 8004f24: 2290 movs r2, #144 @ 0x90 8004f26: 2120 movs r1, #32 8004f28: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004f2a: 68fb ldr r3, [r7, #12] 8004f2c: 2284 movs r2, #132 @ 0x84 8004f2e: 2100 movs r1, #0 8004f30: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 8004f32: 2303 movs r3, #3 8004f34: e00f b.n 8004f56 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004f36: 68fb ldr r3, [r7, #12] 8004f38: 681b ldr r3, [r3, #0] 8004f3a: 69db ldr r3, [r3, #28] 8004f3c: 68ba ldr r2, [r7, #8] 8004f3e: 4013 ands r3, r2 8004f40: 68ba ldr r2, [r7, #8] 8004f42: 1ad3 subs r3, r2, r3 8004f44: 425a negs r2, r3 8004f46: 4153 adcs r3, r2 8004f48: b2db uxtb r3, r3 8004f4a: 001a movs r2, r3 8004f4c: 1dfb adds r3, r7, #7 8004f4e: 781b ldrb r3, [r3, #0] 8004f50: 429a cmp r2, r3 8004f52: d09e beq.n 8004e92 } } } } return HAL_OK; 8004f54: 2300 movs r3, #0 } 8004f56: 0018 movs r0, r3 8004f58: 46bd mov sp, r7 8004f5a: b004 add sp, #16 8004f5c: bd80 pop {r7, pc} ... 08004f60 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8004f60: b580 push {r7, lr} 8004f62: b08e sub sp, #56 @ 0x38 8004f64: af00 add r7, sp, #0 8004f66: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004f68: f3ef 8310 mrs r3, PRIMASK 8004f6c: 617b str r3, [r7, #20] return(result); 8004f6e: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8004f70: 637b str r3, [r7, #52] @ 0x34 8004f72: 2301 movs r3, #1 8004f74: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004f76: 69bb ldr r3, [r7, #24] 8004f78: f383 8810 msr PRIMASK, r3 } 8004f7c: 46c0 nop @ (mov r8, r8) 8004f7e: 687b ldr r3, [r7, #4] 8004f80: 681b ldr r3, [r3, #0] 8004f82: 681a ldr r2, [r3, #0] 8004f84: 687b ldr r3, [r7, #4] 8004f86: 681b ldr r3, [r3, #0] 8004f88: 4926 ldr r1, [pc, #152] @ (8005024 ) 8004f8a: 400a ands r2, r1 8004f8c: 601a str r2, [r3, #0] 8004f8e: 6b7b ldr r3, [r7, #52] @ 0x34 8004f90: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004f92: 69fb ldr r3, [r7, #28] 8004f94: f383 8810 msr PRIMASK, r3 } 8004f98: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004f9a: f3ef 8310 mrs r3, PRIMASK 8004f9e: 623b str r3, [r7, #32] return(result); 8004fa0: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8004fa2: 633b str r3, [r7, #48] @ 0x30 8004fa4: 2301 movs r3, #1 8004fa6: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004fa8: 6a7b ldr r3, [r7, #36] @ 0x24 8004faa: f383 8810 msr PRIMASK, r3 } 8004fae: 46c0 nop @ (mov r8, r8) 8004fb0: 687b ldr r3, [r7, #4] 8004fb2: 681b ldr r3, [r3, #0] 8004fb4: 689a ldr r2, [r3, #8] 8004fb6: 687b ldr r3, [r7, #4] 8004fb8: 681b ldr r3, [r3, #0] 8004fba: 491b ldr r1, [pc, #108] @ (8005028 ) 8004fbc: 400a ands r2, r1 8004fbe: 609a str r2, [r3, #8] 8004fc0: 6b3b ldr r3, [r7, #48] @ 0x30 8004fc2: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004fc4: 6abb ldr r3, [r7, #40] @ 0x28 8004fc6: f383 8810 msr PRIMASK, r3 } 8004fca: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004fcc: 687b ldr r3, [r7, #4] 8004fce: 6edb ldr r3, [r3, #108] @ 0x6c 8004fd0: 2b01 cmp r3, #1 8004fd2: d118 bne.n 8005006 __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004fd4: f3ef 8310 mrs r3, PRIMASK 8004fd8: 60bb str r3, [r7, #8] return(result); 8004fda: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004fdc: 62fb str r3, [r7, #44] @ 0x2c 8004fde: 2301 movs r3, #1 8004fe0: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004fe2: 68fb ldr r3, [r7, #12] 8004fe4: f383 8810 msr PRIMASK, r3 } 8004fe8: 46c0 nop @ (mov r8, r8) 8004fea: 687b ldr r3, [r7, #4] 8004fec: 681b ldr r3, [r3, #0] 8004fee: 681a ldr r2, [r3, #0] 8004ff0: 687b ldr r3, [r7, #4] 8004ff2: 681b ldr r3, [r3, #0] 8004ff4: 2110 movs r1, #16 8004ff6: 438a bics r2, r1 8004ff8: 601a str r2, [r3, #0] 8004ffa: 6afb ldr r3, [r7, #44] @ 0x2c 8004ffc: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004ffe: 693b ldr r3, [r7, #16] 8005000: f383 8810 msr PRIMASK, r3 } 8005004: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8005006: 687b ldr r3, [r7, #4] 8005008: 228c movs r2, #140 @ 0x8c 800500a: 2120 movs r1, #32 800500c: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800500e: 687b ldr r3, [r7, #4] 8005010: 2200 movs r2, #0 8005012: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8005014: 687b ldr r3, [r7, #4] 8005016: 2200 movs r2, #0 8005018: 675a str r2, [r3, #116] @ 0x74 } 800501a: 46c0 nop @ (mov r8, r8) 800501c: 46bd mov sp, r7 800501e: b00e add sp, #56 @ 0x38 8005020: bd80 pop {r7, pc} 8005022: 46c0 nop @ (mov r8, r8) 8005024: fffffedf .word 0xfffffedf 8005028: effffffe .word 0xeffffffe 0800502c : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800502c: b580 push {r7, lr} 800502e: b084 sub sp, #16 8005030: af00 add r7, sp, #0 8005032: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8005034: 687b ldr r3, [r7, #4] 8005036: 2284 movs r2, #132 @ 0x84 8005038: 5c9b ldrb r3, [r3, r2] 800503a: 2b01 cmp r3, #1 800503c: d101 bne.n 8005042 800503e: 2302 movs r3, #2 8005040: e027 b.n 8005092 8005042: 687b ldr r3, [r7, #4] 8005044: 2284 movs r2, #132 @ 0x84 8005046: 2101 movs r1, #1 8005048: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 800504a: 687b ldr r3, [r7, #4] 800504c: 2288 movs r2, #136 @ 0x88 800504e: 2124 movs r1, #36 @ 0x24 8005050: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8005052: 687b ldr r3, [r7, #4] 8005054: 681b ldr r3, [r3, #0] 8005056: 681b ldr r3, [r3, #0] 8005058: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800505a: 687b ldr r3, [r7, #4] 800505c: 681b ldr r3, [r3, #0] 800505e: 681a ldr r2, [r3, #0] 8005060: 687b ldr r3, [r7, #4] 8005062: 681b ldr r3, [r3, #0] 8005064: 2101 movs r1, #1 8005066: 438a bics r2, r1 8005068: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800506a: 68fb ldr r3, [r7, #12] 800506c: 4a0b ldr r2, [pc, #44] @ (800509c ) 800506e: 4013 ands r3, r2 8005070: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8005072: 687b ldr r3, [r7, #4] 8005074: 2200 movs r2, #0 8005076: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8005078: 687b ldr r3, [r7, #4] 800507a: 681b ldr r3, [r3, #0] 800507c: 68fa ldr r2, [r7, #12] 800507e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8005080: 687b ldr r3, [r7, #4] 8005082: 2288 movs r2, #136 @ 0x88 8005084: 2120 movs r1, #32 8005086: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8005088: 687b ldr r3, [r7, #4] 800508a: 2284 movs r2, #132 @ 0x84 800508c: 2100 movs r1, #0 800508e: 5499 strb r1, [r3, r2] return HAL_OK; 8005090: 2300 movs r3, #0 } 8005092: 0018 movs r0, r3 8005094: 46bd mov sp, r7 8005096: b004 add sp, #16 8005098: bd80 pop {r7, pc} 800509a: 46c0 nop @ (mov r8, r8) 800509c: dfffffff .word 0xdfffffff 080050a0 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80050a0: b580 push {r7, lr} 80050a2: b084 sub sp, #16 80050a4: af00 add r7, sp, #0 80050a6: 6078 str r0, [r7, #4] 80050a8: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80050aa: 687b ldr r3, [r7, #4] 80050ac: 2284 movs r2, #132 @ 0x84 80050ae: 5c9b ldrb r3, [r3, r2] 80050b0: 2b01 cmp r3, #1 80050b2: d101 bne.n 80050b8 80050b4: 2302 movs r3, #2 80050b6: e02e b.n 8005116 80050b8: 687b ldr r3, [r7, #4] 80050ba: 2284 movs r2, #132 @ 0x84 80050bc: 2101 movs r1, #1 80050be: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 80050c0: 687b ldr r3, [r7, #4] 80050c2: 2288 movs r2, #136 @ 0x88 80050c4: 2124 movs r1, #36 @ 0x24 80050c6: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80050c8: 687b ldr r3, [r7, #4] 80050ca: 681b ldr r3, [r3, #0] 80050cc: 681b ldr r3, [r3, #0] 80050ce: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80050d0: 687b ldr r3, [r7, #4] 80050d2: 681b ldr r3, [r3, #0] 80050d4: 681a ldr r2, [r3, #0] 80050d6: 687b ldr r3, [r7, #4] 80050d8: 681b ldr r3, [r3, #0] 80050da: 2101 movs r1, #1 80050dc: 438a bics r2, r1 80050de: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 80050e0: 687b ldr r3, [r7, #4] 80050e2: 681b ldr r3, [r3, #0] 80050e4: 689b ldr r3, [r3, #8] 80050e6: 00db lsls r3, r3, #3 80050e8: 08d9 lsrs r1, r3, #3 80050ea: 687b ldr r3, [r7, #4] 80050ec: 681b ldr r3, [r3, #0] 80050ee: 683a ldr r2, [r7, #0] 80050f0: 430a orrs r2, r1 80050f2: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80050f4: 687b ldr r3, [r7, #4] 80050f6: 0018 movs r0, r3 80050f8: f000 f854 bl 80051a4 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80050fc: 687b ldr r3, [r7, #4] 80050fe: 681b ldr r3, [r3, #0] 8005100: 68fa ldr r2, [r7, #12] 8005102: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8005104: 687b ldr r3, [r7, #4] 8005106: 2288 movs r2, #136 @ 0x88 8005108: 2120 movs r1, #32 800510a: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 800510c: 687b ldr r3, [r7, #4] 800510e: 2284 movs r2, #132 @ 0x84 8005110: 2100 movs r1, #0 8005112: 5499 strb r1, [r3, r2] return HAL_OK; 8005114: 2300 movs r3, #0 } 8005116: 0018 movs r0, r3 8005118: 46bd mov sp, r7 800511a: b004 add sp, #16 800511c: bd80 pop {r7, pc} ... 08005120 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8005120: b580 push {r7, lr} 8005122: b084 sub sp, #16 8005124: af00 add r7, sp, #0 8005126: 6078 str r0, [r7, #4] 8005128: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800512a: 687b ldr r3, [r7, #4] 800512c: 2284 movs r2, #132 @ 0x84 800512e: 5c9b ldrb r3, [r3, r2] 8005130: 2b01 cmp r3, #1 8005132: d101 bne.n 8005138 8005134: 2302 movs r3, #2 8005136: e02f b.n 8005198 8005138: 687b ldr r3, [r7, #4] 800513a: 2284 movs r2, #132 @ 0x84 800513c: 2101 movs r1, #1 800513e: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 8005140: 687b ldr r3, [r7, #4] 8005142: 2288 movs r2, #136 @ 0x88 8005144: 2124 movs r1, #36 @ 0x24 8005146: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8005148: 687b ldr r3, [r7, #4] 800514a: 681b ldr r3, [r3, #0] 800514c: 681b ldr r3, [r3, #0] 800514e: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8005150: 687b ldr r3, [r7, #4] 8005152: 681b ldr r3, [r3, #0] 8005154: 681a ldr r2, [r3, #0] 8005156: 687b ldr r3, [r7, #4] 8005158: 681b ldr r3, [r3, #0] 800515a: 2101 movs r1, #1 800515c: 438a bics r2, r1 800515e: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8005160: 687b ldr r3, [r7, #4] 8005162: 681b ldr r3, [r3, #0] 8005164: 689b ldr r3, [r3, #8] 8005166: 4a0e ldr r2, [pc, #56] @ (80051a0 ) 8005168: 4013 ands r3, r2 800516a: 0019 movs r1, r3 800516c: 687b ldr r3, [r7, #4] 800516e: 681b ldr r3, [r3, #0] 8005170: 683a ldr r2, [r7, #0] 8005172: 430a orrs r2, r1 8005174: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8005176: 687b ldr r3, [r7, #4] 8005178: 0018 movs r0, r3 800517a: f000 f813 bl 80051a4 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800517e: 687b ldr r3, [r7, #4] 8005180: 681b ldr r3, [r3, #0] 8005182: 68fa ldr r2, [r7, #12] 8005184: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8005186: 687b ldr r3, [r7, #4] 8005188: 2288 movs r2, #136 @ 0x88 800518a: 2120 movs r1, #32 800518c: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 800518e: 687b ldr r3, [r7, #4] 8005190: 2284 movs r2, #132 @ 0x84 8005192: 2100 movs r1, #0 8005194: 5499 strb r1, [r3, r2] return HAL_OK; 8005196: 2300 movs r3, #0 } 8005198: 0018 movs r0, r3 800519a: 46bd mov sp, r7 800519c: b004 add sp, #16 800519e: bd80 pop {r7, pc} 80051a0: f1ffffff .word 0xf1ffffff 080051a4 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80051a4: b5f0 push {r4, r5, r6, r7, lr} 80051a6: b085 sub sp, #20 80051a8: af00 add r7, sp, #0 80051aa: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80051ac: 687b ldr r3, [r7, #4] 80051ae: 6e5b ldr r3, [r3, #100] @ 0x64 80051b0: 2b00 cmp r3, #0 80051b2: d108 bne.n 80051c6 { huart->NbTxDataToProcess = 1U; 80051b4: 687b ldr r3, [r7, #4] 80051b6: 226a movs r2, #106 @ 0x6a 80051b8: 2101 movs r1, #1 80051ba: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1U; 80051bc: 687b ldr r3, [r7, #4] 80051be: 2268 movs r2, #104 @ 0x68 80051c0: 2101 movs r1, #1 80051c2: 5299 strh r1, [r3, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80051c4: e043 b.n 800524e rx_fifo_depth = RX_FIFO_DEPTH; 80051c6: 260f movs r6, #15 80051c8: 19bb adds r3, r7, r6 80051ca: 2208 movs r2, #8 80051cc: 701a strb r2, [r3, #0] tx_fifo_depth = TX_FIFO_DEPTH; 80051ce: 200e movs r0, #14 80051d0: 183b adds r3, r7, r0 80051d2: 2208 movs r2, #8 80051d4: 701a strb r2, [r3, #0] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80051d6: 687b ldr r3, [r7, #4] 80051d8: 681b ldr r3, [r3, #0] 80051da: 689b ldr r3, [r3, #8] 80051dc: 0e5b lsrs r3, r3, #25 80051de: b2da uxtb r2, r3 80051e0: 240d movs r4, #13 80051e2: 193b adds r3, r7, r4 80051e4: 2107 movs r1, #7 80051e6: 400a ands r2, r1 80051e8: 701a strb r2, [r3, #0] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 80051ea: 687b ldr r3, [r7, #4] 80051ec: 681b ldr r3, [r3, #0] 80051ee: 689b ldr r3, [r3, #8] 80051f0: 0f5b lsrs r3, r3, #29 80051f2: b2da uxtb r2, r3 80051f4: 250c movs r5, #12 80051f6: 197b adds r3, r7, r5 80051f8: 2107 movs r1, #7 80051fa: 400a ands r2, r1 80051fc: 701a strb r2, [r3, #0] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 80051fe: 183b adds r3, r7, r0 8005200: 781b ldrb r3, [r3, #0] 8005202: 197a adds r2, r7, r5 8005204: 7812 ldrb r2, [r2, #0] 8005206: 4914 ldr r1, [pc, #80] @ (8005258 ) 8005208: 5c8a ldrb r2, [r1, r2] 800520a: 435a muls r2, r3 800520c: 0010 movs r0, r2 (uint16_t)denominator[tx_fifo_threshold]; 800520e: 197b adds r3, r7, r5 8005210: 781b ldrb r3, [r3, #0] 8005212: 4a12 ldr r2, [pc, #72] @ (800525c ) 8005214: 5cd3 ldrb r3, [r2, r3] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8005216: 0019 movs r1, r3 8005218: f7fb f806 bl 8000228 <__divsi3> 800521c: 0003 movs r3, r0 800521e: b299 uxth r1, r3 8005220: 687b ldr r3, [r7, #4] 8005222: 226a movs r2, #106 @ 0x6a 8005224: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8005226: 19bb adds r3, r7, r6 8005228: 781b ldrb r3, [r3, #0] 800522a: 193a adds r2, r7, r4 800522c: 7812 ldrb r2, [r2, #0] 800522e: 490a ldr r1, [pc, #40] @ (8005258 ) 8005230: 5c8a ldrb r2, [r1, r2] 8005232: 435a muls r2, r3 8005234: 0010 movs r0, r2 (uint16_t)denominator[rx_fifo_threshold]; 8005236: 193b adds r3, r7, r4 8005238: 781b ldrb r3, [r3, #0] 800523a: 4a08 ldr r2, [pc, #32] @ (800525c ) 800523c: 5cd3 ldrb r3, [r2, r3] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800523e: 0019 movs r1, r3 8005240: f7fa fff2 bl 8000228 <__divsi3> 8005244: 0003 movs r3, r0 8005246: b299 uxth r1, r3 8005248: 687b ldr r3, [r7, #4] 800524a: 2268 movs r2, #104 @ 0x68 800524c: 5299 strh r1, [r3, r2] } 800524e: 46c0 nop @ (mov r8, r8) 8005250: 46bd mov sp, r7 8005252: b005 add sp, #20 8005254: bdf0 pop {r4, r5, r6, r7, pc} 8005256: 46c0 nop @ (mov r8, r8) 8005258: 080062b8 .word 0x080062b8 800525c: 080062c0 .word 0x080062c0 08005260 : 8005260: 2300 movs r3, #0 8005262: b510 push {r4, lr} 8005264: 0004 movs r4, r0 8005266: 6003 str r3, [r0, #0] 8005268: 6043 str r3, [r0, #4] 800526a: 6083 str r3, [r0, #8] 800526c: 8181 strh r1, [r0, #12] 800526e: 6643 str r3, [r0, #100] @ 0x64 8005270: 81c2 strh r2, [r0, #14] 8005272: 6103 str r3, [r0, #16] 8005274: 6143 str r3, [r0, #20] 8005276: 6183 str r3, [r0, #24] 8005278: 0019 movs r1, r3 800527a: 2208 movs r2, #8 800527c: 305c adds r0, #92 @ 0x5c 800527e: f000 fa0f bl 80056a0 8005282: 4b0b ldr r3, [pc, #44] @ (80052b0 ) 8005284: 6224 str r4, [r4, #32] 8005286: 6263 str r3, [r4, #36] @ 0x24 8005288: 4b0a ldr r3, [pc, #40] @ (80052b4 ) 800528a: 62a3 str r3, [r4, #40] @ 0x28 800528c: 4b0a ldr r3, [pc, #40] @ (80052b8 ) 800528e: 62e3 str r3, [r4, #44] @ 0x2c 8005290: 4b0a ldr r3, [pc, #40] @ (80052bc ) 8005292: 6323 str r3, [r4, #48] @ 0x30 8005294: 4b0a ldr r3, [pc, #40] @ (80052c0 ) 8005296: 429c cmp r4, r3 8005298: d005 beq.n 80052a6 800529a: 4b0a ldr r3, [pc, #40] @ (80052c4 ) 800529c: 429c cmp r4, r3 800529e: d002 beq.n 80052a6 80052a0: 4b09 ldr r3, [pc, #36] @ (80052c8 ) 80052a2: 429c cmp r4, r3 80052a4: d103 bne.n 80052ae 80052a6: 0020 movs r0, r4 80052a8: 3058 adds r0, #88 @ 0x58 80052aa: f000 fa79 bl 80057a0 <__retarget_lock_init_recursive> 80052ae: bd10 pop {r4, pc} 80052b0: 080054c9 .word 0x080054c9 80052b4: 080054f1 .word 0x080054f1 80052b8: 08005529 .word 0x08005529 80052bc: 08005555 .word 0x08005555 80052c0: 200001dc .word 0x200001dc 80052c4: 20000244 .word 0x20000244 80052c8: 200002ac .word 0x200002ac 080052cc : 80052cc: b510 push {r4, lr} 80052ce: 4a03 ldr r2, [pc, #12] @ (80052dc ) 80052d0: 4903 ldr r1, [pc, #12] @ (80052e0 ) 80052d2: 4804 ldr r0, [pc, #16] @ (80052e4 ) 80052d4: f000 f86c bl 80053b0 <_fwalk_sglue> 80052d8: bd10 pop {r4, pc} 80052da: 46c0 nop @ (mov r8, r8) 80052dc: 2000000c .word 0x2000000c 80052e0: 08006031 .word 0x08006031 80052e4: 2000001c .word 0x2000001c 080052e8 : 80052e8: 6841 ldr r1, [r0, #4] 80052ea: 4b0b ldr r3, [pc, #44] @ (8005318 ) 80052ec: b510 push {r4, lr} 80052ee: 0004 movs r4, r0 80052f0: 4299 cmp r1, r3 80052f2: d001 beq.n 80052f8 80052f4: f000 fe9c bl 8006030 <_fflush_r> 80052f8: 68a1 ldr r1, [r4, #8] 80052fa: 4b08 ldr r3, [pc, #32] @ (800531c ) 80052fc: 4299 cmp r1, r3 80052fe: d002 beq.n 8005306 8005300: 0020 movs r0, r4 8005302: f000 fe95 bl 8006030 <_fflush_r> 8005306: 68e1 ldr r1, [r4, #12] 8005308: 4b05 ldr r3, [pc, #20] @ (8005320 ) 800530a: 4299 cmp r1, r3 800530c: d002 beq.n 8005314 800530e: 0020 movs r0, r4 8005310: f000 fe8e bl 8006030 <_fflush_r> 8005314: bd10 pop {r4, pc} 8005316: 46c0 nop @ (mov r8, r8) 8005318: 200001dc .word 0x200001dc 800531c: 20000244 .word 0x20000244 8005320: 200002ac .word 0x200002ac 08005324 : 8005324: b510 push {r4, lr} 8005326: 4b09 ldr r3, [pc, #36] @ (800534c ) 8005328: 4a09 ldr r2, [pc, #36] @ (8005350 ) 800532a: 2104 movs r1, #4 800532c: 601a str r2, [r3, #0] 800532e: 4809 ldr r0, [pc, #36] @ (8005354 ) 8005330: 2200 movs r2, #0 8005332: f7ff ff95 bl 8005260 8005336: 2201 movs r2, #1 8005338: 2109 movs r1, #9 800533a: 4807 ldr r0, [pc, #28] @ (8005358 ) 800533c: f7ff ff90 bl 8005260 8005340: 2202 movs r2, #2 8005342: 2112 movs r1, #18 8005344: 4805 ldr r0, [pc, #20] @ (800535c ) 8005346: f7ff ff8b bl 8005260 800534a: bd10 pop {r4, pc} 800534c: 20000314 .word 0x20000314 8005350: 080052cd .word 0x080052cd 8005354: 200001dc .word 0x200001dc 8005358: 20000244 .word 0x20000244 800535c: 200002ac .word 0x200002ac 08005360 <__sfp_lock_acquire>: 8005360: b510 push {r4, lr} 8005362: 4802 ldr r0, [pc, #8] @ (800536c <__sfp_lock_acquire+0xc>) 8005364: f000 fa1d bl 80057a2 <__retarget_lock_acquire_recursive> 8005368: bd10 pop {r4, pc} 800536a: 46c0 nop @ (mov r8, r8) 800536c: 2000031d .word 0x2000031d 08005370 <__sfp_lock_release>: 8005370: b510 push {r4, lr} 8005372: 4802 ldr r0, [pc, #8] @ (800537c <__sfp_lock_release+0xc>) 8005374: f000 fa16 bl 80057a4 <__retarget_lock_release_recursive> 8005378: bd10 pop {r4, pc} 800537a: 46c0 nop @ (mov r8, r8) 800537c: 2000031d .word 0x2000031d 08005380 <__sinit>: 8005380: b510 push {r4, lr} 8005382: 0004 movs r4, r0 8005384: f7ff ffec bl 8005360 <__sfp_lock_acquire> 8005388: 6a23 ldr r3, [r4, #32] 800538a: 2b00 cmp r3, #0 800538c: d002 beq.n 8005394 <__sinit+0x14> 800538e: f7ff ffef bl 8005370 <__sfp_lock_release> 8005392: bd10 pop {r4, pc} 8005394: 4b04 ldr r3, [pc, #16] @ (80053a8 <__sinit+0x28>) 8005396: 6223 str r3, [r4, #32] 8005398: 4b04 ldr r3, [pc, #16] @ (80053ac <__sinit+0x2c>) 800539a: 681b ldr r3, [r3, #0] 800539c: 2b00 cmp r3, #0 800539e: d1f6 bne.n 800538e <__sinit+0xe> 80053a0: f7ff ffc0 bl 8005324 80053a4: e7f3 b.n 800538e <__sinit+0xe> 80053a6: 46c0 nop @ (mov r8, r8) 80053a8: 080052e9 .word 0x080052e9 80053ac: 20000314 .word 0x20000314 080053b0 <_fwalk_sglue>: 80053b0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 80053b2: 0014 movs r4, r2 80053b4: 2600 movs r6, #0 80053b6: 9000 str r0, [sp, #0] 80053b8: 9101 str r1, [sp, #4] 80053ba: 68a5 ldr r5, [r4, #8] 80053bc: 6867 ldr r7, [r4, #4] 80053be: 3f01 subs r7, #1 80053c0: d504 bpl.n 80053cc <_fwalk_sglue+0x1c> 80053c2: 6824 ldr r4, [r4, #0] 80053c4: 2c00 cmp r4, #0 80053c6: d1f8 bne.n 80053ba <_fwalk_sglue+0xa> 80053c8: 0030 movs r0, r6 80053ca: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 80053cc: 89ab ldrh r3, [r5, #12] 80053ce: 2b01 cmp r3, #1 80053d0: d908 bls.n 80053e4 <_fwalk_sglue+0x34> 80053d2: 220e movs r2, #14 80053d4: 5eab ldrsh r3, [r5, r2] 80053d6: 3301 adds r3, #1 80053d8: d004 beq.n 80053e4 <_fwalk_sglue+0x34> 80053da: 0029 movs r1, r5 80053dc: 9800 ldr r0, [sp, #0] 80053de: 9b01 ldr r3, [sp, #4] 80053e0: 4798 blx r3 80053e2: 4306 orrs r6, r0 80053e4: 3568 adds r5, #104 @ 0x68 80053e6: e7ea b.n 80053be <_fwalk_sglue+0xe> 080053e8 : 80053e8: b40f push {r0, r1, r2, r3} 80053ea: b507 push {r0, r1, r2, lr} 80053ec: 4905 ldr r1, [pc, #20] @ (8005404 ) 80053ee: ab04 add r3, sp, #16 80053f0: 6808 ldr r0, [r1, #0] 80053f2: cb04 ldmia r3!, {r2} 80053f4: 6881 ldr r1, [r0, #8] 80053f6: 9301 str r3, [sp, #4] 80053f8: f000 fafa bl 80059f0 <_vfiprintf_r> 80053fc: b003 add sp, #12 80053fe: bc08 pop {r3} 8005400: b004 add sp, #16 8005402: 4718 bx r3 8005404: 20000018 .word 0x20000018 08005408 <_puts_r>: 8005408: 6a03 ldr r3, [r0, #32] 800540a: b570 push {r4, r5, r6, lr} 800540c: 0005 movs r5, r0 800540e: 000e movs r6, r1 8005410: 6884 ldr r4, [r0, #8] 8005412: 2b00 cmp r3, #0 8005414: d101 bne.n 800541a <_puts_r+0x12> 8005416: f7ff ffb3 bl 8005380 <__sinit> 800541a: 6e63 ldr r3, [r4, #100] @ 0x64 800541c: 07db lsls r3, r3, #31 800541e: d405 bmi.n 800542c <_puts_r+0x24> 8005420: 89a3 ldrh r3, [r4, #12] 8005422: 059b lsls r3, r3, #22 8005424: d402 bmi.n 800542c <_puts_r+0x24> 8005426: 6da0 ldr r0, [r4, #88] @ 0x58 8005428: f000 f9bb bl 80057a2 <__retarget_lock_acquire_recursive> 800542c: 89a3 ldrh r3, [r4, #12] 800542e: 071b lsls r3, r3, #28 8005430: d502 bpl.n 8005438 <_puts_r+0x30> 8005432: 6923 ldr r3, [r4, #16] 8005434: 2b00 cmp r3, #0 8005436: d11f bne.n 8005478 <_puts_r+0x70> 8005438: 0021 movs r1, r4 800543a: 0028 movs r0, r5 800543c: f000 f8d2 bl 80055e4 <__swsetup_r> 8005440: 2800 cmp r0, #0 8005442: d019 beq.n 8005478 <_puts_r+0x70> 8005444: 2501 movs r5, #1 8005446: 426d negs r5, r5 8005448: 6e63 ldr r3, [r4, #100] @ 0x64 800544a: 07db lsls r3, r3, #31 800544c: d405 bmi.n 800545a <_puts_r+0x52> 800544e: 89a3 ldrh r3, [r4, #12] 8005450: 059b lsls r3, r3, #22 8005452: d402 bmi.n 800545a <_puts_r+0x52> 8005454: 6da0 ldr r0, [r4, #88] @ 0x58 8005456: f000 f9a5 bl 80057a4 <__retarget_lock_release_recursive> 800545a: 0028 movs r0, r5 800545c: bd70 pop {r4, r5, r6, pc} 800545e: 3601 adds r6, #1 8005460: 60a3 str r3, [r4, #8] 8005462: 2b00 cmp r3, #0 8005464: da04 bge.n 8005470 <_puts_r+0x68> 8005466: 69a2 ldr r2, [r4, #24] 8005468: 429a cmp r2, r3 800546a: dc16 bgt.n 800549a <_puts_r+0x92> 800546c: 290a cmp r1, #10 800546e: d014 beq.n 800549a <_puts_r+0x92> 8005470: 6823 ldr r3, [r4, #0] 8005472: 1c5a adds r2, r3, #1 8005474: 6022 str r2, [r4, #0] 8005476: 7019 strb r1, [r3, #0] 8005478: 68a3 ldr r3, [r4, #8] 800547a: 7831 ldrb r1, [r6, #0] 800547c: 3b01 subs r3, #1 800547e: 2900 cmp r1, #0 8005480: d1ed bne.n 800545e <_puts_r+0x56> 8005482: 60a3 str r3, [r4, #8] 8005484: 2b00 cmp r3, #0 8005486: da0f bge.n 80054a8 <_puts_r+0xa0> 8005488: 0022 movs r2, r4 800548a: 0028 movs r0, r5 800548c: 310a adds r1, #10 800548e: f000 f867 bl 8005560 <__swbuf_r> 8005492: 3001 adds r0, #1 8005494: d0d6 beq.n 8005444 <_puts_r+0x3c> 8005496: 250a movs r5, #10 8005498: e7d6 b.n 8005448 <_puts_r+0x40> 800549a: 0022 movs r2, r4 800549c: 0028 movs r0, r5 800549e: f000 f85f bl 8005560 <__swbuf_r> 80054a2: 3001 adds r0, #1 80054a4: d1e8 bne.n 8005478 <_puts_r+0x70> 80054a6: e7cd b.n 8005444 <_puts_r+0x3c> 80054a8: 6823 ldr r3, [r4, #0] 80054aa: 1c5a adds r2, r3, #1 80054ac: 6022 str r2, [r4, #0] 80054ae: 220a movs r2, #10 80054b0: 701a strb r2, [r3, #0] 80054b2: e7f0 b.n 8005496 <_puts_r+0x8e> 080054b4 : 80054b4: b510 push {r4, lr} 80054b6: 4b03 ldr r3, [pc, #12] @ (80054c4 ) 80054b8: 0001 movs r1, r0 80054ba: 6818 ldr r0, [r3, #0] 80054bc: f7ff ffa4 bl 8005408 <_puts_r> 80054c0: bd10 pop {r4, pc} 80054c2: 46c0 nop @ (mov r8, r8) 80054c4: 20000018 .word 0x20000018 080054c8 <__sread>: 80054c8: b570 push {r4, r5, r6, lr} 80054ca: 000c movs r4, r1 80054cc: 250e movs r5, #14 80054ce: 5f49 ldrsh r1, [r1, r5] 80054d0: f000 f914 bl 80056fc <_read_r> 80054d4: 2800 cmp r0, #0 80054d6: db03 blt.n 80054e0 <__sread+0x18> 80054d8: 6d63 ldr r3, [r4, #84] @ 0x54 80054da: 181b adds r3, r3, r0 80054dc: 6563 str r3, [r4, #84] @ 0x54 80054de: bd70 pop {r4, r5, r6, pc} 80054e0: 89a3 ldrh r3, [r4, #12] 80054e2: 4a02 ldr r2, [pc, #8] @ (80054ec <__sread+0x24>) 80054e4: 4013 ands r3, r2 80054e6: 81a3 strh r3, [r4, #12] 80054e8: e7f9 b.n 80054de <__sread+0x16> 80054ea: 46c0 nop @ (mov r8, r8) 80054ec: ffffefff .word 0xffffefff 080054f0 <__swrite>: 80054f0: b5f8 push {r3, r4, r5, r6, r7, lr} 80054f2: 001f movs r7, r3 80054f4: 898b ldrh r3, [r1, #12] 80054f6: 0005 movs r5, r0 80054f8: 000c movs r4, r1 80054fa: 0016 movs r6, r2 80054fc: 05db lsls r3, r3, #23 80054fe: d505 bpl.n 800550c <__swrite+0x1c> 8005500: 230e movs r3, #14 8005502: 5ec9 ldrsh r1, [r1, r3] 8005504: 2200 movs r2, #0 8005506: 2302 movs r3, #2 8005508: f000 f8e4 bl 80056d4 <_lseek_r> 800550c: 89a3 ldrh r3, [r4, #12] 800550e: 4a05 ldr r2, [pc, #20] @ (8005524 <__swrite+0x34>) 8005510: 0028 movs r0, r5 8005512: 4013 ands r3, r2 8005514: 81a3 strh r3, [r4, #12] 8005516: 0032 movs r2, r6 8005518: 230e movs r3, #14 800551a: 5ee1 ldrsh r1, [r4, r3] 800551c: 003b movs r3, r7 800551e: f000 f901 bl 8005724 <_write_r> 8005522: bdf8 pop {r3, r4, r5, r6, r7, pc} 8005524: ffffefff .word 0xffffefff 08005528 <__sseek>: 8005528: b570 push {r4, r5, r6, lr} 800552a: 000c movs r4, r1 800552c: 250e movs r5, #14 800552e: 5f49 ldrsh r1, [r1, r5] 8005530: f000 f8d0 bl 80056d4 <_lseek_r> 8005534: 89a3 ldrh r3, [r4, #12] 8005536: 1c42 adds r2, r0, #1 8005538: d103 bne.n 8005542 <__sseek+0x1a> 800553a: 4a05 ldr r2, [pc, #20] @ (8005550 <__sseek+0x28>) 800553c: 4013 ands r3, r2 800553e: 81a3 strh r3, [r4, #12] 8005540: bd70 pop {r4, r5, r6, pc} 8005542: 2280 movs r2, #128 @ 0x80 8005544: 0152 lsls r2, r2, #5 8005546: 4313 orrs r3, r2 8005548: 81a3 strh r3, [r4, #12] 800554a: 6560 str r0, [r4, #84] @ 0x54 800554c: e7f8 b.n 8005540 <__sseek+0x18> 800554e: 46c0 nop @ (mov r8, r8) 8005550: ffffefff .word 0xffffefff 08005554 <__sclose>: 8005554: b510 push {r4, lr} 8005556: 230e movs r3, #14 8005558: 5ec9 ldrsh r1, [r1, r3] 800555a: f000 f8a9 bl 80056b0 <_close_r> 800555e: bd10 pop {r4, pc} 08005560 <__swbuf_r>: 8005560: b5f8 push {r3, r4, r5, r6, r7, lr} 8005562: 0006 movs r6, r0 8005564: 000d movs r5, r1 8005566: 0014 movs r4, r2 8005568: 2800 cmp r0, #0 800556a: d004 beq.n 8005576 <__swbuf_r+0x16> 800556c: 6a03 ldr r3, [r0, #32] 800556e: 2b00 cmp r3, #0 8005570: d101 bne.n 8005576 <__swbuf_r+0x16> 8005572: f7ff ff05 bl 8005380 <__sinit> 8005576: 69a3 ldr r3, [r4, #24] 8005578: 60a3 str r3, [r4, #8] 800557a: 89a3 ldrh r3, [r4, #12] 800557c: 071b lsls r3, r3, #28 800557e: d502 bpl.n 8005586 <__swbuf_r+0x26> 8005580: 6923 ldr r3, [r4, #16] 8005582: 2b00 cmp r3, #0 8005584: d109 bne.n 800559a <__swbuf_r+0x3a> 8005586: 0021 movs r1, r4 8005588: 0030 movs r0, r6 800558a: f000 f82b bl 80055e4 <__swsetup_r> 800558e: 2800 cmp r0, #0 8005590: d003 beq.n 800559a <__swbuf_r+0x3a> 8005592: 2501 movs r5, #1 8005594: 426d negs r5, r5 8005596: 0028 movs r0, r5 8005598: bdf8 pop {r3, r4, r5, r6, r7, pc} 800559a: 6923 ldr r3, [r4, #16] 800559c: 6820 ldr r0, [r4, #0] 800559e: b2ef uxtb r7, r5 80055a0: 1ac0 subs r0, r0, r3 80055a2: 6963 ldr r3, [r4, #20] 80055a4: b2ed uxtb r5, r5 80055a6: 4283 cmp r3, r0 80055a8: dc05 bgt.n 80055b6 <__swbuf_r+0x56> 80055aa: 0021 movs r1, r4 80055ac: 0030 movs r0, r6 80055ae: f000 fd3f bl 8006030 <_fflush_r> 80055b2: 2800 cmp r0, #0 80055b4: d1ed bne.n 8005592 <__swbuf_r+0x32> 80055b6: 68a3 ldr r3, [r4, #8] 80055b8: 3001 adds r0, #1 80055ba: 3b01 subs r3, #1 80055bc: 60a3 str r3, [r4, #8] 80055be: 6823 ldr r3, [r4, #0] 80055c0: 1c5a adds r2, r3, #1 80055c2: 6022 str r2, [r4, #0] 80055c4: 701f strb r7, [r3, #0] 80055c6: 6963 ldr r3, [r4, #20] 80055c8: 4283 cmp r3, r0 80055ca: d004 beq.n 80055d6 <__swbuf_r+0x76> 80055cc: 89a3 ldrh r3, [r4, #12] 80055ce: 07db lsls r3, r3, #31 80055d0: d5e1 bpl.n 8005596 <__swbuf_r+0x36> 80055d2: 2d0a cmp r5, #10 80055d4: d1df bne.n 8005596 <__swbuf_r+0x36> 80055d6: 0021 movs r1, r4 80055d8: 0030 movs r0, r6 80055da: f000 fd29 bl 8006030 <_fflush_r> 80055de: 2800 cmp r0, #0 80055e0: d0d9 beq.n 8005596 <__swbuf_r+0x36> 80055e2: e7d6 b.n 8005592 <__swbuf_r+0x32> 080055e4 <__swsetup_r>: 80055e4: 4b2d ldr r3, [pc, #180] @ (800569c <__swsetup_r+0xb8>) 80055e6: b570 push {r4, r5, r6, lr} 80055e8: 0005 movs r5, r0 80055ea: 6818 ldr r0, [r3, #0] 80055ec: 000c movs r4, r1 80055ee: 2800 cmp r0, #0 80055f0: d004 beq.n 80055fc <__swsetup_r+0x18> 80055f2: 6a03 ldr r3, [r0, #32] 80055f4: 2b00 cmp r3, #0 80055f6: d101 bne.n 80055fc <__swsetup_r+0x18> 80055f8: f7ff fec2 bl 8005380 <__sinit> 80055fc: 230c movs r3, #12 80055fe: 5ee2 ldrsh r2, [r4, r3] 8005600: 0713 lsls r3, r2, #28 8005602: d423 bmi.n 800564c <__swsetup_r+0x68> 8005604: 06d3 lsls r3, r2, #27 8005606: d407 bmi.n 8005618 <__swsetup_r+0x34> 8005608: 2309 movs r3, #9 800560a: 602b str r3, [r5, #0] 800560c: 2340 movs r3, #64 @ 0x40 800560e: 2001 movs r0, #1 8005610: 4313 orrs r3, r2 8005612: 81a3 strh r3, [r4, #12] 8005614: 4240 negs r0, r0 8005616: e03a b.n 800568e <__swsetup_r+0xaa> 8005618: 0752 lsls r2, r2, #29 800561a: d513 bpl.n 8005644 <__swsetup_r+0x60> 800561c: 6b61 ldr r1, [r4, #52] @ 0x34 800561e: 2900 cmp r1, #0 8005620: d008 beq.n 8005634 <__swsetup_r+0x50> 8005622: 0023 movs r3, r4 8005624: 3344 adds r3, #68 @ 0x44 8005626: 4299 cmp r1, r3 8005628: d002 beq.n 8005630 <__swsetup_r+0x4c> 800562a: 0028 movs r0, r5 800562c: f000 f8bc bl 80057a8 <_free_r> 8005630: 2300 movs r3, #0 8005632: 6363 str r3, [r4, #52] @ 0x34 8005634: 2224 movs r2, #36 @ 0x24 8005636: 89a3 ldrh r3, [r4, #12] 8005638: 4393 bics r3, r2 800563a: 81a3 strh r3, [r4, #12] 800563c: 2300 movs r3, #0 800563e: 6063 str r3, [r4, #4] 8005640: 6923 ldr r3, [r4, #16] 8005642: 6023 str r3, [r4, #0] 8005644: 2308 movs r3, #8 8005646: 89a2 ldrh r2, [r4, #12] 8005648: 4313 orrs r3, r2 800564a: 81a3 strh r3, [r4, #12] 800564c: 6923 ldr r3, [r4, #16] 800564e: 2b00 cmp r3, #0 8005650: d10b bne.n 800566a <__swsetup_r+0x86> 8005652: 21a0 movs r1, #160 @ 0xa0 8005654: 2280 movs r2, #128 @ 0x80 8005656: 89a3 ldrh r3, [r4, #12] 8005658: 0089 lsls r1, r1, #2 800565a: 0092 lsls r2, r2, #2 800565c: 400b ands r3, r1 800565e: 4293 cmp r3, r2 8005660: d003 beq.n 800566a <__swsetup_r+0x86> 8005662: 0021 movs r1, r4 8005664: 0028 movs r0, r5 8005666: f000 fd39 bl 80060dc <__smakebuf_r> 800566a: 230c movs r3, #12 800566c: 5ee2 ldrsh r2, [r4, r3] 800566e: 2101 movs r1, #1 8005670: 0013 movs r3, r2 8005672: 400b ands r3, r1 8005674: 420a tst r2, r1 8005676: d00b beq.n 8005690 <__swsetup_r+0xac> 8005678: 2300 movs r3, #0 800567a: 60a3 str r3, [r4, #8] 800567c: 6963 ldr r3, [r4, #20] 800567e: 425b negs r3, r3 8005680: 61a3 str r3, [r4, #24] 8005682: 2000 movs r0, #0 8005684: 6923 ldr r3, [r4, #16] 8005686: 4283 cmp r3, r0 8005688: d101 bne.n 800568e <__swsetup_r+0xaa> 800568a: 0613 lsls r3, r2, #24 800568c: d4be bmi.n 800560c <__swsetup_r+0x28> 800568e: bd70 pop {r4, r5, r6, pc} 8005690: 0791 lsls r1, r2, #30 8005692: d400 bmi.n 8005696 <__swsetup_r+0xb2> 8005694: 6963 ldr r3, [r4, #20] 8005696: 60a3 str r3, [r4, #8] 8005698: e7f3 b.n 8005682 <__swsetup_r+0x9e> 800569a: 46c0 nop @ (mov r8, r8) 800569c: 20000018 .word 0x20000018 080056a0 : 80056a0: 0003 movs r3, r0 80056a2: 1882 adds r2, r0, r2 80056a4: 4293 cmp r3, r2 80056a6: d100 bne.n 80056aa 80056a8: 4770 bx lr 80056aa: 7019 strb r1, [r3, #0] 80056ac: 3301 adds r3, #1 80056ae: e7f9 b.n 80056a4 080056b0 <_close_r>: 80056b0: 2300 movs r3, #0 80056b2: b570 push {r4, r5, r6, lr} 80056b4: 4d06 ldr r5, [pc, #24] @ (80056d0 <_close_r+0x20>) 80056b6: 0004 movs r4, r0 80056b8: 0008 movs r0, r1 80056ba: 602b str r3, [r5, #0] 80056bc: f7fb fec7 bl 800144e <_close> 80056c0: 1c43 adds r3, r0, #1 80056c2: d103 bne.n 80056cc <_close_r+0x1c> 80056c4: 682b ldr r3, [r5, #0] 80056c6: 2b00 cmp r3, #0 80056c8: d000 beq.n 80056cc <_close_r+0x1c> 80056ca: 6023 str r3, [r4, #0] 80056cc: bd70 pop {r4, r5, r6, pc} 80056ce: 46c0 nop @ (mov r8, r8) 80056d0: 20000318 .word 0x20000318 080056d4 <_lseek_r>: 80056d4: b570 push {r4, r5, r6, lr} 80056d6: 0004 movs r4, r0 80056d8: 0008 movs r0, r1 80056da: 0011 movs r1, r2 80056dc: 001a movs r2, r3 80056de: 2300 movs r3, #0 80056e0: 4d05 ldr r5, [pc, #20] @ (80056f8 <_lseek_r+0x24>) 80056e2: 602b str r3, [r5, #0] 80056e4: f7fb fed4 bl 8001490 <_lseek> 80056e8: 1c43 adds r3, r0, #1 80056ea: d103 bne.n 80056f4 <_lseek_r+0x20> 80056ec: 682b ldr r3, [r5, #0] 80056ee: 2b00 cmp r3, #0 80056f0: d000 beq.n 80056f4 <_lseek_r+0x20> 80056f2: 6023 str r3, [r4, #0] 80056f4: bd70 pop {r4, r5, r6, pc} 80056f6: 46c0 nop @ (mov r8, r8) 80056f8: 20000318 .word 0x20000318 080056fc <_read_r>: 80056fc: b570 push {r4, r5, r6, lr} 80056fe: 0004 movs r4, r0 8005700: 0008 movs r0, r1 8005702: 0011 movs r1, r2 8005704: 001a movs r2, r3 8005706: 2300 movs r3, #0 8005708: 4d05 ldr r5, [pc, #20] @ (8005720 <_read_r+0x24>) 800570a: 602b str r3, [r5, #0] 800570c: f7fb fe66 bl 80013dc <_read> 8005710: 1c43 adds r3, r0, #1 8005712: d103 bne.n 800571c <_read_r+0x20> 8005714: 682b ldr r3, [r5, #0] 8005716: 2b00 cmp r3, #0 8005718: d000 beq.n 800571c <_read_r+0x20> 800571a: 6023 str r3, [r4, #0] 800571c: bd70 pop {r4, r5, r6, pc} 800571e: 46c0 nop @ (mov r8, r8) 8005720: 20000318 .word 0x20000318 08005724 <_write_r>: 8005724: b570 push {r4, r5, r6, lr} 8005726: 0004 movs r4, r0 8005728: 0008 movs r0, r1 800572a: 0011 movs r1, r2 800572c: 001a movs r2, r3 800572e: 2300 movs r3, #0 8005730: 4d05 ldr r5, [pc, #20] @ (8005748 <_write_r+0x24>) 8005732: 602b str r3, [r5, #0] 8005734: f7fb fe6f bl 8001416 <_write> 8005738: 1c43 adds r3, r0, #1 800573a: d103 bne.n 8005744 <_write_r+0x20> 800573c: 682b ldr r3, [r5, #0] 800573e: 2b00 cmp r3, #0 8005740: d000 beq.n 8005744 <_write_r+0x20> 8005742: 6023 str r3, [r4, #0] 8005744: bd70 pop {r4, r5, r6, pc} 8005746: 46c0 nop @ (mov r8, r8) 8005748: 20000318 .word 0x20000318 0800574c <__errno>: 800574c: 4b01 ldr r3, [pc, #4] @ (8005754 <__errno+0x8>) 800574e: 6818 ldr r0, [r3, #0] 8005750: 4770 bx lr 8005752: 46c0 nop @ (mov r8, r8) 8005754: 20000018 .word 0x20000018 08005758 <__libc_init_array>: 8005758: b570 push {r4, r5, r6, lr} 800575a: 2600 movs r6, #0 800575c: 4c0c ldr r4, [pc, #48] @ (8005790 <__libc_init_array+0x38>) 800575e: 4d0d ldr r5, [pc, #52] @ (8005794 <__libc_init_array+0x3c>) 8005760: 1b64 subs r4, r4, r5 8005762: 10a4 asrs r4, r4, #2 8005764: 42a6 cmp r6, r4 8005766: d109 bne.n 800577c <__libc_init_array+0x24> 8005768: 2600 movs r6, #0 800576a: f000 fd3b bl 80061e4 <_init> 800576e: 4c0a ldr r4, [pc, #40] @ (8005798 <__libc_init_array+0x40>) 8005770: 4d0a ldr r5, [pc, #40] @ (800579c <__libc_init_array+0x44>) 8005772: 1b64 subs r4, r4, r5 8005774: 10a4 asrs r4, r4, #2 8005776: 42a6 cmp r6, r4 8005778: d105 bne.n 8005786 <__libc_init_array+0x2e> 800577a: bd70 pop {r4, r5, r6, pc} 800577c: 00b3 lsls r3, r6, #2 800577e: 58eb ldr r3, [r5, r3] 8005780: 4798 blx r3 8005782: 3601 adds r6, #1 8005784: e7ee b.n 8005764 <__libc_init_array+0xc> 8005786: 00b3 lsls r3, r6, #2 8005788: 58eb ldr r3, [r5, r3] 800578a: 4798 blx r3 800578c: 3601 adds r6, #1 800578e: e7f2 b.n 8005776 <__libc_init_array+0x1e> 8005790: 080062fc .word 0x080062fc 8005794: 080062fc .word 0x080062fc 8005798: 08006300 .word 0x08006300 800579c: 080062fc .word 0x080062fc 080057a0 <__retarget_lock_init_recursive>: 80057a0: 4770 bx lr 080057a2 <__retarget_lock_acquire_recursive>: 80057a2: 4770 bx lr 080057a4 <__retarget_lock_release_recursive>: 80057a4: 4770 bx lr ... 080057a8 <_free_r>: 80057a8: b570 push {r4, r5, r6, lr} 80057aa: 0005 movs r5, r0 80057ac: 1e0c subs r4, r1, #0 80057ae: d010 beq.n 80057d2 <_free_r+0x2a> 80057b0: 3c04 subs r4, #4 80057b2: 6823 ldr r3, [r4, #0] 80057b4: 2b00 cmp r3, #0 80057b6: da00 bge.n 80057ba <_free_r+0x12> 80057b8: 18e4 adds r4, r4, r3 80057ba: 0028 movs r0, r5 80057bc: f000 f8e0 bl 8005980 <__malloc_lock> 80057c0: 4a1d ldr r2, [pc, #116] @ (8005838 <_free_r+0x90>) 80057c2: 6813 ldr r3, [r2, #0] 80057c4: 2b00 cmp r3, #0 80057c6: d105 bne.n 80057d4 <_free_r+0x2c> 80057c8: 6063 str r3, [r4, #4] 80057ca: 6014 str r4, [r2, #0] 80057cc: 0028 movs r0, r5 80057ce: f000 f8df bl 8005990 <__malloc_unlock> 80057d2: bd70 pop {r4, r5, r6, pc} 80057d4: 42a3 cmp r3, r4 80057d6: d908 bls.n 80057ea <_free_r+0x42> 80057d8: 6820 ldr r0, [r4, #0] 80057da: 1821 adds r1, r4, r0 80057dc: 428b cmp r3, r1 80057de: d1f3 bne.n 80057c8 <_free_r+0x20> 80057e0: 6819 ldr r1, [r3, #0] 80057e2: 685b ldr r3, [r3, #4] 80057e4: 1809 adds r1, r1, r0 80057e6: 6021 str r1, [r4, #0] 80057e8: e7ee b.n 80057c8 <_free_r+0x20> 80057ea: 001a movs r2, r3 80057ec: 685b ldr r3, [r3, #4] 80057ee: 2b00 cmp r3, #0 80057f0: d001 beq.n 80057f6 <_free_r+0x4e> 80057f2: 42a3 cmp r3, r4 80057f4: d9f9 bls.n 80057ea <_free_r+0x42> 80057f6: 6811 ldr r1, [r2, #0] 80057f8: 1850 adds r0, r2, r1 80057fa: 42a0 cmp r0, r4 80057fc: d10b bne.n 8005816 <_free_r+0x6e> 80057fe: 6820 ldr r0, [r4, #0] 8005800: 1809 adds r1, r1, r0 8005802: 1850 adds r0, r2, r1 8005804: 6011 str r1, [r2, #0] 8005806: 4283 cmp r3, r0 8005808: d1e0 bne.n 80057cc <_free_r+0x24> 800580a: 6818 ldr r0, [r3, #0] 800580c: 685b ldr r3, [r3, #4] 800580e: 1841 adds r1, r0, r1 8005810: 6011 str r1, [r2, #0] 8005812: 6053 str r3, [r2, #4] 8005814: e7da b.n 80057cc <_free_r+0x24> 8005816: 42a0 cmp r0, r4 8005818: d902 bls.n 8005820 <_free_r+0x78> 800581a: 230c movs r3, #12 800581c: 602b str r3, [r5, #0] 800581e: e7d5 b.n 80057cc <_free_r+0x24> 8005820: 6820 ldr r0, [r4, #0] 8005822: 1821 adds r1, r4, r0 8005824: 428b cmp r3, r1 8005826: d103 bne.n 8005830 <_free_r+0x88> 8005828: 6819 ldr r1, [r3, #0] 800582a: 685b ldr r3, [r3, #4] 800582c: 1809 adds r1, r1, r0 800582e: 6021 str r1, [r4, #0] 8005830: 6063 str r3, [r4, #4] 8005832: 6054 str r4, [r2, #4] 8005834: e7ca b.n 80057cc <_free_r+0x24> 8005836: 46c0 nop @ (mov r8, r8) 8005838: 20000324 .word 0x20000324 0800583c : 800583c: b570 push {r4, r5, r6, lr} 800583e: 4e0f ldr r6, [pc, #60] @ (800587c ) 8005840: 000d movs r5, r1 8005842: 6831 ldr r1, [r6, #0] 8005844: 0004 movs r4, r0 8005846: 2900 cmp r1, #0 8005848: d102 bne.n 8005850 800584a: f000 fcad bl 80061a8 <_sbrk_r> 800584e: 6030 str r0, [r6, #0] 8005850: 0029 movs r1, r5 8005852: 0020 movs r0, r4 8005854: f000 fca8 bl 80061a8 <_sbrk_r> 8005858: 1c43 adds r3, r0, #1 800585a: d103 bne.n 8005864 800585c: 2501 movs r5, #1 800585e: 426d negs r5, r5 8005860: 0028 movs r0, r5 8005862: bd70 pop {r4, r5, r6, pc} 8005864: 2303 movs r3, #3 8005866: 1cc5 adds r5, r0, #3 8005868: 439d bics r5, r3 800586a: 42a8 cmp r0, r5 800586c: d0f8 beq.n 8005860 800586e: 1a29 subs r1, r5, r0 8005870: 0020 movs r0, r4 8005872: f000 fc99 bl 80061a8 <_sbrk_r> 8005876: 3001 adds r0, #1 8005878: d1f2 bne.n 8005860 800587a: e7ef b.n 800585c 800587c: 20000320 .word 0x20000320 08005880 <_malloc_r>: 8005880: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8005882: 2203 movs r2, #3 8005884: 1ccb adds r3, r1, #3 8005886: 4393 bics r3, r2 8005888: 3308 adds r3, #8 800588a: 0005 movs r5, r0 800588c: 001f movs r7, r3 800588e: 2b0c cmp r3, #12 8005890: d234 bcs.n 80058fc <_malloc_r+0x7c> 8005892: 270c movs r7, #12 8005894: 42b9 cmp r1, r7 8005896: d833 bhi.n 8005900 <_malloc_r+0x80> 8005898: 0028 movs r0, r5 800589a: f000 f871 bl 8005980 <__malloc_lock> 800589e: 4e37 ldr r6, [pc, #220] @ (800597c <_malloc_r+0xfc>) 80058a0: 6833 ldr r3, [r6, #0] 80058a2: 001c movs r4, r3 80058a4: 2c00 cmp r4, #0 80058a6: d12f bne.n 8005908 <_malloc_r+0x88> 80058a8: 0039 movs r1, r7 80058aa: 0028 movs r0, r5 80058ac: f7ff ffc6 bl 800583c 80058b0: 0004 movs r4, r0 80058b2: 1c43 adds r3, r0, #1 80058b4: d15f bne.n 8005976 <_malloc_r+0xf6> 80058b6: 6834 ldr r4, [r6, #0] 80058b8: 9400 str r4, [sp, #0] 80058ba: 9b00 ldr r3, [sp, #0] 80058bc: 2b00 cmp r3, #0 80058be: d14a bne.n 8005956 <_malloc_r+0xd6> 80058c0: 2c00 cmp r4, #0 80058c2: d052 beq.n 800596a <_malloc_r+0xea> 80058c4: 6823 ldr r3, [r4, #0] 80058c6: 0028 movs r0, r5 80058c8: 18e3 adds r3, r4, r3 80058ca: 9900 ldr r1, [sp, #0] 80058cc: 9301 str r3, [sp, #4] 80058ce: f000 fc6b bl 80061a8 <_sbrk_r> 80058d2: 9b01 ldr r3, [sp, #4] 80058d4: 4283 cmp r3, r0 80058d6: d148 bne.n 800596a <_malloc_r+0xea> 80058d8: 6823 ldr r3, [r4, #0] 80058da: 0028 movs r0, r5 80058dc: 1aff subs r7, r7, r3 80058de: 0039 movs r1, r7 80058e0: f7ff ffac bl 800583c 80058e4: 3001 adds r0, #1 80058e6: d040 beq.n 800596a <_malloc_r+0xea> 80058e8: 6823 ldr r3, [r4, #0] 80058ea: 19db adds r3, r3, r7 80058ec: 6023 str r3, [r4, #0] 80058ee: 6833 ldr r3, [r6, #0] 80058f0: 685a ldr r2, [r3, #4] 80058f2: 2a00 cmp r2, #0 80058f4: d133 bne.n 800595e <_malloc_r+0xde> 80058f6: 9b00 ldr r3, [sp, #0] 80058f8: 6033 str r3, [r6, #0] 80058fa: e019 b.n 8005930 <_malloc_r+0xb0> 80058fc: 2b00 cmp r3, #0 80058fe: dac9 bge.n 8005894 <_malloc_r+0x14> 8005900: 230c movs r3, #12 8005902: 602b str r3, [r5, #0] 8005904: 2000 movs r0, #0 8005906: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8005908: 6821 ldr r1, [r4, #0] 800590a: 1bc9 subs r1, r1, r7 800590c: d420 bmi.n 8005950 <_malloc_r+0xd0> 800590e: 290b cmp r1, #11 8005910: d90a bls.n 8005928 <_malloc_r+0xa8> 8005912: 19e2 adds r2, r4, r7 8005914: 6027 str r7, [r4, #0] 8005916: 42a3 cmp r3, r4 8005918: d104 bne.n 8005924 <_malloc_r+0xa4> 800591a: 6032 str r2, [r6, #0] 800591c: 6863 ldr r3, [r4, #4] 800591e: 6011 str r1, [r2, #0] 8005920: 6053 str r3, [r2, #4] 8005922: e005 b.n 8005930 <_malloc_r+0xb0> 8005924: 605a str r2, [r3, #4] 8005926: e7f9 b.n 800591c <_malloc_r+0x9c> 8005928: 6862 ldr r2, [r4, #4] 800592a: 42a3 cmp r3, r4 800592c: d10e bne.n 800594c <_malloc_r+0xcc> 800592e: 6032 str r2, [r6, #0] 8005930: 0028 movs r0, r5 8005932: f000 f82d bl 8005990 <__malloc_unlock> 8005936: 0020 movs r0, r4 8005938: 2207 movs r2, #7 800593a: 300b adds r0, #11 800593c: 1d23 adds r3, r4, #4 800593e: 4390 bics r0, r2 8005940: 1ac2 subs r2, r0, r3 8005942: 4298 cmp r0, r3 8005944: d0df beq.n 8005906 <_malloc_r+0x86> 8005946: 1a1b subs r3, r3, r0 8005948: 50a3 str r3, [r4, r2] 800594a: e7dc b.n 8005906 <_malloc_r+0x86> 800594c: 605a str r2, [r3, #4] 800594e: e7ef b.n 8005930 <_malloc_r+0xb0> 8005950: 0023 movs r3, r4 8005952: 6864 ldr r4, [r4, #4] 8005954: e7a6 b.n 80058a4 <_malloc_r+0x24> 8005956: 9c00 ldr r4, [sp, #0] 8005958: 6863 ldr r3, [r4, #4] 800595a: 9300 str r3, [sp, #0] 800595c: e7ad b.n 80058ba <_malloc_r+0x3a> 800595e: 001a movs r2, r3 8005960: 685b ldr r3, [r3, #4] 8005962: 42a3 cmp r3, r4 8005964: d1fb bne.n 800595e <_malloc_r+0xde> 8005966: 2300 movs r3, #0 8005968: e7da b.n 8005920 <_malloc_r+0xa0> 800596a: 230c movs r3, #12 800596c: 0028 movs r0, r5 800596e: 602b str r3, [r5, #0] 8005970: f000 f80e bl 8005990 <__malloc_unlock> 8005974: e7c6 b.n 8005904 <_malloc_r+0x84> 8005976: 6007 str r7, [r0, #0] 8005978: e7da b.n 8005930 <_malloc_r+0xb0> 800597a: 46c0 nop @ (mov r8, r8) 800597c: 20000324 .word 0x20000324 08005980 <__malloc_lock>: 8005980: b510 push {r4, lr} 8005982: 4802 ldr r0, [pc, #8] @ (800598c <__malloc_lock+0xc>) 8005984: f7ff ff0d bl 80057a2 <__retarget_lock_acquire_recursive> 8005988: bd10 pop {r4, pc} 800598a: 46c0 nop @ (mov r8, r8) 800598c: 2000031c .word 0x2000031c 08005990 <__malloc_unlock>: 8005990: b510 push {r4, lr} 8005992: 4802 ldr r0, [pc, #8] @ (800599c <__malloc_unlock+0xc>) 8005994: f7ff ff06 bl 80057a4 <__retarget_lock_release_recursive> 8005998: bd10 pop {r4, pc} 800599a: 46c0 nop @ (mov r8, r8) 800599c: 2000031c .word 0x2000031c 080059a0 <__sfputc_r>: 80059a0: 6893 ldr r3, [r2, #8] 80059a2: b510 push {r4, lr} 80059a4: 3b01 subs r3, #1 80059a6: 6093 str r3, [r2, #8] 80059a8: 2b00 cmp r3, #0 80059aa: da04 bge.n 80059b6 <__sfputc_r+0x16> 80059ac: 6994 ldr r4, [r2, #24] 80059ae: 42a3 cmp r3, r4 80059b0: db07 blt.n 80059c2 <__sfputc_r+0x22> 80059b2: 290a cmp r1, #10 80059b4: d005 beq.n 80059c2 <__sfputc_r+0x22> 80059b6: 6813 ldr r3, [r2, #0] 80059b8: 1c58 adds r0, r3, #1 80059ba: 6010 str r0, [r2, #0] 80059bc: 7019 strb r1, [r3, #0] 80059be: 0008 movs r0, r1 80059c0: bd10 pop {r4, pc} 80059c2: f7ff fdcd bl 8005560 <__swbuf_r> 80059c6: 0001 movs r1, r0 80059c8: e7f9 b.n 80059be <__sfputc_r+0x1e> 080059ca <__sfputs_r>: 80059ca: b5f8 push {r3, r4, r5, r6, r7, lr} 80059cc: 0006 movs r6, r0 80059ce: 000f movs r7, r1 80059d0: 0014 movs r4, r2 80059d2: 18d5 adds r5, r2, r3 80059d4: 42ac cmp r4, r5 80059d6: d101 bne.n 80059dc <__sfputs_r+0x12> 80059d8: 2000 movs r0, #0 80059da: e007 b.n 80059ec <__sfputs_r+0x22> 80059dc: 7821 ldrb r1, [r4, #0] 80059de: 003a movs r2, r7 80059e0: 0030 movs r0, r6 80059e2: f7ff ffdd bl 80059a0 <__sfputc_r> 80059e6: 3401 adds r4, #1 80059e8: 1c43 adds r3, r0, #1 80059ea: d1f3 bne.n 80059d4 <__sfputs_r+0xa> 80059ec: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 080059f0 <_vfiprintf_r>: 80059f0: b5f0 push {r4, r5, r6, r7, lr} 80059f2: b0a1 sub sp, #132 @ 0x84 80059f4: 000f movs r7, r1 80059f6: 0015 movs r5, r2 80059f8: 001e movs r6, r3 80059fa: 9003 str r0, [sp, #12] 80059fc: 2800 cmp r0, #0 80059fe: d004 beq.n 8005a0a <_vfiprintf_r+0x1a> 8005a00: 6a03 ldr r3, [r0, #32] 8005a02: 2b00 cmp r3, #0 8005a04: d101 bne.n 8005a0a <_vfiprintf_r+0x1a> 8005a06: f7ff fcbb bl 8005380 <__sinit> 8005a0a: 6e7b ldr r3, [r7, #100] @ 0x64 8005a0c: 07db lsls r3, r3, #31 8005a0e: d405 bmi.n 8005a1c <_vfiprintf_r+0x2c> 8005a10: 89bb ldrh r3, [r7, #12] 8005a12: 059b lsls r3, r3, #22 8005a14: d402 bmi.n 8005a1c <_vfiprintf_r+0x2c> 8005a16: 6db8 ldr r0, [r7, #88] @ 0x58 8005a18: f7ff fec3 bl 80057a2 <__retarget_lock_acquire_recursive> 8005a1c: 89bb ldrh r3, [r7, #12] 8005a1e: 071b lsls r3, r3, #28 8005a20: d502 bpl.n 8005a28 <_vfiprintf_r+0x38> 8005a22: 693b ldr r3, [r7, #16] 8005a24: 2b00 cmp r3, #0 8005a26: d113 bne.n 8005a50 <_vfiprintf_r+0x60> 8005a28: 0039 movs r1, r7 8005a2a: 9803 ldr r0, [sp, #12] 8005a2c: f7ff fdda bl 80055e4 <__swsetup_r> 8005a30: 2800 cmp r0, #0 8005a32: d00d beq.n 8005a50 <_vfiprintf_r+0x60> 8005a34: 6e7b ldr r3, [r7, #100] @ 0x64 8005a36: 07db lsls r3, r3, #31 8005a38: d503 bpl.n 8005a42 <_vfiprintf_r+0x52> 8005a3a: 2001 movs r0, #1 8005a3c: 4240 negs r0, r0 8005a3e: b021 add sp, #132 @ 0x84 8005a40: bdf0 pop {r4, r5, r6, r7, pc} 8005a42: 89bb ldrh r3, [r7, #12] 8005a44: 059b lsls r3, r3, #22 8005a46: d4f8 bmi.n 8005a3a <_vfiprintf_r+0x4a> 8005a48: 6db8 ldr r0, [r7, #88] @ 0x58 8005a4a: f7ff feab bl 80057a4 <__retarget_lock_release_recursive> 8005a4e: e7f4 b.n 8005a3a <_vfiprintf_r+0x4a> 8005a50: 2300 movs r3, #0 8005a52: ac08 add r4, sp, #32 8005a54: 6163 str r3, [r4, #20] 8005a56: 3320 adds r3, #32 8005a58: 7663 strb r3, [r4, #25] 8005a5a: 3310 adds r3, #16 8005a5c: 76a3 strb r3, [r4, #26] 8005a5e: 9607 str r6, [sp, #28] 8005a60: 002e movs r6, r5 8005a62: 7833 ldrb r3, [r6, #0] 8005a64: 2b00 cmp r3, #0 8005a66: d001 beq.n 8005a6c <_vfiprintf_r+0x7c> 8005a68: 2b25 cmp r3, #37 @ 0x25 8005a6a: d148 bne.n 8005afe <_vfiprintf_r+0x10e> 8005a6c: 1b73 subs r3, r6, r5 8005a6e: 9305 str r3, [sp, #20] 8005a70: 42ae cmp r6, r5 8005a72: d00b beq.n 8005a8c <_vfiprintf_r+0x9c> 8005a74: 002a movs r2, r5 8005a76: 0039 movs r1, r7 8005a78: 9803 ldr r0, [sp, #12] 8005a7a: f7ff ffa6 bl 80059ca <__sfputs_r> 8005a7e: 3001 adds r0, #1 8005a80: d100 bne.n 8005a84 <_vfiprintf_r+0x94> 8005a82: e0ae b.n 8005be2 <_vfiprintf_r+0x1f2> 8005a84: 6963 ldr r3, [r4, #20] 8005a86: 9a05 ldr r2, [sp, #20] 8005a88: 189b adds r3, r3, r2 8005a8a: 6163 str r3, [r4, #20] 8005a8c: 7833 ldrb r3, [r6, #0] 8005a8e: 2b00 cmp r3, #0 8005a90: d100 bne.n 8005a94 <_vfiprintf_r+0xa4> 8005a92: e0a6 b.n 8005be2 <_vfiprintf_r+0x1f2> 8005a94: 2201 movs r2, #1 8005a96: 2300 movs r3, #0 8005a98: 4252 negs r2, r2 8005a9a: 6062 str r2, [r4, #4] 8005a9c: a904 add r1, sp, #16 8005a9e: 3254 adds r2, #84 @ 0x54 8005aa0: 1852 adds r2, r2, r1 8005aa2: 1c75 adds r5, r6, #1 8005aa4: 6023 str r3, [r4, #0] 8005aa6: 60e3 str r3, [r4, #12] 8005aa8: 60a3 str r3, [r4, #8] 8005aaa: 7013 strb r3, [r2, #0] 8005aac: 65a3 str r3, [r4, #88] @ 0x58 8005aae: 4b59 ldr r3, [pc, #356] @ (8005c14 <_vfiprintf_r+0x224>) 8005ab0: 2205 movs r2, #5 8005ab2: 0018 movs r0, r3 8005ab4: 7829 ldrb r1, [r5, #0] 8005ab6: 9305 str r3, [sp, #20] 8005ab8: f000 fb88 bl 80061cc 8005abc: 1c6e adds r6, r5, #1 8005abe: 2800 cmp r0, #0 8005ac0: d11f bne.n 8005b02 <_vfiprintf_r+0x112> 8005ac2: 6822 ldr r2, [r4, #0] 8005ac4: 06d3 lsls r3, r2, #27 8005ac6: d504 bpl.n 8005ad2 <_vfiprintf_r+0xe2> 8005ac8: 2353 movs r3, #83 @ 0x53 8005aca: a904 add r1, sp, #16 8005acc: 185b adds r3, r3, r1 8005ace: 2120 movs r1, #32 8005ad0: 7019 strb r1, [r3, #0] 8005ad2: 0713 lsls r3, r2, #28 8005ad4: d504 bpl.n 8005ae0 <_vfiprintf_r+0xf0> 8005ad6: 2353 movs r3, #83 @ 0x53 8005ad8: a904 add r1, sp, #16 8005ada: 185b adds r3, r3, r1 8005adc: 212b movs r1, #43 @ 0x2b 8005ade: 7019 strb r1, [r3, #0] 8005ae0: 782b ldrb r3, [r5, #0] 8005ae2: 2b2a cmp r3, #42 @ 0x2a 8005ae4: d016 beq.n 8005b14 <_vfiprintf_r+0x124> 8005ae6: 002e movs r6, r5 8005ae8: 2100 movs r1, #0 8005aea: 200a movs r0, #10 8005aec: 68e3 ldr r3, [r4, #12] 8005aee: 7832 ldrb r2, [r6, #0] 8005af0: 1c75 adds r5, r6, #1 8005af2: 3a30 subs r2, #48 @ 0x30 8005af4: 2a09 cmp r2, #9 8005af6: d950 bls.n 8005b9a <_vfiprintf_r+0x1aa> 8005af8: 2900 cmp r1, #0 8005afa: d111 bne.n 8005b20 <_vfiprintf_r+0x130> 8005afc: e017 b.n 8005b2e <_vfiprintf_r+0x13e> 8005afe: 3601 adds r6, #1 8005b00: e7af b.n 8005a62 <_vfiprintf_r+0x72> 8005b02: 9b05 ldr r3, [sp, #20] 8005b04: 6822 ldr r2, [r4, #0] 8005b06: 1ac0 subs r0, r0, r3 8005b08: 2301 movs r3, #1 8005b0a: 4083 lsls r3, r0 8005b0c: 4313 orrs r3, r2 8005b0e: 0035 movs r5, r6 8005b10: 6023 str r3, [r4, #0] 8005b12: e7cc b.n 8005aae <_vfiprintf_r+0xbe> 8005b14: 9b07 ldr r3, [sp, #28] 8005b16: 1d19 adds r1, r3, #4 8005b18: 681b ldr r3, [r3, #0] 8005b1a: 9107 str r1, [sp, #28] 8005b1c: 2b00 cmp r3, #0 8005b1e: db01 blt.n 8005b24 <_vfiprintf_r+0x134> 8005b20: 930b str r3, [sp, #44] @ 0x2c 8005b22: e004 b.n 8005b2e <_vfiprintf_r+0x13e> 8005b24: 425b negs r3, r3 8005b26: 60e3 str r3, [r4, #12] 8005b28: 2302 movs r3, #2 8005b2a: 4313 orrs r3, r2 8005b2c: 6023 str r3, [r4, #0] 8005b2e: 7833 ldrb r3, [r6, #0] 8005b30: 2b2e cmp r3, #46 @ 0x2e 8005b32: d10c bne.n 8005b4e <_vfiprintf_r+0x15e> 8005b34: 7873 ldrb r3, [r6, #1] 8005b36: 2b2a cmp r3, #42 @ 0x2a 8005b38: d134 bne.n 8005ba4 <_vfiprintf_r+0x1b4> 8005b3a: 9b07 ldr r3, [sp, #28] 8005b3c: 3602 adds r6, #2 8005b3e: 1d1a adds r2, r3, #4 8005b40: 681b ldr r3, [r3, #0] 8005b42: 9207 str r2, [sp, #28] 8005b44: 2b00 cmp r3, #0 8005b46: da01 bge.n 8005b4c <_vfiprintf_r+0x15c> 8005b48: 2301 movs r3, #1 8005b4a: 425b negs r3, r3 8005b4c: 9309 str r3, [sp, #36] @ 0x24 8005b4e: 4d32 ldr r5, [pc, #200] @ (8005c18 <_vfiprintf_r+0x228>) 8005b50: 2203 movs r2, #3 8005b52: 0028 movs r0, r5 8005b54: 7831 ldrb r1, [r6, #0] 8005b56: f000 fb39 bl 80061cc 8005b5a: 2800 cmp r0, #0 8005b5c: d006 beq.n 8005b6c <_vfiprintf_r+0x17c> 8005b5e: 2340 movs r3, #64 @ 0x40 8005b60: 1b40 subs r0, r0, r5 8005b62: 4083 lsls r3, r0 8005b64: 6822 ldr r2, [r4, #0] 8005b66: 3601 adds r6, #1 8005b68: 4313 orrs r3, r2 8005b6a: 6023 str r3, [r4, #0] 8005b6c: 7831 ldrb r1, [r6, #0] 8005b6e: 2206 movs r2, #6 8005b70: 482a ldr r0, [pc, #168] @ (8005c1c <_vfiprintf_r+0x22c>) 8005b72: 1c75 adds r5, r6, #1 8005b74: 7621 strb r1, [r4, #24] 8005b76: f000 fb29 bl 80061cc 8005b7a: 2800 cmp r0, #0 8005b7c: d040 beq.n 8005c00 <_vfiprintf_r+0x210> 8005b7e: 4b28 ldr r3, [pc, #160] @ (8005c20 <_vfiprintf_r+0x230>) 8005b80: 2b00 cmp r3, #0 8005b82: d122 bne.n 8005bca <_vfiprintf_r+0x1da> 8005b84: 2207 movs r2, #7 8005b86: 9b07 ldr r3, [sp, #28] 8005b88: 3307 adds r3, #7 8005b8a: 4393 bics r3, r2 8005b8c: 3308 adds r3, #8 8005b8e: 9307 str r3, [sp, #28] 8005b90: 6963 ldr r3, [r4, #20] 8005b92: 9a04 ldr r2, [sp, #16] 8005b94: 189b adds r3, r3, r2 8005b96: 6163 str r3, [r4, #20] 8005b98: e762 b.n 8005a60 <_vfiprintf_r+0x70> 8005b9a: 4343 muls r3, r0 8005b9c: 002e movs r6, r5 8005b9e: 2101 movs r1, #1 8005ba0: 189b adds r3, r3, r2 8005ba2: e7a4 b.n 8005aee <_vfiprintf_r+0xfe> 8005ba4: 2300 movs r3, #0 8005ba6: 200a movs r0, #10 8005ba8: 0019 movs r1, r3 8005baa: 3601 adds r6, #1 8005bac: 6063 str r3, [r4, #4] 8005bae: 7832 ldrb r2, [r6, #0] 8005bb0: 1c75 adds r5, r6, #1 8005bb2: 3a30 subs r2, #48 @ 0x30 8005bb4: 2a09 cmp r2, #9 8005bb6: d903 bls.n 8005bc0 <_vfiprintf_r+0x1d0> 8005bb8: 2b00 cmp r3, #0 8005bba: d0c8 beq.n 8005b4e <_vfiprintf_r+0x15e> 8005bbc: 9109 str r1, [sp, #36] @ 0x24 8005bbe: e7c6 b.n 8005b4e <_vfiprintf_r+0x15e> 8005bc0: 4341 muls r1, r0 8005bc2: 002e movs r6, r5 8005bc4: 2301 movs r3, #1 8005bc6: 1889 adds r1, r1, r2 8005bc8: e7f1 b.n 8005bae <_vfiprintf_r+0x1be> 8005bca: aa07 add r2, sp, #28 8005bcc: 9200 str r2, [sp, #0] 8005bce: 0021 movs r1, r4 8005bd0: 003a movs r2, r7 8005bd2: 4b14 ldr r3, [pc, #80] @ (8005c24 <_vfiprintf_r+0x234>) 8005bd4: 9803 ldr r0, [sp, #12] 8005bd6: e000 b.n 8005bda <_vfiprintf_r+0x1ea> 8005bd8: bf00 nop 8005bda: 9004 str r0, [sp, #16] 8005bdc: 9b04 ldr r3, [sp, #16] 8005bde: 3301 adds r3, #1 8005be0: d1d6 bne.n 8005b90 <_vfiprintf_r+0x1a0> 8005be2: 6e7b ldr r3, [r7, #100] @ 0x64 8005be4: 07db lsls r3, r3, #31 8005be6: d405 bmi.n 8005bf4 <_vfiprintf_r+0x204> 8005be8: 89bb ldrh r3, [r7, #12] 8005bea: 059b lsls r3, r3, #22 8005bec: d402 bmi.n 8005bf4 <_vfiprintf_r+0x204> 8005bee: 6db8 ldr r0, [r7, #88] @ 0x58 8005bf0: f7ff fdd8 bl 80057a4 <__retarget_lock_release_recursive> 8005bf4: 89bb ldrh r3, [r7, #12] 8005bf6: 065b lsls r3, r3, #25 8005bf8: d500 bpl.n 8005bfc <_vfiprintf_r+0x20c> 8005bfa: e71e b.n 8005a3a <_vfiprintf_r+0x4a> 8005bfc: 980d ldr r0, [sp, #52] @ 0x34 8005bfe: e71e b.n 8005a3e <_vfiprintf_r+0x4e> 8005c00: aa07 add r2, sp, #28 8005c02: 9200 str r2, [sp, #0] 8005c04: 0021 movs r1, r4 8005c06: 003a movs r2, r7 8005c08: 4b06 ldr r3, [pc, #24] @ (8005c24 <_vfiprintf_r+0x234>) 8005c0a: 9803 ldr r0, [sp, #12] 8005c0c: f000 f87c bl 8005d08 <_printf_i> 8005c10: e7e3 b.n 8005bda <_vfiprintf_r+0x1ea> 8005c12: 46c0 nop @ (mov r8, r8) 8005c14: 080062c8 .word 0x080062c8 8005c18: 080062ce .word 0x080062ce 8005c1c: 080062d2 .word 0x080062d2 8005c20: 00000000 .word 0x00000000 8005c24: 080059cb .word 0x080059cb 08005c28 <_printf_common>: 8005c28: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8005c2a: 0016 movs r6, r2 8005c2c: 9301 str r3, [sp, #4] 8005c2e: 688a ldr r2, [r1, #8] 8005c30: 690b ldr r3, [r1, #16] 8005c32: 000c movs r4, r1 8005c34: 9000 str r0, [sp, #0] 8005c36: 4293 cmp r3, r2 8005c38: da00 bge.n 8005c3c <_printf_common+0x14> 8005c3a: 0013 movs r3, r2 8005c3c: 0022 movs r2, r4 8005c3e: 6033 str r3, [r6, #0] 8005c40: 3243 adds r2, #67 @ 0x43 8005c42: 7812 ldrb r2, [r2, #0] 8005c44: 2a00 cmp r2, #0 8005c46: d001 beq.n 8005c4c <_printf_common+0x24> 8005c48: 3301 adds r3, #1 8005c4a: 6033 str r3, [r6, #0] 8005c4c: 6823 ldr r3, [r4, #0] 8005c4e: 069b lsls r3, r3, #26 8005c50: d502 bpl.n 8005c58 <_printf_common+0x30> 8005c52: 6833 ldr r3, [r6, #0] 8005c54: 3302 adds r3, #2 8005c56: 6033 str r3, [r6, #0] 8005c58: 6822 ldr r2, [r4, #0] 8005c5a: 2306 movs r3, #6 8005c5c: 0015 movs r5, r2 8005c5e: 401d ands r5, r3 8005c60: 421a tst r2, r3 8005c62: d027 beq.n 8005cb4 <_printf_common+0x8c> 8005c64: 0023 movs r3, r4 8005c66: 3343 adds r3, #67 @ 0x43 8005c68: 781b ldrb r3, [r3, #0] 8005c6a: 1e5a subs r2, r3, #1 8005c6c: 4193 sbcs r3, r2 8005c6e: 6822 ldr r2, [r4, #0] 8005c70: 0692 lsls r2, r2, #26 8005c72: d430 bmi.n 8005cd6 <_printf_common+0xae> 8005c74: 0022 movs r2, r4 8005c76: 9901 ldr r1, [sp, #4] 8005c78: 9800 ldr r0, [sp, #0] 8005c7a: 9d08 ldr r5, [sp, #32] 8005c7c: 3243 adds r2, #67 @ 0x43 8005c7e: 47a8 blx r5 8005c80: 3001 adds r0, #1 8005c82: d025 beq.n 8005cd0 <_printf_common+0xa8> 8005c84: 2206 movs r2, #6 8005c86: 6823 ldr r3, [r4, #0] 8005c88: 2500 movs r5, #0 8005c8a: 4013 ands r3, r2 8005c8c: 2b04 cmp r3, #4 8005c8e: d105 bne.n 8005c9c <_printf_common+0x74> 8005c90: 6833 ldr r3, [r6, #0] 8005c92: 68e5 ldr r5, [r4, #12] 8005c94: 1aed subs r5, r5, r3 8005c96: 43eb mvns r3, r5 8005c98: 17db asrs r3, r3, #31 8005c9a: 401d ands r5, r3 8005c9c: 68a3 ldr r3, [r4, #8] 8005c9e: 6922 ldr r2, [r4, #16] 8005ca0: 4293 cmp r3, r2 8005ca2: dd01 ble.n 8005ca8 <_printf_common+0x80> 8005ca4: 1a9b subs r3, r3, r2 8005ca6: 18ed adds r5, r5, r3 8005ca8: 2600 movs r6, #0 8005caa: 42b5 cmp r5, r6 8005cac: d120 bne.n 8005cf0 <_printf_common+0xc8> 8005cae: 2000 movs r0, #0 8005cb0: e010 b.n 8005cd4 <_printf_common+0xac> 8005cb2: 3501 adds r5, #1 8005cb4: 68e3 ldr r3, [r4, #12] 8005cb6: 6832 ldr r2, [r6, #0] 8005cb8: 1a9b subs r3, r3, r2 8005cba: 42ab cmp r3, r5 8005cbc: ddd2 ble.n 8005c64 <_printf_common+0x3c> 8005cbe: 0022 movs r2, r4 8005cc0: 2301 movs r3, #1 8005cc2: 9901 ldr r1, [sp, #4] 8005cc4: 9800 ldr r0, [sp, #0] 8005cc6: 9f08 ldr r7, [sp, #32] 8005cc8: 3219 adds r2, #25 8005cca: 47b8 blx r7 8005ccc: 3001 adds r0, #1 8005cce: d1f0 bne.n 8005cb2 <_printf_common+0x8a> 8005cd0: 2001 movs r0, #1 8005cd2: 4240 negs r0, r0 8005cd4: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8005cd6: 2030 movs r0, #48 @ 0x30 8005cd8: 18e1 adds r1, r4, r3 8005cda: 3143 adds r1, #67 @ 0x43 8005cdc: 7008 strb r0, [r1, #0] 8005cde: 0021 movs r1, r4 8005ce0: 1c5a adds r2, r3, #1 8005ce2: 3145 adds r1, #69 @ 0x45 8005ce4: 7809 ldrb r1, [r1, #0] 8005ce6: 18a2 adds r2, r4, r2 8005ce8: 3243 adds r2, #67 @ 0x43 8005cea: 3302 adds r3, #2 8005cec: 7011 strb r1, [r2, #0] 8005cee: e7c1 b.n 8005c74 <_printf_common+0x4c> 8005cf0: 0022 movs r2, r4 8005cf2: 2301 movs r3, #1 8005cf4: 9901 ldr r1, [sp, #4] 8005cf6: 9800 ldr r0, [sp, #0] 8005cf8: 9f08 ldr r7, [sp, #32] 8005cfa: 321a adds r2, #26 8005cfc: 47b8 blx r7 8005cfe: 3001 adds r0, #1 8005d00: d0e6 beq.n 8005cd0 <_printf_common+0xa8> 8005d02: 3601 adds r6, #1 8005d04: e7d1 b.n 8005caa <_printf_common+0x82> ... 08005d08 <_printf_i>: 8005d08: b5f0 push {r4, r5, r6, r7, lr} 8005d0a: b08b sub sp, #44 @ 0x2c 8005d0c: 9206 str r2, [sp, #24] 8005d0e: 000a movs r2, r1 8005d10: 3243 adds r2, #67 @ 0x43 8005d12: 9307 str r3, [sp, #28] 8005d14: 9005 str r0, [sp, #20] 8005d16: 9203 str r2, [sp, #12] 8005d18: 7e0a ldrb r2, [r1, #24] 8005d1a: 000c movs r4, r1 8005d1c: 9b10 ldr r3, [sp, #64] @ 0x40 8005d1e: 2a78 cmp r2, #120 @ 0x78 8005d20: d809 bhi.n 8005d36 <_printf_i+0x2e> 8005d22: 2a62 cmp r2, #98 @ 0x62 8005d24: d80b bhi.n 8005d3e <_printf_i+0x36> 8005d26: 2a00 cmp r2, #0 8005d28: d100 bne.n 8005d2c <_printf_i+0x24> 8005d2a: e0bc b.n 8005ea6 <_printf_i+0x19e> 8005d2c: 497b ldr r1, [pc, #492] @ (8005f1c <_printf_i+0x214>) 8005d2e: 9104 str r1, [sp, #16] 8005d30: 2a58 cmp r2, #88 @ 0x58 8005d32: d100 bne.n 8005d36 <_printf_i+0x2e> 8005d34: e090 b.n 8005e58 <_printf_i+0x150> 8005d36: 0025 movs r5, r4 8005d38: 3542 adds r5, #66 @ 0x42 8005d3a: 702a strb r2, [r5, #0] 8005d3c: e022 b.n 8005d84 <_printf_i+0x7c> 8005d3e: 0010 movs r0, r2 8005d40: 3863 subs r0, #99 @ 0x63 8005d42: 2815 cmp r0, #21 8005d44: d8f7 bhi.n 8005d36 <_printf_i+0x2e> 8005d46: f7fa f9db bl 8000100 <__gnu_thumb1_case_shi> 8005d4a: 0016 .short 0x0016 8005d4c: fff6001f .word 0xfff6001f 8005d50: fff6fff6 .word 0xfff6fff6 8005d54: 001ffff6 .word 0x001ffff6 8005d58: fff6fff6 .word 0xfff6fff6 8005d5c: fff6fff6 .word 0xfff6fff6 8005d60: 003600a1 .word 0x003600a1 8005d64: fff60080 .word 0xfff60080 8005d68: 00b2fff6 .word 0x00b2fff6 8005d6c: 0036fff6 .word 0x0036fff6 8005d70: fff6fff6 .word 0xfff6fff6 8005d74: 0084 .short 0x0084 8005d76: 0025 movs r5, r4 8005d78: 681a ldr r2, [r3, #0] 8005d7a: 3542 adds r5, #66 @ 0x42 8005d7c: 1d11 adds r1, r2, #4 8005d7e: 6019 str r1, [r3, #0] 8005d80: 6813 ldr r3, [r2, #0] 8005d82: 702b strb r3, [r5, #0] 8005d84: 2301 movs r3, #1 8005d86: e0a0 b.n 8005eca <_printf_i+0x1c2> 8005d88: 6818 ldr r0, [r3, #0] 8005d8a: 6809 ldr r1, [r1, #0] 8005d8c: 1d02 adds r2, r0, #4 8005d8e: 060d lsls r5, r1, #24 8005d90: d50b bpl.n 8005daa <_printf_i+0xa2> 8005d92: 6806 ldr r6, [r0, #0] 8005d94: 601a str r2, [r3, #0] 8005d96: 2e00 cmp r6, #0 8005d98: da03 bge.n 8005da2 <_printf_i+0x9a> 8005d9a: 232d movs r3, #45 @ 0x2d 8005d9c: 9a03 ldr r2, [sp, #12] 8005d9e: 4276 negs r6, r6 8005da0: 7013 strb r3, [r2, #0] 8005da2: 4b5e ldr r3, [pc, #376] @ (8005f1c <_printf_i+0x214>) 8005da4: 270a movs r7, #10 8005da6: 9304 str r3, [sp, #16] 8005da8: e018 b.n 8005ddc <_printf_i+0xd4> 8005daa: 6806 ldr r6, [r0, #0] 8005dac: 601a str r2, [r3, #0] 8005dae: 0649 lsls r1, r1, #25 8005db0: d5f1 bpl.n 8005d96 <_printf_i+0x8e> 8005db2: b236 sxth r6, r6 8005db4: e7ef b.n 8005d96 <_printf_i+0x8e> 8005db6: 6808 ldr r0, [r1, #0] 8005db8: 6819 ldr r1, [r3, #0] 8005dba: c940 ldmia r1!, {r6} 8005dbc: 0605 lsls r5, r0, #24 8005dbe: d402 bmi.n 8005dc6 <_printf_i+0xbe> 8005dc0: 0640 lsls r0, r0, #25 8005dc2: d500 bpl.n 8005dc6 <_printf_i+0xbe> 8005dc4: b2b6 uxth r6, r6 8005dc6: 6019 str r1, [r3, #0] 8005dc8: 4b54 ldr r3, [pc, #336] @ (8005f1c <_printf_i+0x214>) 8005dca: 270a movs r7, #10 8005dcc: 9304 str r3, [sp, #16] 8005dce: 2a6f cmp r2, #111 @ 0x6f 8005dd0: d100 bne.n 8005dd4 <_printf_i+0xcc> 8005dd2: 3f02 subs r7, #2 8005dd4: 0023 movs r3, r4 8005dd6: 2200 movs r2, #0 8005dd8: 3343 adds r3, #67 @ 0x43 8005dda: 701a strb r2, [r3, #0] 8005ddc: 6863 ldr r3, [r4, #4] 8005dde: 60a3 str r3, [r4, #8] 8005de0: 2b00 cmp r3, #0 8005de2: db03 blt.n 8005dec <_printf_i+0xe4> 8005de4: 2104 movs r1, #4 8005de6: 6822 ldr r2, [r4, #0] 8005de8: 438a bics r2, r1 8005dea: 6022 str r2, [r4, #0] 8005dec: 2e00 cmp r6, #0 8005dee: d102 bne.n 8005df6 <_printf_i+0xee> 8005df0: 9d03 ldr r5, [sp, #12] 8005df2: 2b00 cmp r3, #0 8005df4: d00c beq.n 8005e10 <_printf_i+0x108> 8005df6: 9d03 ldr r5, [sp, #12] 8005df8: 0030 movs r0, r6 8005dfa: 0039 movs r1, r7 8005dfc: f7fa fa10 bl 8000220 <__aeabi_uidivmod> 8005e00: 9b04 ldr r3, [sp, #16] 8005e02: 3d01 subs r5, #1 8005e04: 5c5b ldrb r3, [r3, r1] 8005e06: 702b strb r3, [r5, #0] 8005e08: 0033 movs r3, r6 8005e0a: 0006 movs r6, r0 8005e0c: 429f cmp r7, r3 8005e0e: d9f3 bls.n 8005df8 <_printf_i+0xf0> 8005e10: 2f08 cmp r7, #8 8005e12: d109 bne.n 8005e28 <_printf_i+0x120> 8005e14: 6823 ldr r3, [r4, #0] 8005e16: 07db lsls r3, r3, #31 8005e18: d506 bpl.n 8005e28 <_printf_i+0x120> 8005e1a: 6862 ldr r2, [r4, #4] 8005e1c: 6923 ldr r3, [r4, #16] 8005e1e: 429a cmp r2, r3 8005e20: dc02 bgt.n 8005e28 <_printf_i+0x120> 8005e22: 2330 movs r3, #48 @ 0x30 8005e24: 3d01 subs r5, #1 8005e26: 702b strb r3, [r5, #0] 8005e28: 9b03 ldr r3, [sp, #12] 8005e2a: 1b5b subs r3, r3, r5 8005e2c: 6123 str r3, [r4, #16] 8005e2e: 9b07 ldr r3, [sp, #28] 8005e30: 0021 movs r1, r4 8005e32: 9300 str r3, [sp, #0] 8005e34: 9805 ldr r0, [sp, #20] 8005e36: 9b06 ldr r3, [sp, #24] 8005e38: aa09 add r2, sp, #36 @ 0x24 8005e3a: f7ff fef5 bl 8005c28 <_printf_common> 8005e3e: 3001 adds r0, #1 8005e40: d148 bne.n 8005ed4 <_printf_i+0x1cc> 8005e42: 2001 movs r0, #1 8005e44: 4240 negs r0, r0 8005e46: b00b add sp, #44 @ 0x2c 8005e48: bdf0 pop {r4, r5, r6, r7, pc} 8005e4a: 2220 movs r2, #32 8005e4c: 6809 ldr r1, [r1, #0] 8005e4e: 430a orrs r2, r1 8005e50: 6022 str r2, [r4, #0] 8005e52: 2278 movs r2, #120 @ 0x78 8005e54: 4932 ldr r1, [pc, #200] @ (8005f20 <_printf_i+0x218>) 8005e56: 9104 str r1, [sp, #16] 8005e58: 0021 movs r1, r4 8005e5a: 3145 adds r1, #69 @ 0x45 8005e5c: 700a strb r2, [r1, #0] 8005e5e: 6819 ldr r1, [r3, #0] 8005e60: 6822 ldr r2, [r4, #0] 8005e62: c940 ldmia r1!, {r6} 8005e64: 0610 lsls r0, r2, #24 8005e66: d402 bmi.n 8005e6e <_printf_i+0x166> 8005e68: 0650 lsls r0, r2, #25 8005e6a: d500 bpl.n 8005e6e <_printf_i+0x166> 8005e6c: b2b6 uxth r6, r6 8005e6e: 6019 str r1, [r3, #0] 8005e70: 07d3 lsls r3, r2, #31 8005e72: d502 bpl.n 8005e7a <_printf_i+0x172> 8005e74: 2320 movs r3, #32 8005e76: 4313 orrs r3, r2 8005e78: 6023 str r3, [r4, #0] 8005e7a: 2e00 cmp r6, #0 8005e7c: d001 beq.n 8005e82 <_printf_i+0x17a> 8005e7e: 2710 movs r7, #16 8005e80: e7a8 b.n 8005dd4 <_printf_i+0xcc> 8005e82: 2220 movs r2, #32 8005e84: 6823 ldr r3, [r4, #0] 8005e86: 4393 bics r3, r2 8005e88: 6023 str r3, [r4, #0] 8005e8a: e7f8 b.n 8005e7e <_printf_i+0x176> 8005e8c: 681a ldr r2, [r3, #0] 8005e8e: 680d ldr r5, [r1, #0] 8005e90: 1d10 adds r0, r2, #4 8005e92: 6949 ldr r1, [r1, #20] 8005e94: 6018 str r0, [r3, #0] 8005e96: 6813 ldr r3, [r2, #0] 8005e98: 062e lsls r6, r5, #24 8005e9a: d501 bpl.n 8005ea0 <_printf_i+0x198> 8005e9c: 6019 str r1, [r3, #0] 8005e9e: e002 b.n 8005ea6 <_printf_i+0x19e> 8005ea0: 066d lsls r5, r5, #25 8005ea2: d5fb bpl.n 8005e9c <_printf_i+0x194> 8005ea4: 8019 strh r1, [r3, #0] 8005ea6: 2300 movs r3, #0 8005ea8: 9d03 ldr r5, [sp, #12] 8005eaa: 6123 str r3, [r4, #16] 8005eac: e7bf b.n 8005e2e <_printf_i+0x126> 8005eae: 681a ldr r2, [r3, #0] 8005eb0: 1d11 adds r1, r2, #4 8005eb2: 6019 str r1, [r3, #0] 8005eb4: 6815 ldr r5, [r2, #0] 8005eb6: 2100 movs r1, #0 8005eb8: 0028 movs r0, r5 8005eba: 6862 ldr r2, [r4, #4] 8005ebc: f000 f986 bl 80061cc 8005ec0: 2800 cmp r0, #0 8005ec2: d001 beq.n 8005ec8 <_printf_i+0x1c0> 8005ec4: 1b40 subs r0, r0, r5 8005ec6: 6060 str r0, [r4, #4] 8005ec8: 6863 ldr r3, [r4, #4] 8005eca: 6123 str r3, [r4, #16] 8005ecc: 2300 movs r3, #0 8005ece: 9a03 ldr r2, [sp, #12] 8005ed0: 7013 strb r3, [r2, #0] 8005ed2: e7ac b.n 8005e2e <_printf_i+0x126> 8005ed4: 002a movs r2, r5 8005ed6: 6923 ldr r3, [r4, #16] 8005ed8: 9906 ldr r1, [sp, #24] 8005eda: 9805 ldr r0, [sp, #20] 8005edc: 9d07 ldr r5, [sp, #28] 8005ede: 47a8 blx r5 8005ee0: 3001 adds r0, #1 8005ee2: d0ae beq.n 8005e42 <_printf_i+0x13a> 8005ee4: 6823 ldr r3, [r4, #0] 8005ee6: 079b lsls r3, r3, #30 8005ee8: d415 bmi.n 8005f16 <_printf_i+0x20e> 8005eea: 9b09 ldr r3, [sp, #36] @ 0x24 8005eec: 68e0 ldr r0, [r4, #12] 8005eee: 4298 cmp r0, r3 8005ef0: daa9 bge.n 8005e46 <_printf_i+0x13e> 8005ef2: 0018 movs r0, r3 8005ef4: e7a7 b.n 8005e46 <_printf_i+0x13e> 8005ef6: 0022 movs r2, r4 8005ef8: 2301 movs r3, #1 8005efa: 9906 ldr r1, [sp, #24] 8005efc: 9805 ldr r0, [sp, #20] 8005efe: 9e07 ldr r6, [sp, #28] 8005f00: 3219 adds r2, #25 8005f02: 47b0 blx r6 8005f04: 3001 adds r0, #1 8005f06: d09c beq.n 8005e42 <_printf_i+0x13a> 8005f08: 3501 adds r5, #1 8005f0a: 68e3 ldr r3, [r4, #12] 8005f0c: 9a09 ldr r2, [sp, #36] @ 0x24 8005f0e: 1a9b subs r3, r3, r2 8005f10: 42ab cmp r3, r5 8005f12: dcf0 bgt.n 8005ef6 <_printf_i+0x1ee> 8005f14: e7e9 b.n 8005eea <_printf_i+0x1e2> 8005f16: 2500 movs r5, #0 8005f18: e7f7 b.n 8005f0a <_printf_i+0x202> 8005f1a: 46c0 nop @ (mov r8, r8) 8005f1c: 080062d9 .word 0x080062d9 8005f20: 080062ea .word 0x080062ea 08005f24 <__sflush_r>: 8005f24: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8005f26: 220c movs r2, #12 8005f28: 5e8b ldrsh r3, [r1, r2] 8005f2a: 0005 movs r5, r0 8005f2c: 000c movs r4, r1 8005f2e: 071a lsls r2, r3, #28 8005f30: d456 bmi.n 8005fe0 <__sflush_r+0xbc> 8005f32: 684a ldr r2, [r1, #4] 8005f34: 2a00 cmp r2, #0 8005f36: dc02 bgt.n 8005f3e <__sflush_r+0x1a> 8005f38: 6c0a ldr r2, [r1, #64] @ 0x40 8005f3a: 2a00 cmp r2, #0 8005f3c: dd4e ble.n 8005fdc <__sflush_r+0xb8> 8005f3e: 6ae7 ldr r7, [r4, #44] @ 0x2c 8005f40: 2f00 cmp r7, #0 8005f42: d04b beq.n 8005fdc <__sflush_r+0xb8> 8005f44: 2200 movs r2, #0 8005f46: 2080 movs r0, #128 @ 0x80 8005f48: 682e ldr r6, [r5, #0] 8005f4a: 602a str r2, [r5, #0] 8005f4c: 001a movs r2, r3 8005f4e: 0140 lsls r0, r0, #5 8005f50: 6a21 ldr r1, [r4, #32] 8005f52: 4002 ands r2, r0 8005f54: 4203 tst r3, r0 8005f56: d033 beq.n 8005fc0 <__sflush_r+0x9c> 8005f58: 6d62 ldr r2, [r4, #84] @ 0x54 8005f5a: 89a3 ldrh r3, [r4, #12] 8005f5c: 075b lsls r3, r3, #29 8005f5e: d506 bpl.n 8005f6e <__sflush_r+0x4a> 8005f60: 6863 ldr r3, [r4, #4] 8005f62: 1ad2 subs r2, r2, r3 8005f64: 6b63 ldr r3, [r4, #52] @ 0x34 8005f66: 2b00 cmp r3, #0 8005f68: d001 beq.n 8005f6e <__sflush_r+0x4a> 8005f6a: 6c23 ldr r3, [r4, #64] @ 0x40 8005f6c: 1ad2 subs r2, r2, r3 8005f6e: 2300 movs r3, #0 8005f70: 0028 movs r0, r5 8005f72: 6ae7 ldr r7, [r4, #44] @ 0x2c 8005f74: 6a21 ldr r1, [r4, #32] 8005f76: 47b8 blx r7 8005f78: 89a2 ldrh r2, [r4, #12] 8005f7a: 1c43 adds r3, r0, #1 8005f7c: d106 bne.n 8005f8c <__sflush_r+0x68> 8005f7e: 6829 ldr r1, [r5, #0] 8005f80: 291d cmp r1, #29 8005f82: d846 bhi.n 8006012 <__sflush_r+0xee> 8005f84: 4b29 ldr r3, [pc, #164] @ (800602c <__sflush_r+0x108>) 8005f86: 410b asrs r3, r1 8005f88: 07db lsls r3, r3, #31 8005f8a: d442 bmi.n 8006012 <__sflush_r+0xee> 8005f8c: 2300 movs r3, #0 8005f8e: 6063 str r3, [r4, #4] 8005f90: 6923 ldr r3, [r4, #16] 8005f92: 6023 str r3, [r4, #0] 8005f94: 04d2 lsls r2, r2, #19 8005f96: d505 bpl.n 8005fa4 <__sflush_r+0x80> 8005f98: 1c43 adds r3, r0, #1 8005f9a: d102 bne.n 8005fa2 <__sflush_r+0x7e> 8005f9c: 682b ldr r3, [r5, #0] 8005f9e: 2b00 cmp r3, #0 8005fa0: d100 bne.n 8005fa4 <__sflush_r+0x80> 8005fa2: 6560 str r0, [r4, #84] @ 0x54 8005fa4: 6b61 ldr r1, [r4, #52] @ 0x34 8005fa6: 602e str r6, [r5, #0] 8005fa8: 2900 cmp r1, #0 8005faa: d017 beq.n 8005fdc <__sflush_r+0xb8> 8005fac: 0023 movs r3, r4 8005fae: 3344 adds r3, #68 @ 0x44 8005fb0: 4299 cmp r1, r3 8005fb2: d002 beq.n 8005fba <__sflush_r+0x96> 8005fb4: 0028 movs r0, r5 8005fb6: f7ff fbf7 bl 80057a8 <_free_r> 8005fba: 2300 movs r3, #0 8005fbc: 6363 str r3, [r4, #52] @ 0x34 8005fbe: e00d b.n 8005fdc <__sflush_r+0xb8> 8005fc0: 2301 movs r3, #1 8005fc2: 0028 movs r0, r5 8005fc4: 47b8 blx r7 8005fc6: 0002 movs r2, r0 8005fc8: 1c43 adds r3, r0, #1 8005fca: d1c6 bne.n 8005f5a <__sflush_r+0x36> 8005fcc: 682b ldr r3, [r5, #0] 8005fce: 2b00 cmp r3, #0 8005fd0: d0c3 beq.n 8005f5a <__sflush_r+0x36> 8005fd2: 2b1d cmp r3, #29 8005fd4: d001 beq.n 8005fda <__sflush_r+0xb6> 8005fd6: 2b16 cmp r3, #22 8005fd8: d11a bne.n 8006010 <__sflush_r+0xec> 8005fda: 602e str r6, [r5, #0] 8005fdc: 2000 movs r0, #0 8005fde: e01e b.n 800601e <__sflush_r+0xfa> 8005fe0: 690e ldr r6, [r1, #16] 8005fe2: 2e00 cmp r6, #0 8005fe4: d0fa beq.n 8005fdc <__sflush_r+0xb8> 8005fe6: 680f ldr r7, [r1, #0] 8005fe8: 600e str r6, [r1, #0] 8005fea: 1bba subs r2, r7, r6 8005fec: 9201 str r2, [sp, #4] 8005fee: 2200 movs r2, #0 8005ff0: 079b lsls r3, r3, #30 8005ff2: d100 bne.n 8005ff6 <__sflush_r+0xd2> 8005ff4: 694a ldr r2, [r1, #20] 8005ff6: 60a2 str r2, [r4, #8] 8005ff8: 9b01 ldr r3, [sp, #4] 8005ffa: 2b00 cmp r3, #0 8005ffc: ddee ble.n 8005fdc <__sflush_r+0xb8> 8005ffe: 6aa3 ldr r3, [r4, #40] @ 0x28 8006000: 0032 movs r2, r6 8006002: 001f movs r7, r3 8006004: 0028 movs r0, r5 8006006: 9b01 ldr r3, [sp, #4] 8006008: 6a21 ldr r1, [r4, #32] 800600a: 47b8 blx r7 800600c: 2800 cmp r0, #0 800600e: dc07 bgt.n 8006020 <__sflush_r+0xfc> 8006010: 89a2 ldrh r2, [r4, #12] 8006012: 2340 movs r3, #64 @ 0x40 8006014: 2001 movs r0, #1 8006016: 4313 orrs r3, r2 8006018: b21b sxth r3, r3 800601a: 81a3 strh r3, [r4, #12] 800601c: 4240 negs r0, r0 800601e: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} 8006020: 9b01 ldr r3, [sp, #4] 8006022: 1836 adds r6, r6, r0 8006024: 1a1b subs r3, r3, r0 8006026: 9301 str r3, [sp, #4] 8006028: e7e6 b.n 8005ff8 <__sflush_r+0xd4> 800602a: 46c0 nop @ (mov r8, r8) 800602c: dfbffffe .word 0xdfbffffe 08006030 <_fflush_r>: 8006030: 690b ldr r3, [r1, #16] 8006032: b570 push {r4, r5, r6, lr} 8006034: 0005 movs r5, r0 8006036: 000c movs r4, r1 8006038: 2b00 cmp r3, #0 800603a: d102 bne.n 8006042 <_fflush_r+0x12> 800603c: 2500 movs r5, #0 800603e: 0028 movs r0, r5 8006040: bd70 pop {r4, r5, r6, pc} 8006042: 2800 cmp r0, #0 8006044: d004 beq.n 8006050 <_fflush_r+0x20> 8006046: 6a03 ldr r3, [r0, #32] 8006048: 2b00 cmp r3, #0 800604a: d101 bne.n 8006050 <_fflush_r+0x20> 800604c: f7ff f998 bl 8005380 <__sinit> 8006050: 220c movs r2, #12 8006052: 5ea3 ldrsh r3, [r4, r2] 8006054: 2b00 cmp r3, #0 8006056: d0f1 beq.n 800603c <_fflush_r+0xc> 8006058: 6e62 ldr r2, [r4, #100] @ 0x64 800605a: 07d2 lsls r2, r2, #31 800605c: d404 bmi.n 8006068 <_fflush_r+0x38> 800605e: 059b lsls r3, r3, #22 8006060: d402 bmi.n 8006068 <_fflush_r+0x38> 8006062: 6da0 ldr r0, [r4, #88] @ 0x58 8006064: f7ff fb9d bl 80057a2 <__retarget_lock_acquire_recursive> 8006068: 0028 movs r0, r5 800606a: 0021 movs r1, r4 800606c: f7ff ff5a bl 8005f24 <__sflush_r> 8006070: 6e63 ldr r3, [r4, #100] @ 0x64 8006072: 0005 movs r5, r0 8006074: 07db lsls r3, r3, #31 8006076: d4e2 bmi.n 800603e <_fflush_r+0xe> 8006078: 89a3 ldrh r3, [r4, #12] 800607a: 059b lsls r3, r3, #22 800607c: d4df bmi.n 800603e <_fflush_r+0xe> 800607e: 6da0 ldr r0, [r4, #88] @ 0x58 8006080: f7ff fb90 bl 80057a4 <__retarget_lock_release_recursive> 8006084: e7db b.n 800603e <_fflush_r+0xe> ... 08006088 <__swhatbuf_r>: 8006088: b570 push {r4, r5, r6, lr} 800608a: 000e movs r6, r1 800608c: 001d movs r5, r3 800608e: 230e movs r3, #14 8006090: 5ec9 ldrsh r1, [r1, r3] 8006092: 0014 movs r4, r2 8006094: b096 sub sp, #88 @ 0x58 8006096: 2900 cmp r1, #0 8006098: da0c bge.n 80060b4 <__swhatbuf_r+0x2c> 800609a: 89b2 ldrh r2, [r6, #12] 800609c: 2380 movs r3, #128 @ 0x80 800609e: 0011 movs r1, r2 80060a0: 4019 ands r1, r3 80060a2: 421a tst r2, r3 80060a4: d114 bne.n 80060d0 <__swhatbuf_r+0x48> 80060a6: 2380 movs r3, #128 @ 0x80 80060a8: 00db lsls r3, r3, #3 80060aa: 2000 movs r0, #0 80060ac: 6029 str r1, [r5, #0] 80060ae: 6023 str r3, [r4, #0] 80060b0: b016 add sp, #88 @ 0x58 80060b2: bd70 pop {r4, r5, r6, pc} 80060b4: 466a mov r2, sp 80060b6: f000 f853 bl 8006160 <_fstat_r> 80060ba: 2800 cmp r0, #0 80060bc: dbed blt.n 800609a <__swhatbuf_r+0x12> 80060be: 23f0 movs r3, #240 @ 0xf0 80060c0: 9901 ldr r1, [sp, #4] 80060c2: 021b lsls r3, r3, #8 80060c4: 4019 ands r1, r3 80060c6: 4b04 ldr r3, [pc, #16] @ (80060d8 <__swhatbuf_r+0x50>) 80060c8: 18c9 adds r1, r1, r3 80060ca: 424b negs r3, r1 80060cc: 4159 adcs r1, r3 80060ce: e7ea b.n 80060a6 <__swhatbuf_r+0x1e> 80060d0: 2100 movs r1, #0 80060d2: 2340 movs r3, #64 @ 0x40 80060d4: e7e9 b.n 80060aa <__swhatbuf_r+0x22> 80060d6: 46c0 nop @ (mov r8, r8) 80060d8: ffffe000 .word 0xffffe000 080060dc <__smakebuf_r>: 80060dc: b5f0 push {r4, r5, r6, r7, lr} 80060de: 2602 movs r6, #2 80060e0: 898b ldrh r3, [r1, #12] 80060e2: 0005 movs r5, r0 80060e4: 000c movs r4, r1 80060e6: b085 sub sp, #20 80060e8: 4233 tst r3, r6 80060ea: d007 beq.n 80060fc <__smakebuf_r+0x20> 80060ec: 0023 movs r3, r4 80060ee: 3347 adds r3, #71 @ 0x47 80060f0: 6023 str r3, [r4, #0] 80060f2: 6123 str r3, [r4, #16] 80060f4: 2301 movs r3, #1 80060f6: 6163 str r3, [r4, #20] 80060f8: b005 add sp, #20 80060fa: bdf0 pop {r4, r5, r6, r7, pc} 80060fc: ab03 add r3, sp, #12 80060fe: aa02 add r2, sp, #8 8006100: f7ff ffc2 bl 8006088 <__swhatbuf_r> 8006104: 9f02 ldr r7, [sp, #8] 8006106: 9001 str r0, [sp, #4] 8006108: 0039 movs r1, r7 800610a: 0028 movs r0, r5 800610c: f7ff fbb8 bl 8005880 <_malloc_r> 8006110: 2800 cmp r0, #0 8006112: d108 bne.n 8006126 <__smakebuf_r+0x4a> 8006114: 220c movs r2, #12 8006116: 5ea3 ldrsh r3, [r4, r2] 8006118: 059a lsls r2, r3, #22 800611a: d4ed bmi.n 80060f8 <__smakebuf_r+0x1c> 800611c: 2203 movs r2, #3 800611e: 4393 bics r3, r2 8006120: 431e orrs r6, r3 8006122: 81a6 strh r6, [r4, #12] 8006124: e7e2 b.n 80060ec <__smakebuf_r+0x10> 8006126: 2380 movs r3, #128 @ 0x80 8006128: 89a2 ldrh r2, [r4, #12] 800612a: 6020 str r0, [r4, #0] 800612c: 4313 orrs r3, r2 800612e: 81a3 strh r3, [r4, #12] 8006130: 9b03 ldr r3, [sp, #12] 8006132: 6120 str r0, [r4, #16] 8006134: 6167 str r7, [r4, #20] 8006136: 2b00 cmp r3, #0 8006138: d00c beq.n 8006154 <__smakebuf_r+0x78> 800613a: 0028 movs r0, r5 800613c: 230e movs r3, #14 800613e: 5ee1 ldrsh r1, [r4, r3] 8006140: f000 f820 bl 8006184 <_isatty_r> 8006144: 2800 cmp r0, #0 8006146: d005 beq.n 8006154 <__smakebuf_r+0x78> 8006148: 2303 movs r3, #3 800614a: 89a2 ldrh r2, [r4, #12] 800614c: 439a bics r2, r3 800614e: 3b02 subs r3, #2 8006150: 4313 orrs r3, r2 8006152: 81a3 strh r3, [r4, #12] 8006154: 89a3 ldrh r3, [r4, #12] 8006156: 9a01 ldr r2, [sp, #4] 8006158: 4313 orrs r3, r2 800615a: 81a3 strh r3, [r4, #12] 800615c: e7cc b.n 80060f8 <__smakebuf_r+0x1c> ... 08006160 <_fstat_r>: 8006160: 2300 movs r3, #0 8006162: b570 push {r4, r5, r6, lr} 8006164: 4d06 ldr r5, [pc, #24] @ (8006180 <_fstat_r+0x20>) 8006166: 0004 movs r4, r0 8006168: 0008 movs r0, r1 800616a: 0011 movs r1, r2 800616c: 602b str r3, [r5, #0] 800616e: f7fb f978 bl 8001462 <_fstat> 8006172: 1c43 adds r3, r0, #1 8006174: d103 bne.n 800617e <_fstat_r+0x1e> 8006176: 682b ldr r3, [r5, #0] 8006178: 2b00 cmp r3, #0 800617a: d000 beq.n 800617e <_fstat_r+0x1e> 800617c: 6023 str r3, [r4, #0] 800617e: bd70 pop {r4, r5, r6, pc} 8006180: 20000318 .word 0x20000318 08006184 <_isatty_r>: 8006184: 2300 movs r3, #0 8006186: b570 push {r4, r5, r6, lr} 8006188: 4d06 ldr r5, [pc, #24] @ (80061a4 <_isatty_r+0x20>) 800618a: 0004 movs r4, r0 800618c: 0008 movs r0, r1 800618e: 602b str r3, [r5, #0] 8006190: f7fb f975 bl 800147e <_isatty> 8006194: 1c43 adds r3, r0, #1 8006196: d103 bne.n 80061a0 <_isatty_r+0x1c> 8006198: 682b ldr r3, [r5, #0] 800619a: 2b00 cmp r3, #0 800619c: d000 beq.n 80061a0 <_isatty_r+0x1c> 800619e: 6023 str r3, [r4, #0] 80061a0: bd70 pop {r4, r5, r6, pc} 80061a2: 46c0 nop @ (mov r8, r8) 80061a4: 20000318 .word 0x20000318 080061a8 <_sbrk_r>: 80061a8: 2300 movs r3, #0 80061aa: b570 push {r4, r5, r6, lr} 80061ac: 4d06 ldr r5, [pc, #24] @ (80061c8 <_sbrk_r+0x20>) 80061ae: 0004 movs r4, r0 80061b0: 0008 movs r0, r1 80061b2: 602b str r3, [r5, #0] 80061b4: f7fb f978 bl 80014a8 <_sbrk> 80061b8: 1c43 adds r3, r0, #1 80061ba: d103 bne.n 80061c4 <_sbrk_r+0x1c> 80061bc: 682b ldr r3, [r5, #0] 80061be: 2b00 cmp r3, #0 80061c0: d000 beq.n 80061c4 <_sbrk_r+0x1c> 80061c2: 6023 str r3, [r4, #0] 80061c4: bd70 pop {r4, r5, r6, pc} 80061c6: 46c0 nop @ (mov r8, r8) 80061c8: 20000318 .word 0x20000318 080061cc : 80061cc: b2c9 uxtb r1, r1 80061ce: 1882 adds r2, r0, r2 80061d0: 4290 cmp r0, r2 80061d2: d101 bne.n 80061d8 80061d4: 2000 movs r0, #0 80061d6: 4770 bx lr 80061d8: 7803 ldrb r3, [r0, #0] 80061da: 428b cmp r3, r1 80061dc: d0fb beq.n 80061d6 80061de: 3001 adds r0, #1 80061e0: e7f6 b.n 80061d0 ... 080061e4 <_init>: 80061e4: b5f8 push {r3, r4, r5, r6, r7, lr} 80061e6: 46c0 nop @ (mov r8, r8) 80061e8: bcf8 pop {r3, r4, r5, r6, r7} 80061ea: bc08 pop {r3} 80061ec: 469e mov lr, r3 80061ee: 4770 bx lr 080061f0 <_fini>: 80061f0: b5f8 push {r3, r4, r5, r6, r7, lr} 80061f2: 46c0 nop @ (mov r8, r8) 80061f4: bcf8 pop {r3, r4, r5, r6, r7} 80061f6: bc08 pop {r3} 80061f8: 469e mov lr, r3 80061fa: 4770 bx lr