wires.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000b8 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00004aac 080000b8 080000b8 000010b8 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000000ac 08004b64 08004b64 00005b64 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08004c10 08004c10 00006010 2**0 CONTENTS 4 .ARM 00000000 08004c10 08004c10 00006010 2**0 CONTENTS 5 .preinit_array 00000000 08004c10 08004c10 00006010 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08004c10 08004c10 00005c10 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08004c14 08004c14 00005c14 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000010 20000000 08004c18 00006000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 0000012c 20000010 08004c28 00006010 2**2 ALLOC 10 ._user_heap_stack 00000604 2000013c 08004c28 0000613c 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00006010 2**0 CONTENTS, READONLY 12 .debug_info 0000e952 00000000 00000000 00006038 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 0000224a 00000000 00000000 0001498a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000ba8 00000000 00000000 00016bd8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000924 00000000 00000000 00017780 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00015034 00000000 00000000 000180a4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 00010201 00000000 00000000 0002d0d8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00083b0a 00000000 00000000 0003d2d9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000c0de3 2**0 CONTENTS, READONLY 20 .debug_frame 00002940 00000000 00000000 000c0e28 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 00000061 00000000 00000000 000c3768 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000b8 <__do_global_dtors_aux>: 80000b8: b510 push {r4, lr} 80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>) 80000bc: 7823 ldrb r3, [r4, #0] 80000be: 2b00 cmp r3, #0 80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a> 80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>) 80000c4: 2b00 cmp r3, #0 80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16> 80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>) 80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16> 80000cc: bf00 nop 80000ce: 2301 movs r3, #1 80000d0: 7023 strb r3, [r4, #0] 80000d2: bd10 pop {r4, pc} 80000d4: 20000010 .word 0x20000010 80000d8: 00000000 .word 0x00000000 80000dc: 08004b4c .word 0x08004b4c 080000e0 : 80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 ) 80000e2: b510 push {r4, lr} 80000e4: 2b00 cmp r3, #0 80000e6: d003 beq.n 80000f0 80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 ) 80000ea: 4804 ldr r0, [pc, #16] @ (80000fc ) 80000ec: e000 b.n 80000f0 80000ee: bf00 nop 80000f0: bd10 pop {r4, pc} 80000f2: 46c0 nop @ (mov r8, r8) 80000f4: 00000000 .word 0x00000000 80000f8: 20000014 .word 0x20000014 80000fc: 08004b4c .word 0x08004b4c 08000100 <__udivsi3>: 8000100: 2200 movs r2, #0 8000102: 0843 lsrs r3, r0, #1 8000104: 428b cmp r3, r1 8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2> 8000108: 0903 lsrs r3, r0, #4 800010a: 428b cmp r3, r1 800010c: d35f bcc.n 80001ce <__udivsi3+0xce> 800010e: 0a03 lsrs r3, r0, #8 8000110: 428b cmp r3, r1 8000112: d344 bcc.n 800019e <__udivsi3+0x9e> 8000114: 0b03 lsrs r3, r0, #12 8000116: 428b cmp r3, r1 8000118: d328 bcc.n 800016c <__udivsi3+0x6c> 800011a: 0c03 lsrs r3, r0, #16 800011c: 428b cmp r3, r1 800011e: d30d bcc.n 800013c <__udivsi3+0x3c> 8000120: 22ff movs r2, #255 @ 0xff 8000122: 0209 lsls r1, r1, #8 8000124: ba12 rev r2, r2 8000126: 0c03 lsrs r3, r0, #16 8000128: 428b cmp r3, r1 800012a: d302 bcc.n 8000132 <__udivsi3+0x32> 800012c: 1212 asrs r2, r2, #8 800012e: 0209 lsls r1, r1, #8 8000130: d065 beq.n 80001fe <__udivsi3+0xfe> 8000132: 0b03 lsrs r3, r0, #12 8000134: 428b cmp r3, r1 8000136: d319 bcc.n 800016c <__udivsi3+0x6c> 8000138: e000 b.n 800013c <__udivsi3+0x3c> 800013a: 0a09 lsrs r1, r1, #8 800013c: 0bc3 lsrs r3, r0, #15 800013e: 428b cmp r3, r1 8000140: d301 bcc.n 8000146 <__udivsi3+0x46> 8000142: 03cb lsls r3, r1, #15 8000144: 1ac0 subs r0, r0, r3 8000146: 4152 adcs r2, r2 8000148: 0b83 lsrs r3, r0, #14 800014a: 428b cmp r3, r1 800014c: d301 bcc.n 8000152 <__udivsi3+0x52> 800014e: 038b lsls r3, r1, #14 8000150: 1ac0 subs r0, r0, r3 8000152: 4152 adcs r2, r2 8000154: 0b43 lsrs r3, r0, #13 8000156: 428b cmp r3, r1 8000158: d301 bcc.n 800015e <__udivsi3+0x5e> 800015a: 034b lsls r3, r1, #13 800015c: 1ac0 subs r0, r0, r3 800015e: 4152 adcs r2, r2 8000160: 0b03 lsrs r3, r0, #12 8000162: 428b cmp r3, r1 8000164: d301 bcc.n 800016a <__udivsi3+0x6a> 8000166: 030b lsls r3, r1, #12 8000168: 1ac0 subs r0, r0, r3 800016a: 4152 adcs r2, r2 800016c: 0ac3 lsrs r3, r0, #11 800016e: 428b cmp r3, r1 8000170: d301 bcc.n 8000176 <__udivsi3+0x76> 8000172: 02cb lsls r3, r1, #11 8000174: 1ac0 subs r0, r0, r3 8000176: 4152 adcs r2, r2 8000178: 0a83 lsrs r3, r0, #10 800017a: 428b cmp r3, r1 800017c: d301 bcc.n 8000182 <__udivsi3+0x82> 800017e: 028b lsls r3, r1, #10 8000180: 1ac0 subs r0, r0, r3 8000182: 4152 adcs r2, r2 8000184: 0a43 lsrs r3, r0, #9 8000186: 428b cmp r3, r1 8000188: d301 bcc.n 800018e <__udivsi3+0x8e> 800018a: 024b lsls r3, r1, #9 800018c: 1ac0 subs r0, r0, r3 800018e: 4152 adcs r2, r2 8000190: 0a03 lsrs r3, r0, #8 8000192: 428b cmp r3, r1 8000194: d301 bcc.n 800019a <__udivsi3+0x9a> 8000196: 020b lsls r3, r1, #8 8000198: 1ac0 subs r0, r0, r3 800019a: 4152 adcs r2, r2 800019c: d2cd bcs.n 800013a <__udivsi3+0x3a> 800019e: 09c3 lsrs r3, r0, #7 80001a0: 428b cmp r3, r1 80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8> 80001a4: 01cb lsls r3, r1, #7 80001a6: 1ac0 subs r0, r0, r3 80001a8: 4152 adcs r2, r2 80001aa: 0983 lsrs r3, r0, #6 80001ac: 428b cmp r3, r1 80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4> 80001b0: 018b lsls r3, r1, #6 80001b2: 1ac0 subs r0, r0, r3 80001b4: 4152 adcs r2, r2 80001b6: 0943 lsrs r3, r0, #5 80001b8: 428b cmp r3, r1 80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0> 80001bc: 014b lsls r3, r1, #5 80001be: 1ac0 subs r0, r0, r3 80001c0: 4152 adcs r2, r2 80001c2: 0903 lsrs r3, r0, #4 80001c4: 428b cmp r3, r1 80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc> 80001c8: 010b lsls r3, r1, #4 80001ca: 1ac0 subs r0, r0, r3 80001cc: 4152 adcs r2, r2 80001ce: 08c3 lsrs r3, r0, #3 80001d0: 428b cmp r3, r1 80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8> 80001d4: 00cb lsls r3, r1, #3 80001d6: 1ac0 subs r0, r0, r3 80001d8: 4152 adcs r2, r2 80001da: 0883 lsrs r3, r0, #2 80001dc: 428b cmp r3, r1 80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4> 80001e0: 008b lsls r3, r1, #2 80001e2: 1ac0 subs r0, r0, r3 80001e4: 4152 adcs r2, r2 80001e6: 0843 lsrs r3, r0, #1 80001e8: 428b cmp r3, r1 80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0> 80001ec: 004b lsls r3, r1, #1 80001ee: 1ac0 subs r0, r0, r3 80001f0: 4152 adcs r2, r2 80001f2: 1a41 subs r1, r0, r1 80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8> 80001f6: 4601 mov r1, r0 80001f8: 4152 adcs r2, r2 80001fa: 4610 mov r0, r2 80001fc: 4770 bx lr 80001fe: e7ff b.n 8000200 <__udivsi3+0x100> 8000200: b501 push {r0, lr} 8000202: 2000 movs r0, #0 8000204: f000 f8f0 bl 80003e8 <__aeabi_idiv0> 8000208: bd02 pop {r1, pc} 800020a: 46c0 nop @ (mov r8, r8) 0800020c <__aeabi_uidivmod>: 800020c: 2900 cmp r1, #0 800020e: d0f7 beq.n 8000200 <__udivsi3+0x100> 8000210: e776 b.n 8000100 <__udivsi3> 8000212: 4770 bx lr 08000214 <__divsi3>: 8000214: 4603 mov r3, r0 8000216: 430b orrs r3, r1 8000218: d47f bmi.n 800031a <__divsi3+0x106> 800021a: 2200 movs r2, #0 800021c: 0843 lsrs r3, r0, #1 800021e: 428b cmp r3, r1 8000220: d374 bcc.n 800030c <__divsi3+0xf8> 8000222: 0903 lsrs r3, r0, #4 8000224: 428b cmp r3, r1 8000226: d35f bcc.n 80002e8 <__divsi3+0xd4> 8000228: 0a03 lsrs r3, r0, #8 800022a: 428b cmp r3, r1 800022c: d344 bcc.n 80002b8 <__divsi3+0xa4> 800022e: 0b03 lsrs r3, r0, #12 8000230: 428b cmp r3, r1 8000232: d328 bcc.n 8000286 <__divsi3+0x72> 8000234: 0c03 lsrs r3, r0, #16 8000236: 428b cmp r3, r1 8000238: d30d bcc.n 8000256 <__divsi3+0x42> 800023a: 22ff movs r2, #255 @ 0xff 800023c: 0209 lsls r1, r1, #8 800023e: ba12 rev r2, r2 8000240: 0c03 lsrs r3, r0, #16 8000242: 428b cmp r3, r1 8000244: d302 bcc.n 800024c <__divsi3+0x38> 8000246: 1212 asrs r2, r2, #8 8000248: 0209 lsls r1, r1, #8 800024a: d065 beq.n 8000318 <__divsi3+0x104> 800024c: 0b03 lsrs r3, r0, #12 800024e: 428b cmp r3, r1 8000250: d319 bcc.n 8000286 <__divsi3+0x72> 8000252: e000 b.n 8000256 <__divsi3+0x42> 8000254: 0a09 lsrs r1, r1, #8 8000256: 0bc3 lsrs r3, r0, #15 8000258: 428b cmp r3, r1 800025a: d301 bcc.n 8000260 <__divsi3+0x4c> 800025c: 03cb lsls r3, r1, #15 800025e: 1ac0 subs r0, r0, r3 8000260: 4152 adcs r2, r2 8000262: 0b83 lsrs r3, r0, #14 8000264: 428b cmp r3, r1 8000266: d301 bcc.n 800026c <__divsi3+0x58> 8000268: 038b lsls r3, r1, #14 800026a: 1ac0 subs r0, r0, r3 800026c: 4152 adcs r2, r2 800026e: 0b43 lsrs r3, r0, #13 8000270: 428b cmp r3, r1 8000272: d301 bcc.n 8000278 <__divsi3+0x64> 8000274: 034b lsls r3, r1, #13 8000276: 1ac0 subs r0, r0, r3 8000278: 4152 adcs r2, r2 800027a: 0b03 lsrs r3, r0, #12 800027c: 428b cmp r3, r1 800027e: d301 bcc.n 8000284 <__divsi3+0x70> 8000280: 030b lsls r3, r1, #12 8000282: 1ac0 subs r0, r0, r3 8000284: 4152 adcs r2, r2 8000286: 0ac3 lsrs r3, r0, #11 8000288: 428b cmp r3, r1 800028a: d301 bcc.n 8000290 <__divsi3+0x7c> 800028c: 02cb lsls r3, r1, #11 800028e: 1ac0 subs r0, r0, r3 8000290: 4152 adcs r2, r2 8000292: 0a83 lsrs r3, r0, #10 8000294: 428b cmp r3, r1 8000296: d301 bcc.n 800029c <__divsi3+0x88> 8000298: 028b lsls r3, r1, #10 800029a: 1ac0 subs r0, r0, r3 800029c: 4152 adcs r2, r2 800029e: 0a43 lsrs r3, r0, #9 80002a0: 428b cmp r3, r1 80002a2: d301 bcc.n 80002a8 <__divsi3+0x94> 80002a4: 024b lsls r3, r1, #9 80002a6: 1ac0 subs r0, r0, r3 80002a8: 4152 adcs r2, r2 80002aa: 0a03 lsrs r3, r0, #8 80002ac: 428b cmp r3, r1 80002ae: d301 bcc.n 80002b4 <__divsi3+0xa0> 80002b0: 020b lsls r3, r1, #8 80002b2: 1ac0 subs r0, r0, r3 80002b4: 4152 adcs r2, r2 80002b6: d2cd bcs.n 8000254 <__divsi3+0x40> 80002b8: 09c3 lsrs r3, r0, #7 80002ba: 428b cmp r3, r1 80002bc: d301 bcc.n 80002c2 <__divsi3+0xae> 80002be: 01cb lsls r3, r1, #7 80002c0: 1ac0 subs r0, r0, r3 80002c2: 4152 adcs r2, r2 80002c4: 0983 lsrs r3, r0, #6 80002c6: 428b cmp r3, r1 80002c8: d301 bcc.n 80002ce <__divsi3+0xba> 80002ca: 018b lsls r3, r1, #6 80002cc: 1ac0 subs r0, r0, r3 80002ce: 4152 adcs r2, r2 80002d0: 0943 lsrs r3, r0, #5 80002d2: 428b cmp r3, r1 80002d4: d301 bcc.n 80002da <__divsi3+0xc6> 80002d6: 014b lsls r3, r1, #5 80002d8: 1ac0 subs r0, r0, r3 80002da: 4152 adcs r2, r2 80002dc: 0903 lsrs r3, r0, #4 80002de: 428b cmp r3, r1 80002e0: d301 bcc.n 80002e6 <__divsi3+0xd2> 80002e2: 010b lsls r3, r1, #4 80002e4: 1ac0 subs r0, r0, r3 80002e6: 4152 adcs r2, r2 80002e8: 08c3 lsrs r3, r0, #3 80002ea: 428b cmp r3, r1 80002ec: d301 bcc.n 80002f2 <__divsi3+0xde> 80002ee: 00cb lsls r3, r1, #3 80002f0: 1ac0 subs r0, r0, r3 80002f2: 4152 adcs r2, r2 80002f4: 0883 lsrs r3, r0, #2 80002f6: 428b cmp r3, r1 80002f8: d301 bcc.n 80002fe <__divsi3+0xea> 80002fa: 008b lsls r3, r1, #2 80002fc: 1ac0 subs r0, r0, r3 80002fe: 4152 adcs r2, r2 8000300: 0843 lsrs r3, r0, #1 8000302: 428b cmp r3, r1 8000304: d301 bcc.n 800030a <__divsi3+0xf6> 8000306: 004b lsls r3, r1, #1 8000308: 1ac0 subs r0, r0, r3 800030a: 4152 adcs r2, r2 800030c: 1a41 subs r1, r0, r1 800030e: d200 bcs.n 8000312 <__divsi3+0xfe> 8000310: 4601 mov r1, r0 8000312: 4152 adcs r2, r2 8000314: 4610 mov r0, r2 8000316: 4770 bx lr 8000318: e05d b.n 80003d6 <__divsi3+0x1c2> 800031a: 0fca lsrs r2, r1, #31 800031c: d000 beq.n 8000320 <__divsi3+0x10c> 800031e: 4249 negs r1, r1 8000320: 1003 asrs r3, r0, #32 8000322: d300 bcc.n 8000326 <__divsi3+0x112> 8000324: 4240 negs r0, r0 8000326: 4053 eors r3, r2 8000328: 2200 movs r2, #0 800032a: 469c mov ip, r3 800032c: 0903 lsrs r3, r0, #4 800032e: 428b cmp r3, r1 8000330: d32d bcc.n 800038e <__divsi3+0x17a> 8000332: 0a03 lsrs r3, r0, #8 8000334: 428b cmp r3, r1 8000336: d312 bcc.n 800035e <__divsi3+0x14a> 8000338: 22fc movs r2, #252 @ 0xfc 800033a: 0189 lsls r1, r1, #6 800033c: ba12 rev r2, r2 800033e: 0a03 lsrs r3, r0, #8 8000340: 428b cmp r3, r1 8000342: d30c bcc.n 800035e <__divsi3+0x14a> 8000344: 0189 lsls r1, r1, #6 8000346: 1192 asrs r2, r2, #6 8000348: 428b cmp r3, r1 800034a: d308 bcc.n 800035e <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d304 bcc.n 800035e <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: d03a beq.n 80003ce <__divsi3+0x1ba> 8000358: 1192 asrs r2, r2, #6 800035a: e000 b.n 800035e <__divsi3+0x14a> 800035c: 0989 lsrs r1, r1, #6 800035e: 09c3 lsrs r3, r0, #7 8000360: 428b cmp r3, r1 8000362: d301 bcc.n 8000368 <__divsi3+0x154> 8000364: 01cb lsls r3, r1, #7 8000366: 1ac0 subs r0, r0, r3 8000368: 4152 adcs r2, r2 800036a: 0983 lsrs r3, r0, #6 800036c: 428b cmp r3, r1 800036e: d301 bcc.n 8000374 <__divsi3+0x160> 8000370: 018b lsls r3, r1, #6 8000372: 1ac0 subs r0, r0, r3 8000374: 4152 adcs r2, r2 8000376: 0943 lsrs r3, r0, #5 8000378: 428b cmp r3, r1 800037a: d301 bcc.n 8000380 <__divsi3+0x16c> 800037c: 014b lsls r3, r1, #5 800037e: 1ac0 subs r0, r0, r3 8000380: 4152 adcs r2, r2 8000382: 0903 lsrs r3, r0, #4 8000384: 428b cmp r3, r1 8000386: d301 bcc.n 800038c <__divsi3+0x178> 8000388: 010b lsls r3, r1, #4 800038a: 1ac0 subs r0, r0, r3 800038c: 4152 adcs r2, r2 800038e: 08c3 lsrs r3, r0, #3 8000390: 428b cmp r3, r1 8000392: d301 bcc.n 8000398 <__divsi3+0x184> 8000394: 00cb lsls r3, r1, #3 8000396: 1ac0 subs r0, r0, r3 8000398: 4152 adcs r2, r2 800039a: 0883 lsrs r3, r0, #2 800039c: 428b cmp r3, r1 800039e: d301 bcc.n 80003a4 <__divsi3+0x190> 80003a0: 008b lsls r3, r1, #2 80003a2: 1ac0 subs r0, r0, r3 80003a4: 4152 adcs r2, r2 80003a6: d2d9 bcs.n 800035c <__divsi3+0x148> 80003a8: 0843 lsrs r3, r0, #1 80003aa: 428b cmp r3, r1 80003ac: d301 bcc.n 80003b2 <__divsi3+0x19e> 80003ae: 004b lsls r3, r1, #1 80003b0: 1ac0 subs r0, r0, r3 80003b2: 4152 adcs r2, r2 80003b4: 1a41 subs r1, r0, r1 80003b6: d200 bcs.n 80003ba <__divsi3+0x1a6> 80003b8: 4601 mov r1, r0 80003ba: 4663 mov r3, ip 80003bc: 4152 adcs r2, r2 80003be: 105b asrs r3, r3, #1 80003c0: 4610 mov r0, r2 80003c2: d301 bcc.n 80003c8 <__divsi3+0x1b4> 80003c4: 4240 negs r0, r0 80003c6: 2b00 cmp r3, #0 80003c8: d500 bpl.n 80003cc <__divsi3+0x1b8> 80003ca: 4249 negs r1, r1 80003cc: 4770 bx lr 80003ce: 4663 mov r3, ip 80003d0: 105b asrs r3, r3, #1 80003d2: d300 bcc.n 80003d6 <__divsi3+0x1c2> 80003d4: 4240 negs r0, r0 80003d6: b501 push {r0, lr} 80003d8: 2000 movs r0, #0 80003da: f000 f805 bl 80003e8 <__aeabi_idiv0> 80003de: bd02 pop {r1, pc} 080003e0 <__aeabi_idivmod>: 80003e0: 2900 cmp r1, #0 80003e2: d0f8 beq.n 80003d6 <__divsi3+0x1c2> 80003e4: e716 b.n 8000214 <__divsi3> 80003e6: 4770 bx lr 080003e8 <__aeabi_idiv0>: 80003e8: 4770 bx lr 80003ea: 46c0 nop @ (mov r8, r8) 080003ec
: /** * @brief The application entry point. * @retval int */ int main(void) { 80003ec: b580 push {r7, lr} 80003ee: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80003f0: f000 fe4e bl 8001090 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80003f4: f000 f81a bl 800042c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80003f8: f000 f8ee bl 80005d8 MX_I2C1_Init(); 80003fc: f000 f85e bl 80004bc MX_USART2_UART_Init(); 8000400: f000 f89c bl 800053c /* USER CODE BEGIN 2 */ HAL_I2C_EnableListen_IT(&hi2c1); 8000404: 4b08 ldr r3, [pc, #32] @ (8000428 ) 8000406: 0018 movs r0, r3 8000408: f001 fbf8 bl 8001bfc while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ scan_wires(); 800040c: f000 faf0 bl 80009f0 scan_button(); 8000410: f000 fbaa bl 8000b68 handle_strike(); 8000414: f000 fc78 bl 8000d08 set_relay_buzz(); 8000418: f000 fbd2 bl 8000bc0 set_leds(); 800041c: f000 fc0a bl 8000c34 send_interupt(); 8000420: f000 fc52 bl 8000cc8 scan_wires(); 8000424: 46c0 nop @ (mov r8, r8) 8000426: e7f1 b.n 800040c 8000428: 20000030 .word 0x20000030 0800042c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800042c: b590 push {r4, r7, lr} 800042e: b093 sub sp, #76 @ 0x4c 8000430: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000432: 2414 movs r4, #20 8000434: 193b adds r3, r7, r4 8000436: 0018 movs r0, r3 8000438: 2334 movs r3, #52 @ 0x34 800043a: 001a movs r2, r3 800043c: 2100 movs r1, #0 800043e: f004 fb59 bl 8004af4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000442: 1d3b adds r3, r7, #4 8000444: 0018 movs r0, r3 8000446: 2310 movs r3, #16 8000448: 001a movs r2, r3 800044a: 2100 movs r1, #0 800044c: f004 fb52 bl 8004af4 /** Configure the main internal regulator output voltage */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); 8000450: 2380 movs r3, #128 @ 0x80 8000452: 009b lsls r3, r3, #2 8000454: 0018 movs r0, r3 8000456: f002 ffcb bl 80033f0 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800045a: 193b adds r3, r7, r4 800045c: 2202 movs r2, #2 800045e: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000460: 193b adds r3, r7, r4 8000462: 2280 movs r2, #128 @ 0x80 8000464: 0052 lsls r2, r2, #1 8000466: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; 8000468: 193b adds r3, r7, r4 800046a: 2200 movs r2, #0 800046c: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 800046e: 193b adds r3, r7, r4 8000470: 2240 movs r2, #64 @ 0x40 8000472: 615a str r2, [r3, #20] RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8000474: 193b adds r3, r7, r4 8000476: 2200 movs r2, #0 8000478: 61da str r2, [r3, #28] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800047a: 193b adds r3, r7, r4 800047c: 0018 movs r0, r3 800047e: f003 f803 bl 8003488 8000482: 1e03 subs r3, r0, #0 8000484: d001 beq.n 800048a { Error_Handler(); 8000486: f000 fca9 bl 8000ddc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800048a: 1d3b adds r3, r7, #4 800048c: 2207 movs r2, #7 800048e: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 8000490: 1d3b adds r3, r7, #4 8000492: 2200 movs r2, #0 8000494: 605a str r2, [r3, #4] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000496: 1d3b adds r3, r7, #4 8000498: 2200 movs r2, #0 800049a: 609a str r2, [r3, #8] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 800049c: 1d3b adds r3, r7, #4 800049e: 2200 movs r2, #0 80004a0: 60da str r2, [r3, #12] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80004a2: 1d3b adds r3, r7, #4 80004a4: 2100 movs r1, #0 80004a6: 0018 movs r0, r3 80004a8: f003 fafe bl 8003aa8 80004ac: 1e03 subs r3, r0, #0 80004ae: d001 beq.n 80004b4 { Error_Handler(); 80004b0: f000 fc94 bl 8000ddc } } 80004b4: 46c0 nop @ (mov r8, r8) 80004b6: 46bd mov sp, r7 80004b8: b013 add sp, #76 @ 0x4c 80004ba: bd90 pop {r4, r7, pc} 080004bc : * @brief I2C1 Initialization Function * @param None * @retval None */ static void MX_I2C1_Init(void) { 80004bc: b580 push {r7, lr} 80004be: af00 add r7, sp, #0 /* USER CODE END I2C1_Init 0 */ /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ hi2c1.Instance = I2C1; 80004c0: 4b1b ldr r3, [pc, #108] @ (8000530 ) 80004c2: 4a1c ldr r2, [pc, #112] @ (8000534 ) 80004c4: 601a str r2, [r3, #0] hi2c1.Init.Timing = 0x00303D5B; 80004c6: 4b1a ldr r3, [pc, #104] @ (8000530 ) 80004c8: 4a1b ldr r2, [pc, #108] @ (8000538 ) 80004ca: 605a str r2, [r3, #4] hi2c1.Init.OwnAddress1 = 250; 80004cc: 4b18 ldr r3, [pc, #96] @ (8000530 ) 80004ce: 22fa movs r2, #250 @ 0xfa 80004d0: 609a str r2, [r3, #8] hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80004d2: 4b17 ldr r3, [pc, #92] @ (8000530 ) 80004d4: 2201 movs r2, #1 80004d6: 60da str r2, [r3, #12] hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80004d8: 4b15 ldr r3, [pc, #84] @ (8000530 ) 80004da: 2200 movs r2, #0 80004dc: 611a str r2, [r3, #16] hi2c1.Init.OwnAddress2 = 0; 80004de: 4b14 ldr r3, [pc, #80] @ (8000530 ) 80004e0: 2200 movs r2, #0 80004e2: 615a str r2, [r3, #20] hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; 80004e4: 4b12 ldr r3, [pc, #72] @ (8000530 ) 80004e6: 2200 movs r2, #0 80004e8: 619a str r2, [r3, #24] hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80004ea: 4b11 ldr r3, [pc, #68] @ (8000530 ) 80004ec: 2200 movs r2, #0 80004ee: 61da str r2, [r3, #28] hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 80004f0: 4b0f ldr r3, [pc, #60] @ (8000530 ) 80004f2: 2200 movs r2, #0 80004f4: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c1) != HAL_OK) 80004f6: 4b0e ldr r3, [pc, #56] @ (8000530 ) 80004f8: 0018 movs r0, r3 80004fa: f001 f957 bl 80017ac 80004fe: 1e03 subs r3, r0, #0 8000500: d001 beq.n 8000506 { Error_Handler(); 8000502: f000 fc6b bl 8000ddc } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000506: 4b0a ldr r3, [pc, #40] @ (8000530 ) 8000508: 2100 movs r1, #0 800050a: 0018 movs r0, r3 800050c: f002 fed8 bl 80032c0 8000510: 1e03 subs r3, r0, #0 8000512: d001 beq.n 8000518 { Error_Handler(); 8000514: f000 fc62 bl 8000ddc } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) 8000518: 4b05 ldr r3, [pc, #20] @ (8000530 ) 800051a: 2100 movs r1, #0 800051c: 0018 movs r0, r3 800051e: f002 ff1b bl 8003358 8000522: 1e03 subs r3, r0, #0 8000524: d001 beq.n 800052a { Error_Handler(); 8000526: f000 fc59 bl 8000ddc } /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ } 800052a: 46c0 nop @ (mov r8, r8) 800052c: 46bd mov sp, r7 800052e: bd80 pop {r7, pc} 8000530: 20000030 .word 0x20000030 8000534: 40005400 .word 0x40005400 8000538: 00303d5b .word 0x00303d5b 0800053c : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 800053c: b580 push {r7, lr} 800053e: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8000540: 4b23 ldr r3, [pc, #140] @ (80005d0 ) 8000542: 4a24 ldr r2, [pc, #144] @ (80005d4 ) 8000544: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; 8000546: 4b22 ldr r3, [pc, #136] @ (80005d0 ) 8000548: 22e1 movs r2, #225 @ 0xe1 800054a: 0252 lsls r2, r2, #9 800054c: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 800054e: 4b20 ldr r3, [pc, #128] @ (80005d0 ) 8000550: 2200 movs r2, #0 8000552: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 8000554: 4b1e ldr r3, [pc, #120] @ (80005d0 ) 8000556: 2200 movs r2, #0 8000558: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 800055a: 4b1d ldr r3, [pc, #116] @ (80005d0 ) 800055c: 2200 movs r2, #0 800055e: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8000560: 4b1b ldr r3, [pc, #108] @ (80005d0 ) 8000562: 220c movs r2, #12 8000564: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000566: 4b1a ldr r3, [pc, #104] @ (80005d0 ) 8000568: 2200 movs r2, #0 800056a: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 800056c: 4b18 ldr r3, [pc, #96] @ (80005d0 ) 800056e: 2200 movs r2, #0 8000570: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000572: 4b17 ldr r3, [pc, #92] @ (80005d0 ) 8000574: 2200 movs r2, #0 8000576: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000578: 4b15 ldr r3, [pc, #84] @ (80005d0 ) 800057a: 2200 movs r2, #0 800057c: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 800057e: 4b14 ldr r3, [pc, #80] @ (80005d0 ) 8000580: 2200 movs r2, #0 8000582: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart2) != HAL_OK) 8000584: 4b12 ldr r3, [pc, #72] @ (80005d0 ) 8000586: 0018 movs r0, r3 8000588: f003 fd6c bl 8004064 800058c: 1e03 subs r3, r0, #0 800058e: d001 beq.n 8000594 { Error_Handler(); 8000590: f000 fc24 bl 8000ddc } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000594: 4b0e ldr r3, [pc, #56] @ (80005d0 ) 8000596: 2100 movs r1, #0 8000598: 0018 movs r0, r3 800059a: f004 f9cb bl 8004934 800059e: 1e03 subs r3, r0, #0 80005a0: d001 beq.n 80005a6 { Error_Handler(); 80005a2: f000 fc1b bl 8000ddc } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80005a6: 4b0a ldr r3, [pc, #40] @ (80005d0 ) 80005a8: 2100 movs r1, #0 80005aa: 0018 movs r0, r3 80005ac: f004 fa02 bl 80049b4 80005b0: 1e03 subs r3, r0, #0 80005b2: d001 beq.n 80005b8 { Error_Handler(); 80005b4: f000 fc12 bl 8000ddc } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 80005b8: 4b05 ldr r3, [pc, #20] @ (80005d0 ) 80005ba: 0018 movs r0, r3 80005bc: f004 f980 bl 80048c0 80005c0: 1e03 subs r3, r0, #0 80005c2: d001 beq.n 80005c8 { Error_Handler(); 80005c4: f000 fc0a bl 8000ddc } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80005c8: 46c0 nop @ (mov r8, r8) 80005ca: 46bd mov sp, r7 80005cc: bd80 pop {r7, pc} 80005ce: 46c0 nop @ (mov r8, r8) 80005d0: 20000084 .word 0x20000084 80005d4: 40004400 .word 0x40004400 080005d8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80005d8: b590 push {r4, r7, lr} 80005da: b08b sub sp, #44 @ 0x2c 80005dc: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80005de: 2414 movs r4, #20 80005e0: 193b adds r3, r7, r4 80005e2: 0018 movs r0, r3 80005e4: 2314 movs r3, #20 80005e6: 001a movs r2, r3 80005e8: 2100 movs r1, #0 80005ea: f004 fa83 bl 8004af4 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 80005ee: 4b51 ldr r3, [pc, #324] @ (8000734 ) 80005f0: 6b5a ldr r2, [r3, #52] @ 0x34 80005f2: 4b50 ldr r3, [pc, #320] @ (8000734 ) 80005f4: 2104 movs r1, #4 80005f6: 430a orrs r2, r1 80005f8: 635a str r2, [r3, #52] @ 0x34 80005fa: 4b4e ldr r3, [pc, #312] @ (8000734 ) 80005fc: 6b5b ldr r3, [r3, #52] @ 0x34 80005fe: 2204 movs r2, #4 8000600: 4013 ands r3, r2 8000602: 613b str r3, [r7, #16] 8000604: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000606: 4b4b ldr r3, [pc, #300] @ (8000734 ) 8000608: 6b5a ldr r2, [r3, #52] @ 0x34 800060a: 4b4a ldr r3, [pc, #296] @ (8000734 ) 800060c: 2120 movs r1, #32 800060e: 430a orrs r2, r1 8000610: 635a str r2, [r3, #52] @ 0x34 8000612: 4b48 ldr r3, [pc, #288] @ (8000734 ) 8000614: 6b5b ldr r3, [r3, #52] @ 0x34 8000616: 2220 movs r2, #32 8000618: 4013 ands r3, r2 800061a: 60fb str r3, [r7, #12] 800061c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 800061e: 4b45 ldr r3, [pc, #276] @ (8000734 ) 8000620: 6b5a ldr r2, [r3, #52] @ 0x34 8000622: 4b44 ldr r3, [pc, #272] @ (8000734 ) 8000624: 2101 movs r1, #1 8000626: 430a orrs r2, r1 8000628: 635a str r2, [r3, #52] @ 0x34 800062a: 4b42 ldr r3, [pc, #264] @ (8000734 ) 800062c: 6b5b ldr r3, [r3, #52] @ 0x34 800062e: 2201 movs r2, #1 8000630: 4013 ands r3, r2 8000632: 60bb str r3, [r7, #8] 8000634: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000636: 4b3f ldr r3, [pc, #252] @ (8000734 ) 8000638: 6b5a ldr r2, [r3, #52] @ 0x34 800063a: 4b3e ldr r3, [pc, #248] @ (8000734 ) 800063c: 2102 movs r1, #2 800063e: 430a orrs r2, r1 8000640: 635a str r2, [r3, #52] @ 0x34 8000642: 4b3c ldr r3, [pc, #240] @ (8000734 ) 8000644: 6b5b ldr r3, [r3, #52] @ 0x34 8000646: 2202 movs r2, #2 8000648: 4013 ands r3, r2 800064a: 607b str r3, [r7, #4] 800064c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, GPIO_PIN_RESET); 800064e: 2380 movs r3, #128 @ 0x80 8000650: 019b lsls r3, r3, #6 8000652: 4839 ldr r0, [pc, #228] @ (8000738 ) 8000654: 2200 movs r2, #0 8000656: 0019 movs r1, r3 8000658: f001 f88b bl 8001772 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, LED3_Pin|HELP_BTN_Pin|INT_Pin, GPIO_PIN_RESET); 800065c: 4937 ldr r1, [pc, #220] @ (800073c ) 800065e: 23a0 movs r3, #160 @ 0xa0 8000660: 05db lsls r3, r3, #23 8000662: 2200 movs r2, #0 8000664: 0018 movs r0, r3 8000666: f001 f884 bl 8001772 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, RELAY1_Pin|RELAY2_Pin|BUZZ_Pin|LED4_Pin 800066a: 23e3 movs r3, #227 @ 0xe3 800066c: 021b lsls r3, r3, #8 800066e: 4834 ldr r0, [pc, #208] @ (8000740 ) 8000670: 2200 movs r2, #0 8000672: 0019 movs r1, r3 8000674: f001 f87d bl 8001772 |LED1_Pin, GPIO_PIN_RESET); /*Configure GPIO pin : LED2_Pin */ GPIO_InitStruct.Pin = LED2_Pin; 8000678: 193b adds r3, r7, r4 800067a: 2280 movs r2, #128 @ 0x80 800067c: 0192 lsls r2, r2, #6 800067e: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000680: 193b adds r3, r7, r4 8000682: 2201 movs r2, #1 8000684: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000686: 193b adds r3, r7, r4 8000688: 2200 movs r2, #0 800068a: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800068c: 193b adds r3, r7, r4 800068e: 2200 movs r2, #0 8000690: 60da str r2, [r3, #12] HAL_GPIO_Init(LED2_GPIO_Port, &GPIO_InitStruct); 8000692: 193b adds r3, r7, r4 8000694: 4a28 ldr r2, [pc, #160] @ (8000738 ) 8000696: 0019 movs r1, r3 8000698: 0010 movs r0, r2 800069a: f000 fee9 bl 8001470 /*Configure GPIO pins : LED3_Pin HELP_BTN_Pin INT_Pin */ GPIO_InitStruct.Pin = LED3_Pin|HELP_BTN_Pin|INT_Pin; 800069e: 193b adds r3, r7, r4 80006a0: 4a26 ldr r2, [pc, #152] @ (800073c ) 80006a2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80006a4: 193b adds r3, r7, r4 80006a6: 2201 movs r2, #1 80006a8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80006aa: 193b adds r3, r7, r4 80006ac: 2200 movs r2, #0 80006ae: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80006b0: 193b adds r3, r7, r4 80006b2: 2200 movs r2, #0 80006b4: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80006b6: 193a adds r2, r7, r4 80006b8: 23a0 movs r3, #160 @ 0xa0 80006ba: 05db lsls r3, r3, #23 80006bc: 0011 movs r1, r2 80006be: 0018 movs r0, r3 80006c0: f000 fed6 bl 8001470 /*Configure GPIO pins : WIRE8_Pin WIRE7_Pin WIRE6_Pin WIRE5_Pin */ GPIO_InitStruct.Pin = WIRE8_Pin|WIRE7_Pin|WIRE6_Pin|WIRE5_Pin; 80006c4: 193b adds r3, r7, r4 80006c6: 22f0 movs r2, #240 @ 0xf0 80006c8: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ca: 193b adds r3, r7, r4 80006cc: 2200 movs r2, #0 80006ce: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006d0: 193b adds r3, r7, r4 80006d2: 2201 movs r2, #1 80006d4: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80006d6: 193a adds r2, r7, r4 80006d8: 23a0 movs r3, #160 @ 0xa0 80006da: 05db lsls r3, r3, #23 80006dc: 0011 movs r1, r2 80006de: 0018 movs r0, r3 80006e0: f000 fec6 bl 8001470 /*Configure GPIO pins : WIRE4_Pin WIRE3_Pin WIRE2_Pin WIRE1_Pin */ GPIO_InitStruct.Pin = WIRE4_Pin|WIRE3_Pin|WIRE2_Pin|WIRE1_Pin; 80006e4: 193b adds r3, r7, r4 80006e6: 4a17 ldr r2, [pc, #92] @ (8000744 ) 80006e8: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80006ea: 193b adds r3, r7, r4 80006ec: 2200 movs r2, #0 80006ee: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80006f0: 193b adds r3, r7, r4 80006f2: 2201 movs r2, #1 80006f4: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80006f6: 193b adds r3, r7, r4 80006f8: 4a11 ldr r2, [pc, #68] @ (8000740 ) 80006fa: 0019 movs r1, r3 80006fc: 0010 movs r0, r2 80006fe: f000 feb7 bl 8001470 /*Configure GPIO pins : RELAY1_Pin RELAY2_Pin BUZZ_Pin LED4_Pin LED1_Pin */ GPIO_InitStruct.Pin = RELAY1_Pin|RELAY2_Pin|BUZZ_Pin|LED4_Pin 8000702: 0021 movs r1, r4 8000704: 187b adds r3, r7, r1 8000706: 22e3 movs r2, #227 @ 0xe3 8000708: 0212 lsls r2, r2, #8 800070a: 601a str r2, [r3, #0] |LED1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800070c: 187b adds r3, r7, r1 800070e: 2201 movs r2, #1 8000710: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000712: 187b adds r3, r7, r1 8000714: 2200 movs r2, #0 8000716: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000718: 187b adds r3, r7, r1 800071a: 2200 movs r2, #0 800071c: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800071e: 187b adds r3, r7, r1 8000720: 4a07 ldr r2, [pc, #28] @ (8000740 ) 8000722: 0019 movs r1, r3 8000724: 0010 movs r0, r2 8000726: f000 fea3 bl 8001470 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 800072a: 46c0 nop @ (mov r8, r8) 800072c: 46bd mov sp, r7 800072e: b00b add sp, #44 @ 0x2c 8000730: bd90 pop {r4, r7, pc} 8000732: 46c0 nop @ (mov r8, r8) 8000734: 40021000 .word 0x40021000 8000738: 50000800 .word 0x50000800 800073c: 00000501 .word 0x00000501 8000740: 50000400 .word 0x50000400 8000744: 00000407 .word 0x00000407 08000748 : return ch; } bool has_received_data; void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { 8000748: b580 push {r7, lr} 800074a: b082 sub sp, #8 800074c: af00 add r7, sp, #0 800074e: 6078 str r0, [r7, #4] i2c_register = 0; 8000750: 4b06 ldr r3, [pc, #24] @ (800076c ) 8000752: 2200 movs r2, #0 8000754: 701a strb r2, [r3, #0] has_received_data = false; 8000756: 4b06 ldr r3, [pc, #24] @ (8000770 ) 8000758: 2200 movs r2, #0 800075a: 701a strb r2, [r3, #0] HAL_I2C_EnableListen_IT(hi2c); 800075c: 687b ldr r3, [r7, #4] 800075e: 0018 movs r0, r3 8000760: f001 fa4c bl 8001bfc } 8000764: 46c0 nop @ (mov r8, r8) 8000766: 46bd mov sp, r7 8000768: b002 add sp, #8 800076a: bd80 pop {r7, pc} 800076c: 2000002c .word 0x2000002c 8000770: 20000128 .word 0x20000128 08000774 : void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { 8000774: b580 push {r7, lr} 8000776: b082 sub sp, #8 8000778: af00 add r7, sp, #0 800077a: 6078 str r0, [r7, #4] 800077c: 0008 movs r0, r1 800077e: 0011 movs r1, r2 8000780: 1cfb adds r3, r7, #3 8000782: 1c02 adds r2, r0, #0 8000784: 701a strb r2, [r3, #0] 8000786: 003b movs r3, r7 8000788: 1c0a adds r2, r1, #0 800078a: 801a strh r2, [r3, #0] if (TransferDirection == I2C_DIRECTION_TRANSMIT) { 800078c: 1cfb adds r3, r7, #3 800078e: 781b ldrb r3, [r3, #0] 8000790: 2b00 cmp r3, #0 8000792: d107 bne.n 80007a4 HAL_I2C_Slave_Seq_Receive_IT(hi2c, &i2c_register, 1, I2C_NEXT_FRAME); 8000794: 2380 movs r3, #128 @ 0x80 8000796: 045b lsls r3, r3, #17 8000798: 4905 ldr r1, [pc, #20] @ (80007b0 ) 800079a: 6878 ldr r0, [r7, #4] 800079c: 2201 movs r2, #1 800079e: f001 f96b bl 8001a78 } else { send_register(); } } 80007a2: e001 b.n 80007a8 send_register(); 80007a4: f000 f806 bl 80007b4 } 80007a8: 46c0 nop @ (mov r8, r8) 80007aa: 46bd mov sp, r7 80007ac: b002 add sp, #8 80007ae: bd80 pop {r7, pc} 80007b0: 2000002c .word 0x2000002c 080007b4 : uint8_t send_data[2]; void send_register(void) { 80007b4: b580 push {r7, lr} 80007b6: af00 add r7, sp, #0 switch (i2c_register) { 80007b8: 4b35 ldr r3, [pc, #212] @ (8000890 ) 80007ba: 781b ldrb r3, [r3, #0] 80007bc: 2b08 cmp r3, #8 80007be: d862 bhi.n 8000886 80007c0: 009a lsls r2, r3, #2 80007c2: 4b34 ldr r3, [pc, #208] @ (8000894 ) 80007c4: 18d3 adds r3, r2, r3 80007c6: 681b ldr r3, [r3, #0] 80007c8: 469f mov pc, r3 case I2C_REGISTER_DELTA: HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &delta, 1, I2C_NEXT_FRAME); 80007ca: 2380 movs r3, #128 @ 0x80 80007cc: 045b lsls r3, r3, #17 80007ce: 4932 ldr r1, [pc, #200] @ (8000898 ) 80007d0: 4832 ldr r0, [pc, #200] @ (800089c ) 80007d2: 2201 movs r2, #1 80007d4: f001 f890 bl 80018f8 break; 80007d8: e056 b.n 8000888 case I2C_REGISTER_WIRES: HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &wires, 1, I2C_NEXT_FRAME); 80007da: 2380 movs r3, #128 @ 0x80 80007dc: 045b lsls r3, r3, #17 80007de: 4930 ldr r1, [pc, #192] @ (80008a0 ) 80007e0: 482e ldr r0, [pc, #184] @ (800089c ) 80007e2: 2201 movs r2, #1 80007e4: f001 f888 bl 80018f8 delta &= ~(1 << DELTA_BIT_WIRES); 80007e8: 4b2b ldr r3, [pc, #172] @ (8000898 ) 80007ea: 781b ldrb r3, [r3, #0] 80007ec: 2201 movs r2, #1 80007ee: 4393 bics r3, r2 80007f0: b2da uxtb r2, r3 80007f2: 4b29 ldr r3, [pc, #164] @ (8000898 ) 80007f4: 701a strb r2, [r3, #0] break; 80007f6: e047 b.n 8000888 case I2C_REGISTER_BUTTON: HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &button, 1, I2C_NEXT_FRAME); 80007f8: 2380 movs r3, #128 @ 0x80 80007fa: 045b lsls r3, r3, #17 80007fc: 4929 ldr r1, [pc, #164] @ (80008a4 ) 80007fe: 4827 ldr r0, [pc, #156] @ (800089c ) 8000800: 2201 movs r2, #1 8000802: f001 f879 bl 80018f8 delta &= ~(1 << DELTA_BIT_BUTTON); 8000806: 4b24 ldr r3, [pc, #144] @ (8000898 ) 8000808: 781b ldrb r3, [r3, #0] 800080a: 2202 movs r2, #2 800080c: 4393 bics r3, r2 800080e: b2da uxtb r2, r3 8000810: 4b21 ldr r3, [pc, #132] @ (8000898 ) 8000812: 701a strb r2, [r3, #0] break; 8000814: e038 b.n 8000888 case I2C_REGISTER_RELAY_BUZZ: HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &relay_buzz, 1, I2C_NEXT_FRAME); 8000816: 2380 movs r3, #128 @ 0x80 8000818: 045b lsls r3, r3, #17 800081a: 4923 ldr r1, [pc, #140] @ (80008a8 ) 800081c: 481f ldr r0, [pc, #124] @ (800089c ) 800081e: 2201 movs r2, #1 8000820: f001 f86a bl 80018f8 break; 8000824: e030 b.n 8000888 case I2C_REGISTER_LED: HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &leds, 1, I2C_NEXT_FRAME); 8000826: 2380 movs r3, #128 @ 0x80 8000828: 045b lsls r3, r3, #17 800082a: 4920 ldr r1, [pc, #128] @ (80008ac ) 800082c: 481b ldr r0, [pc, #108] @ (800089c ) 800082e: 2201 movs r2, #1 8000830: f001 f862 bl 80018f8 break; 8000834: e028 b.n 8000888 case I2C_REGISTER_STRIKE_BUZZ_LEN: send_data[0] = strike_buzz_len & 0xFF; 8000836: 4b1e ldr r3, [pc, #120] @ (80008b0 ) 8000838: 881b ldrh r3, [r3, #0] 800083a: b2da uxtb r2, r3 800083c: 4b1d ldr r3, [pc, #116] @ (80008b4 ) 800083e: 701a strb r2, [r3, #0] send_data[1] = strike_buzz_len >> 8; 8000840: 4b1b ldr r3, [pc, #108] @ (80008b0 ) 8000842: 881b ldrh r3, [r3, #0] 8000844: 0a1b lsrs r3, r3, #8 8000846: b29b uxth r3, r3 8000848: b2da uxtb r2, r3 800084a: 4b1a ldr r3, [pc, #104] @ (80008b4 ) 800084c: 705a strb r2, [r3, #1] HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, send_data, 2, I2C_NEXT_FRAME); 800084e: 2380 movs r3, #128 @ 0x80 8000850: 045b lsls r3, r3, #17 8000852: 4918 ldr r1, [pc, #96] @ (80008b4 ) 8000854: 4811 ldr r0, [pc, #68] @ (800089c ) 8000856: 2202 movs r2, #2 8000858: f001 f84e bl 80018f8 break; 800085c: e014 b.n 8000888 case I2C_REGISTER_STRIKE_RELAY_LEN: send_data[0] = strike_relay_len & 0xFF; 800085e: 4b16 ldr r3, [pc, #88] @ (80008b8 ) 8000860: 881b ldrh r3, [r3, #0] 8000862: b2da uxtb r2, r3 8000864: 4b13 ldr r3, [pc, #76] @ (80008b4 ) 8000866: 701a strb r2, [r3, #0] send_data[1] = strike_relay_len >> 8; 8000868: 4b13 ldr r3, [pc, #76] @ (80008b8 ) 800086a: 881b ldrh r3, [r3, #0] 800086c: 0a1b lsrs r3, r3, #8 800086e: b29b uxth r3, r3 8000870: b2da uxtb r2, r3 8000872: 4b10 ldr r3, [pc, #64] @ (80008b4 ) 8000874: 705a strb r2, [r3, #1] HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, send_data, 2, I2C_NEXT_FRAME); 8000876: 2380 movs r3, #128 @ 0x80 8000878: 045b lsls r3, r3, #17 800087a: 490e ldr r1, [pc, #56] @ (80008b4 ) 800087c: 4807 ldr r0, [pc, #28] @ (800089c ) 800087e: 2202 movs r2, #2 8000880: f001 f83a bl 80018f8 break; 8000884: e000 b.n 8000888 default: break; 8000886: 46c0 nop @ (mov r8, r8) } } 8000888: 46c0 nop @ (mov r8, r8) 800088a: 46bd mov sp, r7 800088c: bd80 pop {r7, pc} 800088e: 46c0 nop @ (mov r8, r8) 8000890: 2000002c .word 0x2000002c 8000894: 08004b64 .word 0x08004b64 8000898: 20000119 .word 0x20000119 800089c: 20000030 .word 0x20000030 80008a0: 2000011b .word 0x2000011b 80008a4: 2000011d .word 0x2000011d 80008a8: 2000011f .word 0x2000011f 80008ac: 20000121 .word 0x20000121 80008b0: 20000000 .word 0x20000000 80008b4: 2000012c .word 0x2000012c 80008b8: 20000002 .word 0x20000002 080008bc : uint8_t recv_data[2]; void recv_register(void) { 80008bc: b580 push {r7, lr} 80008be: af00 add r7, sp, #0 switch (i2c_register) { 80008c0: 4b19 ldr r3, [pc, #100] @ (8000928 ) 80008c2: 781b ldrb r3, [r3, #0] 80008c4: 2b08 cmp r3, #8 80008c6: d020 beq.n 800090a 80008c8: dc27 bgt.n 800091a 80008ca: 2b07 cmp r3, #7 80008cc: d015 beq.n 80008fa 80008ce: dc24 bgt.n 800091a 80008d0: 2b04 cmp r3, #4 80008d2: d002 beq.n 80008da 80008d4: 2b05 cmp r3, #5 80008d6: d008 beq.n 80008ea break; case I2C_REGISTER_STRIKE_RELAY_LEN: HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME); break; default: break; 80008d8: e01f b.n 800091a HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, &relay_buzz, 1, I2C_NEXT_FRAME); 80008da: 2380 movs r3, #128 @ 0x80 80008dc: 045b lsls r3, r3, #17 80008de: 4913 ldr r1, [pc, #76] @ (800092c ) 80008e0: 4813 ldr r0, [pc, #76] @ (8000930 ) 80008e2: 2201 movs r2, #1 80008e4: f001 f8c8 bl 8001a78 break; 80008e8: e018 b.n 800091c HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, &leds, 1, I2C_NEXT_FRAME); 80008ea: 2380 movs r3, #128 @ 0x80 80008ec: 045b lsls r3, r3, #17 80008ee: 4911 ldr r1, [pc, #68] @ (8000934 ) 80008f0: 480f ldr r0, [pc, #60] @ (8000930 ) 80008f2: 2201 movs r2, #1 80008f4: f001 f8c0 bl 8001a78 break; 80008f8: e010 b.n 800091c HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME); 80008fa: 2380 movs r3, #128 @ 0x80 80008fc: 045b lsls r3, r3, #17 80008fe: 490e ldr r1, [pc, #56] @ (8000938 ) 8000900: 480b ldr r0, [pc, #44] @ (8000930 ) 8000902: 2202 movs r2, #2 8000904: f001 f8b8 bl 8001a78 break; 8000908: e008 b.n 800091c HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME); 800090a: 2380 movs r3, #128 @ 0x80 800090c: 045b lsls r3, r3, #17 800090e: 490a ldr r1, [pc, #40] @ (8000938 ) 8000910: 4807 ldr r0, [pc, #28] @ (8000930 ) 8000912: 2202 movs r2, #2 8000914: f001 f8b0 bl 8001a78 break; 8000918: e000 b.n 800091c break; 800091a: 46c0 nop @ (mov r8, r8) } has_received_data = true; 800091c: 4b07 ldr r3, [pc, #28] @ (800093c ) 800091e: 2201 movs r2, #1 8000920: 701a strb r2, [r3, #0] } 8000922: 46c0 nop @ (mov r8, r8) 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 8000928: 2000002c .word 0x2000002c 800092c: 2000011f .word 0x2000011f 8000930: 20000030 .word 0x20000030 8000934: 20000121 .word 0x20000121 8000938: 20000130 .word 0x20000130 800093c: 20000128 .word 0x20000128 08000940 : void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { 8000940: b580 push {r7, lr} 8000942: b082 sub sp, #8 8000944: af00 add r7, sp, #0 8000946: 6078 str r0, [r7, #4] if (i2c_register == I2C_REGISTER_ISSUE_STRIKE) { 8000948: 4b1f ldr r3, [pc, #124] @ (80009c8 ) 800094a: 781b ldrb r3, [r3, #0] 800094c: 2b06 cmp r3, #6 800094e: d102 bne.n 8000956 strike_issued = true; 8000950: 4b1e ldr r3, [pc, #120] @ (80009cc ) 8000952: 2201 movs r2, #1 8000954: 701a strb r2, [r3, #0] } if (has_received_data) { 8000956: 4b1e ldr r3, [pc, #120] @ (80009d0 ) 8000958: 781b ldrb r3, [r3, #0] 800095a: 2b00 cmp r3, #0 800095c: d02d beq.n 80009ba has_received_data = false; 800095e: 4b1c ldr r3, [pc, #112] @ (80009d0 ) 8000960: 2200 movs r2, #0 8000962: 701a strb r2, [r3, #0] // reconstruct anything that needs to be reconstructed switch (i2c_register) { 8000964: 4b18 ldr r3, [pc, #96] @ (80009c8 ) 8000966: 781b ldrb r3, [r3, #0] 8000968: 2b07 cmp r3, #7 800096a: d002 beq.n 8000972 800096c: 2b08 cmp r3, #8 800096e: d012 beq.n 8000996 case I2C_REGISTER_STRIKE_RELAY_LEN: strike_relay_len = recv_data[0]; strike_relay_len |= ((uint16_t) recv_data[1]) << 8; break; default: break; 8000970: e026 b.n 80009c0 strike_buzz_len = recv_data[0]; 8000972: 4b18 ldr r3, [pc, #96] @ (80009d4 ) 8000974: 781b ldrb r3, [r3, #0] 8000976: 001a movs r2, r3 8000978: 4b17 ldr r3, [pc, #92] @ (80009d8 ) 800097a: 801a strh r2, [r3, #0] strike_buzz_len |= ((uint16_t) recv_data[1]) << 8; 800097c: 4b15 ldr r3, [pc, #84] @ (80009d4 ) 800097e: 785b ldrb r3, [r3, #1] 8000980: 021b lsls r3, r3, #8 8000982: b21a sxth r2, r3 8000984: 4b14 ldr r3, [pc, #80] @ (80009d8 ) 8000986: 881b ldrh r3, [r3, #0] 8000988: b21b sxth r3, r3 800098a: 4313 orrs r3, r2 800098c: b21b sxth r3, r3 800098e: b29a uxth r2, r3 8000990: 4b11 ldr r3, [pc, #68] @ (80009d8 ) 8000992: 801a strh r2, [r3, #0] break; 8000994: e014 b.n 80009c0 strike_relay_len = recv_data[0]; 8000996: 4b0f ldr r3, [pc, #60] @ (80009d4 ) 8000998: 781b ldrb r3, [r3, #0] 800099a: 001a movs r2, r3 800099c: 4b0f ldr r3, [pc, #60] @ (80009dc ) 800099e: 801a strh r2, [r3, #0] strike_relay_len |= ((uint16_t) recv_data[1]) << 8; 80009a0: 4b0c ldr r3, [pc, #48] @ (80009d4 ) 80009a2: 785b ldrb r3, [r3, #1] 80009a4: 021b lsls r3, r3, #8 80009a6: b21a sxth r2, r3 80009a8: 4b0c ldr r3, [pc, #48] @ (80009dc ) 80009aa: 881b ldrh r3, [r3, #0] 80009ac: b21b sxth r3, r3 80009ae: 4313 orrs r3, r2 80009b0: b21b sxth r3, r3 80009b2: b29a uxth r2, r3 80009b4: 4b09 ldr r3, [pc, #36] @ (80009dc ) 80009b6: 801a strh r2, [r3, #0] break; 80009b8: e002 b.n 80009c0 } } else { recv_register(); 80009ba: f7ff ff7f bl 80008bc } } 80009be: 46c0 nop @ (mov r8, r8) 80009c0: 46c0 nop @ (mov r8, r8) 80009c2: 46bd mov sp, r7 80009c4: b002 add sp, #8 80009c6: bd80 pop {r7, pc} 80009c8: 2000002c .word 0x2000002c 80009cc: 20000122 .word 0x20000122 80009d0: 20000128 .word 0x20000128 80009d4: 20000130 .word 0x20000130 80009d8: 20000000 .word 0x20000000 80009dc: 20000002 .word 0x20000002 080009e0 : void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) { 80009e0: b580 push {r7, lr} 80009e2: b082 sub sp, #8 80009e4: af00 add r7, sp, #0 80009e6: 6078 str r0, [r7, #4] } 80009e8: 46c0 nop @ (mov r8, r8) 80009ea: 46bd mov sp, r7 80009ec: b002 add sp, #8 80009ee: bd80 pop {r7, pc} 080009f0 : void scan_wires(void) { 80009f0: b580 push {r7, lr} 80009f2: b082 sub sp, #8 80009f4: af00 add r7, sp, #0 old_wires = wires; 80009f6: 4b58 ldr r3, [pc, #352] @ (8000b58 ) 80009f8: 781a ldrb r2, [r3, #0] 80009fa: 4b58 ldr r3, [pc, #352] @ (8000b5c ) 80009fc: 701a strb r2, [r3, #0] uint8_t new_wires = 0; 80009fe: 1dfb adds r3, r7, #7 8000a00: 2200 movs r2, #0 8000a02: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE1_GPIO_Port, WIRE1_Pin) == GPIO_PIN_RESET) << 0; 8000a04: 2380 movs r3, #128 @ 0x80 8000a06: 00db lsls r3, r3, #3 8000a08: 4a55 ldr r2, [pc, #340] @ (8000b60 ) 8000a0a: 0019 movs r1, r3 8000a0c: 0010 movs r0, r2 8000a0e: f000 fe93 bl 8001738 8000a12: 0003 movs r3, r0 8000a14: 425a negs r2, r3 8000a16: 4153 adcs r3, r2 8000a18: b2db uxtb r3, r3 8000a1a: b25a sxtb r2, r3 8000a1c: 1dfb adds r3, r7, #7 8000a1e: 781b ldrb r3, [r3, #0] 8000a20: b25b sxtb r3, r3 8000a22: 4313 orrs r3, r2 8000a24: b25a sxtb r2, r3 8000a26: 1dfb adds r3, r7, #7 8000a28: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE2_GPIO_Port, WIRE2_Pin) == GPIO_PIN_RESET) << 1; 8000a2a: 4b4d ldr r3, [pc, #308] @ (8000b60 ) 8000a2c: 2104 movs r1, #4 8000a2e: 0018 movs r0, r3 8000a30: f000 fe82 bl 8001738 8000a34: 1e03 subs r3, r0, #0 8000a36: d101 bne.n 8000a3c 8000a38: 2302 movs r3, #2 8000a3a: e000 b.n 8000a3e 8000a3c: 2300 movs r3, #0 8000a3e: b25a sxtb r2, r3 8000a40: 1dfb adds r3, r7, #7 8000a42: 781b ldrb r3, [r3, #0] 8000a44: b25b sxtb r3, r3 8000a46: 4313 orrs r3, r2 8000a48: b25a sxtb r2, r3 8000a4a: 1dfb adds r3, r7, #7 8000a4c: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE3_GPIO_Port, WIRE3_Pin) == GPIO_PIN_RESET) << 2; 8000a4e: 4b44 ldr r3, [pc, #272] @ (8000b60 ) 8000a50: 2102 movs r1, #2 8000a52: 0018 movs r0, r3 8000a54: f000 fe70 bl 8001738 8000a58: 1e03 subs r3, r0, #0 8000a5a: d101 bne.n 8000a60 8000a5c: 2304 movs r3, #4 8000a5e: e000 b.n 8000a62 8000a60: 2300 movs r3, #0 8000a62: b25a sxtb r2, r3 8000a64: 1dfb adds r3, r7, #7 8000a66: 781b ldrb r3, [r3, #0] 8000a68: b25b sxtb r3, r3 8000a6a: 4313 orrs r3, r2 8000a6c: b25a sxtb r2, r3 8000a6e: 1dfb adds r3, r7, #7 8000a70: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE4_GPIO_Port, WIRE4_Pin) == GPIO_PIN_RESET) << 3; 8000a72: 4b3b ldr r3, [pc, #236] @ (8000b60 ) 8000a74: 2101 movs r1, #1 8000a76: 0018 movs r0, r3 8000a78: f000 fe5e bl 8001738 8000a7c: 1e03 subs r3, r0, #0 8000a7e: d101 bne.n 8000a84 8000a80: 2308 movs r3, #8 8000a82: e000 b.n 8000a86 8000a84: 2300 movs r3, #0 8000a86: b25a sxtb r2, r3 8000a88: 1dfb adds r3, r7, #7 8000a8a: 781b ldrb r3, [r3, #0] 8000a8c: b25b sxtb r3, r3 8000a8e: 4313 orrs r3, r2 8000a90: b25a sxtb r2, r3 8000a92: 1dfb adds r3, r7, #7 8000a94: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE5_GPIO_Port, WIRE5_Pin) == GPIO_PIN_RESET) << 4; 8000a96: 23a0 movs r3, #160 @ 0xa0 8000a98: 05db lsls r3, r3, #23 8000a9a: 2180 movs r1, #128 @ 0x80 8000a9c: 0018 movs r0, r3 8000a9e: f000 fe4b bl 8001738 8000aa2: 1e03 subs r3, r0, #0 8000aa4: d101 bne.n 8000aaa 8000aa6: 2310 movs r3, #16 8000aa8: e000 b.n 8000aac 8000aaa: 2300 movs r3, #0 8000aac: b25a sxtb r2, r3 8000aae: 1dfb adds r3, r7, #7 8000ab0: 781b ldrb r3, [r3, #0] 8000ab2: b25b sxtb r3, r3 8000ab4: 4313 orrs r3, r2 8000ab6: b25a sxtb r2, r3 8000ab8: 1dfb adds r3, r7, #7 8000aba: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE6_GPIO_Port, WIRE6_Pin) == GPIO_PIN_RESET) << 5; 8000abc: 23a0 movs r3, #160 @ 0xa0 8000abe: 05db lsls r3, r3, #23 8000ac0: 2140 movs r1, #64 @ 0x40 8000ac2: 0018 movs r0, r3 8000ac4: f000 fe38 bl 8001738 8000ac8: 1e03 subs r3, r0, #0 8000aca: d101 bne.n 8000ad0 8000acc: 2320 movs r3, #32 8000ace: e000 b.n 8000ad2 8000ad0: 2300 movs r3, #0 8000ad2: b25a sxtb r2, r3 8000ad4: 1dfb adds r3, r7, #7 8000ad6: 781b ldrb r3, [r3, #0] 8000ad8: b25b sxtb r3, r3 8000ada: 4313 orrs r3, r2 8000adc: b25a sxtb r2, r3 8000ade: 1dfb adds r3, r7, #7 8000ae0: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE7_GPIO_Port, WIRE7_Pin) == GPIO_PIN_RESET) << 6; 8000ae2: 23a0 movs r3, #160 @ 0xa0 8000ae4: 05db lsls r3, r3, #23 8000ae6: 2120 movs r1, #32 8000ae8: 0018 movs r0, r3 8000aea: f000 fe25 bl 8001738 8000aee: 1e03 subs r3, r0, #0 8000af0: d101 bne.n 8000af6 8000af2: 2340 movs r3, #64 @ 0x40 8000af4: e000 b.n 8000af8 8000af6: 2300 movs r3, #0 8000af8: b25a sxtb r2, r3 8000afa: 1dfb adds r3, r7, #7 8000afc: 781b ldrb r3, [r3, #0] 8000afe: b25b sxtb r3, r3 8000b00: 4313 orrs r3, r2 8000b02: b25a sxtb r2, r3 8000b04: 1dfb adds r3, r7, #7 8000b06: 701a strb r2, [r3, #0] new_wires |= (HAL_GPIO_ReadPin(WIRE8_GPIO_Port, WIRE8_Pin) == GPIO_PIN_RESET) << 7; 8000b08: 23a0 movs r3, #160 @ 0xa0 8000b0a: 05db lsls r3, r3, #23 8000b0c: 2110 movs r1, #16 8000b0e: 0018 movs r0, r3 8000b10: f000 fe12 bl 8001738 8000b14: 1e03 subs r3, r0, #0 8000b16: d101 bne.n 8000b1c 8000b18: 2380 movs r3, #128 @ 0x80 8000b1a: e000 b.n 8000b1e 8000b1c: 2300 movs r3, #0 8000b1e: b25a sxtb r2, r3 8000b20: 1dfb adds r3, r7, #7 8000b22: 781b ldrb r3, [r3, #0] 8000b24: b25b sxtb r3, r3 8000b26: 4313 orrs r3, r2 8000b28: b25a sxtb r2, r3 8000b2a: 1dfb adds r3, r7, #7 8000b2c: 701a strb r2, [r3, #0] wires = new_wires; 8000b2e: 4b0a ldr r3, [pc, #40] @ (8000b58 ) 8000b30: 1dfa adds r2, r7, #7 8000b32: 7812 ldrb r2, [r2, #0] 8000b34: 701a strb r2, [r3, #0] if (wires != old_wires) { 8000b36: 4b08 ldr r3, [pc, #32] @ (8000b58 ) 8000b38: 781a ldrb r2, [r3, #0] 8000b3a: 4b08 ldr r3, [pc, #32] @ (8000b5c ) 8000b3c: 781b ldrb r3, [r3, #0] 8000b3e: 429a cmp r2, r3 8000b40: d006 beq.n 8000b50 delta |= 1 << DELTA_BIT_WIRES; 8000b42: 4b08 ldr r3, [pc, #32] @ (8000b64 ) 8000b44: 781b ldrb r3, [r3, #0] 8000b46: 2201 movs r2, #1 8000b48: 4313 orrs r3, r2 8000b4a: b2da uxtb r2, r3 8000b4c: 4b05 ldr r3, [pc, #20] @ (8000b64 ) 8000b4e: 701a strb r2, [r3, #0] } } 8000b50: 46c0 nop @ (mov r8, r8) 8000b52: 46bd mov sp, r7 8000b54: b002 add sp, #8 8000b56: bd80 pop {r7, pc} 8000b58: 2000011b .word 0x2000011b 8000b5c: 2000011a .word 0x2000011a 8000b60: 50000400 .word 0x50000400 8000b64: 20000119 .word 0x20000119 08000b68 : void scan_button(void) { 8000b68: b580 push {r7, lr} 8000b6a: af00 add r7, sp, #0 old_button = button; 8000b6c: 4b11 ldr r3, [pc, #68] @ (8000bb4 ) 8000b6e: 781a ldrb r2, [r3, #0] 8000b70: 4b11 ldr r3, [pc, #68] @ (8000bb8 ) 8000b72: 701a strb r2, [r3, #0] button = HAL_GPIO_ReadPin(HELP_BTN_GPIO_Port, HELP_BTN_Pin) == GPIO_PIN_RESET; 8000b74: 2380 movs r3, #128 @ 0x80 8000b76: 005a lsls r2, r3, #1 8000b78: 23a0 movs r3, #160 @ 0xa0 8000b7a: 05db lsls r3, r3, #23 8000b7c: 0011 movs r1, r2 8000b7e: 0018 movs r0, r3 8000b80: f000 fdda bl 8001738 8000b84: 0003 movs r3, r0 8000b86: 425a negs r2, r3 8000b88: 4153 adcs r3, r2 8000b8a: b2db uxtb r3, r3 8000b8c: 001a movs r2, r3 8000b8e: 4b09 ldr r3, [pc, #36] @ (8000bb4 ) 8000b90: 701a strb r2, [r3, #0] if (button != old_button) { 8000b92: 4b08 ldr r3, [pc, #32] @ (8000bb4 ) 8000b94: 781a ldrb r2, [r3, #0] 8000b96: 4b08 ldr r3, [pc, #32] @ (8000bb8 ) 8000b98: 781b ldrb r3, [r3, #0] 8000b9a: 429a cmp r2, r3 8000b9c: d006 beq.n 8000bac delta |= 1 << DELTA_BIT_BUTTON; 8000b9e: 4b07 ldr r3, [pc, #28] @ (8000bbc ) 8000ba0: 781b ldrb r3, [r3, #0] 8000ba2: 2202 movs r2, #2 8000ba4: 4313 orrs r3, r2 8000ba6: b2da uxtb r2, r3 8000ba8: 4b04 ldr r3, [pc, #16] @ (8000bbc ) 8000baa: 701a strb r2, [r3, #0] } } 8000bac: 46c0 nop @ (mov r8, r8) 8000bae: 46bd mov sp, r7 8000bb0: bd80 pop {r7, pc} 8000bb2: 46c0 nop @ (mov r8, r8) 8000bb4: 2000011d .word 0x2000011d 8000bb8: 2000011c .word 0x2000011c 8000bbc: 20000119 .word 0x20000119 08000bc0 : void set_relay_buzz(void) { 8000bc0: b580 push {r7, lr} 8000bc2: af00 add r7, sp, #0 if (relay_buzz != old_relay_buzz) { 8000bc4: 4b18 ldr r3, [pc, #96] @ (8000c28 ) 8000bc6: 781a ldrb r2, [r3, #0] 8000bc8: 4b18 ldr r3, [pc, #96] @ (8000c2c ) 8000bca: 781b ldrb r3, [r3, #0] 8000bcc: 429a cmp r2, r3 8000bce: d028 beq.n 8000c22 old_relay_buzz = relay_buzz; 8000bd0: 4b15 ldr r3, [pc, #84] @ (8000c28 ) 8000bd2: 781a ldrb r2, [r3, #0] 8000bd4: 4b15 ldr r3, [pc, #84] @ (8000c2c ) 8000bd6: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(BUZZ_GPIO_Port, BUZZ_Pin, (relay_buzz >> BUZZ_BIT_IDX) & 1); 8000bd8: 4b13 ldr r3, [pc, #76] @ (8000c28 ) 8000bda: 781b ldrb r3, [r3, #0] 8000bdc: 2201 movs r2, #1 8000bde: 4013 ands r3, r2 8000be0: b2da uxtb r2, r3 8000be2: 2380 movs r3, #128 @ 0x80 8000be4: 021b lsls r3, r3, #8 8000be6: 4812 ldr r0, [pc, #72] @ (8000c30 ) 8000be8: 0019 movs r1, r3 8000bea: f000 fdc2 bl 8001772 HAL_GPIO_WritePin(RELAY1_GPIO_Port, RELAY1_Pin, (relay_buzz >> RELAY_BIT_IDX) & 1); 8000bee: 4b0e ldr r3, [pc, #56] @ (8000c28 ) 8000bf0: 781b ldrb r3, [r3, #0] 8000bf2: 085b lsrs r3, r3, #1 8000bf4: b2db uxtb r3, r3 8000bf6: 2201 movs r2, #1 8000bf8: 4013 ands r3, r2 8000bfa: b2da uxtb r2, r3 8000bfc: 2380 movs r3, #128 @ 0x80 8000bfe: 019b lsls r3, r3, #6 8000c00: 480b ldr r0, [pc, #44] @ (8000c30 ) 8000c02: 0019 movs r1, r3 8000c04: f000 fdb5 bl 8001772 HAL_GPIO_WritePin(RELAY2_GPIO_Port, RELAY2_Pin, (relay_buzz >> RELAY_BIT_IDX) & 1); 8000c08: 4b07 ldr r3, [pc, #28] @ (8000c28 ) 8000c0a: 781b ldrb r3, [r3, #0] 8000c0c: 085b lsrs r3, r3, #1 8000c0e: b2db uxtb r3, r3 8000c10: 2201 movs r2, #1 8000c12: 4013 ands r3, r2 8000c14: b2da uxtb r2, r3 8000c16: 2380 movs r3, #128 @ 0x80 8000c18: 01db lsls r3, r3, #7 8000c1a: 4805 ldr r0, [pc, #20] @ (8000c30 ) 8000c1c: 0019 movs r1, r3 8000c1e: f000 fda8 bl 8001772 } } 8000c22: 46c0 nop @ (mov r8, r8) 8000c24: 46bd mov sp, r7 8000c26: bd80 pop {r7, pc} 8000c28: 2000011f .word 0x2000011f 8000c2c: 2000011e .word 0x2000011e 8000c30: 50000400 .word 0x50000400 08000c34 : void set_leds(void) { 8000c34: b580 push {r7, lr} 8000c36: af00 add r7, sp, #0 if (leds != old_leds) { 8000c38: 4b1f ldr r3, [pc, #124] @ (8000cb8 ) 8000c3a: 781a ldrb r2, [r3, #0] 8000c3c: 4b1f ldr r3, [pc, #124] @ (8000cbc ) 8000c3e: 781b ldrb r3, [r3, #0] 8000c40: 429a cmp r2, r3 8000c42: d035 beq.n 8000cb0 old_leds = leds; 8000c44: 4b1c ldr r3, [pc, #112] @ (8000cb8 ) 8000c46: 781a ldrb r2, [r3, #0] 8000c48: 4b1c ldr r3, [pc, #112] @ (8000cbc ) 8000c4a: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (leds >> 0) & 1); 8000c4c: 4b1a ldr r3, [pc, #104] @ (8000cb8 ) 8000c4e: 781b ldrb r3, [r3, #0] 8000c50: 2201 movs r2, #1 8000c52: 4013 ands r3, r2 8000c54: b2da uxtb r2, r3 8000c56: 2380 movs r3, #128 @ 0x80 8000c58: 009b lsls r3, r3, #2 8000c5a: 4819 ldr r0, [pc, #100] @ (8000cc0 ) 8000c5c: 0019 movs r1, r3 8000c5e: f000 fd88 bl 8001772 HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (leds >> 1) & 1); 8000c62: 4b15 ldr r3, [pc, #84] @ (8000cb8 ) 8000c64: 781b ldrb r3, [r3, #0] 8000c66: 085b lsrs r3, r3, #1 8000c68: b2db uxtb r3, r3 8000c6a: 2201 movs r2, #1 8000c6c: 4013 ands r3, r2 8000c6e: b2da uxtb r2, r3 8000c70: 2380 movs r3, #128 @ 0x80 8000c72: 019b lsls r3, r3, #6 8000c74: 4813 ldr r0, [pc, #76] @ (8000cc4 ) 8000c76: 0019 movs r1, r3 8000c78: f000 fd7b bl 8001772 HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, (leds >> 2) & 1); 8000c7c: 4b0e ldr r3, [pc, #56] @ (8000cb8 ) 8000c7e: 781b ldrb r3, [r3, #0] 8000c80: 089b lsrs r3, r3, #2 8000c82: b2db uxtb r3, r3 8000c84: 2201 movs r2, #1 8000c86: 4013 ands r3, r2 8000c88: b2da uxtb r2, r3 8000c8a: 23a0 movs r3, #160 @ 0xa0 8000c8c: 05db lsls r3, r3, #23 8000c8e: 2101 movs r1, #1 8000c90: 0018 movs r0, r3 8000c92: f000 fd6e bl 8001772 HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, (leds >> 3) & 1); 8000c96: 4b08 ldr r3, [pc, #32] @ (8000cb8 ) 8000c98: 781b ldrb r3, [r3, #0] 8000c9a: 08db lsrs r3, r3, #3 8000c9c: b2db uxtb r3, r3 8000c9e: 2201 movs r2, #1 8000ca0: 4013 ands r3, r2 8000ca2: b2da uxtb r2, r3 8000ca4: 2380 movs r3, #128 @ 0x80 8000ca6: 005b lsls r3, r3, #1 8000ca8: 4805 ldr r0, [pc, #20] @ (8000cc0 ) 8000caa: 0019 movs r1, r3 8000cac: f000 fd61 bl 8001772 } } 8000cb0: 46c0 nop @ (mov r8, r8) 8000cb2: 46bd mov sp, r7 8000cb4: bd80 pop {r7, pc} 8000cb6: 46c0 nop @ (mov r8, r8) 8000cb8: 20000121 .word 0x20000121 8000cbc: 20000120 .word 0x20000120 8000cc0: 50000400 .word 0x50000400 8000cc4: 50000800 .word 0x50000800 08000cc8 : void send_interupt(void) { 8000cc8: b580 push {r7, lr} 8000cca: af00 add r7, sp, #0 if (delta != old_delta) { 8000ccc: 4b0c ldr r3, [pc, #48] @ (8000d00 ) 8000cce: 781a ldrb r2, [r3, #0] 8000cd0: 4b0c ldr r3, [pc, #48] @ (8000d04 ) 8000cd2: 781b ldrb r3, [r3, #0] 8000cd4: 429a cmp r2, r3 8000cd6: d010 beq.n 8000cfa old_delta = delta; 8000cd8: 4b09 ldr r3, [pc, #36] @ (8000d00 ) 8000cda: 781a ldrb r2, [r3, #0] 8000cdc: 4b09 ldr r3, [pc, #36] @ (8000d04 ) 8000cde: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(INT_GPIO_Port, INT_Pin, delta == 0); 8000ce0: 4b07 ldr r3, [pc, #28] @ (8000d00 ) 8000ce2: 781b ldrb r3, [r3, #0] 8000ce4: 425a negs r2, r3 8000ce6: 4153 adcs r3, r2 8000ce8: b2db uxtb r3, r3 8000cea: 001a movs r2, r3 8000cec: 2380 movs r3, #128 @ 0x80 8000cee: 00d9 lsls r1, r3, #3 8000cf0: 23a0 movs r3, #160 @ 0xa0 8000cf2: 05db lsls r3, r3, #23 8000cf4: 0018 movs r0, r3 8000cf6: f000 fd3c bl 8001772 } } 8000cfa: 46c0 nop @ (mov r8, r8) 8000cfc: 46bd mov sp, r7 8000cfe: bd80 pop {r7, pc} 8000d00: 20000119 .word 0x20000119 8000d04: 20000118 .word 0x20000118 08000d08 : uint32_t old_tick; void handle_strike(void) { 8000d08: b580 push {r7, lr} 8000d0a: b084 sub sp, #16 8000d0c: af00 add r7, sp, #0 if (strike_issued && (strike_at == 0)) { 8000d0e: 4b2c ldr r3, [pc, #176] @ (8000dc0 ) 8000d10: 781b ldrb r3, [r3, #0] 8000d12: 2b00 cmp r3, #0 8000d14: d019 beq.n 8000d4a 8000d16: 4b2b ldr r3, [pc, #172] @ (8000dc4 ) 8000d18: 681b ldr r3, [r3, #0] 8000d1a: 2b00 cmp r3, #0 8000d1c: d115 bne.n 8000d4a strike_issued = false; 8000d1e: 4b28 ldr r3, [pc, #160] @ (8000dc0 ) 8000d20: 2200 movs r2, #0 8000d22: 701a strb r2, [r3, #0] strike_at = HAL_GetTick(); 8000d24: f000 fa30 bl 8001188 8000d28: 0002 movs r2, r0 8000d2a: 4b26 ldr r3, [pc, #152] @ (8000dc4 ) 8000d2c: 601a str r2, [r3, #0] // start the buzzer and set the led relay_buzz |= 1 << BUZZ_BIT_IDX; 8000d2e: 4b26 ldr r3, [pc, #152] @ (8000dc8 ) 8000d30: 781b ldrb r3, [r3, #0] 8000d32: 2201 movs r2, #1 8000d34: 4313 orrs r3, r2 8000d36: b2da uxtb r2, r3 8000d38: 4b23 ldr r3, [pc, #140] @ (8000dc8 ) 8000d3a: 701a strb r2, [r3, #0] leds |= 1 << 3; 8000d3c: 4b23 ldr r3, [pc, #140] @ (8000dcc ) 8000d3e: 781b ldrb r3, [r3, #0] 8000d40: 2208 movs r2, #8 8000d42: 4313 orrs r3, r2 8000d44: b2da uxtb r2, r3 8000d46: 4b21 ldr r3, [pc, #132] @ (8000dcc ) 8000d48: 701a strb r2, [r3, #0] } if (strike_at == 0) { 8000d4a: 4b1e ldr r3, [pc, #120] @ (8000dc4 ) 8000d4c: 681b ldr r3, [r3, #0] 8000d4e: 2b00 cmp r3, #0 8000d50: d031 beq.n 8000db6 return; } uint32_t now = HAL_GetTick(); 8000d52: f000 fa19 bl 8001188 8000d56: 0003 movs r3, r0 8000d58: 60fb str r3, [r7, #12] uint32_t buzz_threshold = strike_at + strike_buzz_len; 8000d5a: 4b1d ldr r3, [pc, #116] @ (8000dd0 ) 8000d5c: 881b ldrh r3, [r3, #0] 8000d5e: 001a movs r2, r3 8000d60: 4b18 ldr r3, [pc, #96] @ (8000dc4 ) 8000d62: 681b ldr r3, [r3, #0] 8000d64: 18d3 adds r3, r2, r3 8000d66: 60bb str r3, [r7, #8] if (now > buzz_threshold && old_tick <= buzz_threshold) { 8000d68: 68fa ldr r2, [r7, #12] 8000d6a: 68bb ldr r3, [r7, #8] 8000d6c: 429a cmp r2, r3 8000d6e: d907 bls.n 8000d80 8000d70: 4b18 ldr r3, [pc, #96] @ (8000dd4 ) 8000d72: 681b ldr r3, [r3, #0] 8000d74: 68ba ldr r2, [r7, #8] 8000d76: 429a cmp r2, r3 8000d78: d302 bcc.n 8000d80 // stop buzzing, start the relay relay_buzz = (1 << RELAY_BIT_IDX); 8000d7a: 4b13 ldr r3, [pc, #76] @ (8000dc8 ) 8000d7c: 2202 movs r2, #2 8000d7e: 701a strb r2, [r3, #0] } uint32_t relay_threshold = buzz_threshold + strike_relay_len; 8000d80: 4b15 ldr r3, [pc, #84] @ (8000dd8 ) 8000d82: 881b ldrh r3, [r3, #0] 8000d84: 001a movs r2, r3 8000d86: 68bb ldr r3, [r7, #8] 8000d88: 189b adds r3, r3, r2 8000d8a: 607b str r3, [r7, #4] if (now > relay_threshold) { 8000d8c: 68fa ldr r2, [r7, #12] 8000d8e: 687b ldr r3, [r7, #4] 8000d90: 429a cmp r2, r3 8000d92: d90c bls.n 8000dae // stop the strike strike_at = 0; 8000d94: 4b0b ldr r3, [pc, #44] @ (8000dc4 ) 8000d96: 2200 movs r2, #0 8000d98: 601a str r2, [r3, #0] relay_buzz = 0; 8000d9a: 4b0b ldr r3, [pc, #44] @ (8000dc8 ) 8000d9c: 2200 movs r2, #0 8000d9e: 701a strb r2, [r3, #0] leds &= ~(1 << 3); 8000da0: 4b0a ldr r3, [pc, #40] @ (8000dcc ) 8000da2: 781b ldrb r3, [r3, #0] 8000da4: 2208 movs r2, #8 8000da6: 4393 bics r3, r2 8000da8: b2da uxtb r2, r3 8000daa: 4b08 ldr r3, [pc, #32] @ (8000dcc ) 8000dac: 701a strb r2, [r3, #0] } old_tick = now; 8000dae: 4b09 ldr r3, [pc, #36] @ (8000dd4 ) 8000db0: 68fa ldr r2, [r7, #12] 8000db2: 601a str r2, [r3, #0] 8000db4: e000 b.n 8000db8 return; 8000db6: 46c0 nop @ (mov r8, r8) } 8000db8: 46bd mov sp, r7 8000dba: b004 add sp, #16 8000dbc: bd80 pop {r7, pc} 8000dbe: 46c0 nop @ (mov r8, r8) 8000dc0: 20000122 .word 0x20000122 8000dc4: 20000124 .word 0x20000124 8000dc8: 2000011f .word 0x2000011f 8000dcc: 20000121 .word 0x20000121 8000dd0: 20000000 .word 0x20000000 8000dd4: 20000134 .word 0x20000134 8000dd8: 20000002 .word 0x20000002 08000ddc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000ddc: b580 push {r7, lr} 8000dde: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000de0: b672 cpsid i } 8000de2: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000de4: 46c0 nop @ (mov r8, r8) 8000de6: e7fd b.n 8000de4 08000de8 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000de8: b580 push {r7, lr} 8000dea: b082 sub sp, #8 8000dec: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000dee: 4b11 ldr r3, [pc, #68] @ (8000e34 ) 8000df0: 6c1a ldr r2, [r3, #64] @ 0x40 8000df2: 4b10 ldr r3, [pc, #64] @ (8000e34 ) 8000df4: 2101 movs r1, #1 8000df6: 430a orrs r2, r1 8000df8: 641a str r2, [r3, #64] @ 0x40 8000dfa: 4b0e ldr r3, [pc, #56] @ (8000e34 ) 8000dfc: 6c1b ldr r3, [r3, #64] @ 0x40 8000dfe: 2201 movs r2, #1 8000e00: 4013 ands r3, r2 8000e02: 607b str r3, [r7, #4] 8000e04: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000e06: 4b0b ldr r3, [pc, #44] @ (8000e34 ) 8000e08: 6bda ldr r2, [r3, #60] @ 0x3c 8000e0a: 4b0a ldr r3, [pc, #40] @ (8000e34 ) 8000e0c: 2180 movs r1, #128 @ 0x80 8000e0e: 0549 lsls r1, r1, #21 8000e10: 430a orrs r2, r1 8000e12: 63da str r2, [r3, #60] @ 0x3c 8000e14: 4b07 ldr r3, [pc, #28] @ (8000e34 ) 8000e16: 6bda ldr r2, [r3, #60] @ 0x3c 8000e18: 2380 movs r3, #128 @ 0x80 8000e1a: 055b lsls r3, r3, #21 8000e1c: 4013 ands r3, r2 8000e1e: 603b str r3, [r7, #0] 8000e20: 683b ldr r3, [r7, #0] /* System interrupt init*/ /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); 8000e22: 23c0 movs r3, #192 @ 0xc0 8000e24: 00db lsls r3, r3, #3 8000e26: 0018 movs r0, r3 8000e28: f000 f9b8 bl 800119c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e2c: 46c0 nop @ (mov r8, r8) 8000e2e: 46bd mov sp, r7 8000e30: b002 add sp, #8 8000e32: bd80 pop {r7, pc} 8000e34: 40021000 .word 0x40021000 08000e38 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8000e38: b590 push {r4, r7, lr} 8000e3a: b091 sub sp, #68 @ 0x44 8000e3c: af00 add r7, sp, #0 8000e3e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e40: 232c movs r3, #44 @ 0x2c 8000e42: 18fb adds r3, r7, r3 8000e44: 0018 movs r0, r3 8000e46: 2314 movs r3, #20 8000e48: 001a movs r2, r3 8000e4a: 2100 movs r1, #0 8000e4c: f003 fe52 bl 8004af4 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000e50: 2410 movs r4, #16 8000e52: 193b adds r3, r7, r4 8000e54: 0018 movs r0, r3 8000e56: 231c movs r3, #28 8000e58: 001a movs r2, r3 8000e5a: 2100 movs r1, #0 8000e5c: f003 fe4a bl 8004af4 if(hi2c->Instance==I2C1) 8000e60: 687b ldr r3, [r7, #4] 8000e62: 681b ldr r3, [r3, #0] 8000e64: 4a26 ldr r2, [pc, #152] @ (8000f00 ) 8000e66: 4293 cmp r3, r2 8000e68: d145 bne.n 8000ef6 /* USER CODE END I2C1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; 8000e6a: 193b adds r3, r7, r4 8000e6c: 2220 movs r2, #32 8000e6e: 601a str r2, [r3, #0] PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; 8000e70: 193b adds r3, r7, r4 8000e72: 2200 movs r2, #0 8000e74: 60da str r2, [r3, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000e76: 193b adds r3, r7, r4 8000e78: 0018 movs r0, r3 8000e7a: f002 ffbf bl 8003dfc 8000e7e: 1e03 subs r3, r0, #0 8000e80: d001 beq.n 8000e86 { Error_Handler(); 8000e82: f7ff ffab bl 8000ddc } __HAL_RCC_GPIOB_CLK_ENABLE(); 8000e86: 4b1f ldr r3, [pc, #124] @ (8000f04 ) 8000e88: 6b5a ldr r2, [r3, #52] @ 0x34 8000e8a: 4b1e ldr r3, [pc, #120] @ (8000f04 ) 8000e8c: 2102 movs r1, #2 8000e8e: 430a orrs r2, r1 8000e90: 635a str r2, [r3, #52] @ 0x34 8000e92: 4b1c ldr r3, [pc, #112] @ (8000f04 ) 8000e94: 6b5b ldr r3, [r3, #52] @ 0x34 8000e96: 2202 movs r2, #2 8000e98: 4013 ands r3, r2 8000e9a: 60fb str r3, [r7, #12] 8000e9c: 68fb ldr r3, [r7, #12] /**I2C1 GPIO Configuration PB6 ------> I2C1_SCL PB7 ------> I2C1_SDA */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8000e9e: 212c movs r1, #44 @ 0x2c 8000ea0: 187b adds r3, r7, r1 8000ea2: 22c0 movs r2, #192 @ 0xc0 8000ea4: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000ea6: 187b adds r3, r7, r1 8000ea8: 2212 movs r2, #18 8000eaa: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000eac: 187b adds r3, r7, r1 8000eae: 2200 movs r2, #0 8000eb0: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000eb2: 187b adds r3, r7, r1 8000eb4: 2200 movs r2, #0 8000eb6: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF6_I2C1; 8000eb8: 187b adds r3, r7, r1 8000eba: 2206 movs r2, #6 8000ebc: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000ebe: 187b adds r3, r7, r1 8000ec0: 4a11 ldr r2, [pc, #68] @ (8000f08 ) 8000ec2: 0019 movs r1, r3 8000ec4: 0010 movs r0, r2 8000ec6: f000 fad3 bl 8001470 /* Peripheral clock enable */ __HAL_RCC_I2C1_CLK_ENABLE(); 8000eca: 4b0e ldr r3, [pc, #56] @ (8000f04 ) 8000ecc: 6bda ldr r2, [r3, #60] @ 0x3c 8000ece: 4b0d ldr r3, [pc, #52] @ (8000f04 ) 8000ed0: 2180 movs r1, #128 @ 0x80 8000ed2: 0389 lsls r1, r1, #14 8000ed4: 430a orrs r2, r1 8000ed6: 63da str r2, [r3, #60] @ 0x3c 8000ed8: 4b0a ldr r3, [pc, #40] @ (8000f04 ) 8000eda: 6bda ldr r2, [r3, #60] @ 0x3c 8000edc: 2380 movs r3, #128 @ 0x80 8000ede: 039b lsls r3, r3, #14 8000ee0: 4013 ands r3, r2 8000ee2: 60bb str r3, [r7, #8] 8000ee4: 68bb ldr r3, [r7, #8] /* I2C1 interrupt Init */ HAL_NVIC_SetPriority(I2C1_IRQn, 0, 0); 8000ee6: 2200 movs r2, #0 8000ee8: 2100 movs r1, #0 8000eea: 2017 movs r0, #23 8000eec: f000 fa18 bl 8001320 HAL_NVIC_EnableIRQ(I2C1_IRQn); 8000ef0: 2017 movs r0, #23 8000ef2: f000 fa2a bl 800134a /* USER CODE BEGIN I2C1_MspInit 1 */ /* USER CODE END I2C1_MspInit 1 */ } } 8000ef6: 46c0 nop @ (mov r8, r8) 8000ef8: 46bd mov sp, r7 8000efa: b011 add sp, #68 @ 0x44 8000efc: bd90 pop {r4, r7, pc} 8000efe: 46c0 nop @ (mov r8, r8) 8000f00: 40005400 .word 0x40005400 8000f04: 40021000 .word 0x40021000 8000f08: 50000400 .word 0x50000400 08000f0c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8000f0c: b590 push {r4, r7, lr} 8000f0e: b091 sub sp, #68 @ 0x44 8000f10: af00 add r7, sp, #0 8000f12: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f14: 232c movs r3, #44 @ 0x2c 8000f16: 18fb adds r3, r7, r3 8000f18: 0018 movs r0, r3 8000f1a: 2314 movs r3, #20 8000f1c: 001a movs r2, r3 8000f1e: 2100 movs r1, #0 8000f20: f003 fde8 bl 8004af4 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8000f24: 2410 movs r4, #16 8000f26: 193b adds r3, r7, r4 8000f28: 0018 movs r0, r3 8000f2a: 231c movs r3, #28 8000f2c: 001a movs r2, r3 8000f2e: 2100 movs r1, #0 8000f30: f003 fde0 bl 8004af4 if(huart->Instance==USART2) 8000f34: 687b ldr r3, [r7, #4] 8000f36: 681b ldr r3, [r3, #0] 8000f38: 4a22 ldr r2, [pc, #136] @ (8000fc4 ) 8000f3a: 4293 cmp r3, r2 8000f3c: d13e bne.n 8000fbc /* USER CODE END USART2_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; 8000f3e: 193b adds r3, r7, r4 8000f40: 2202 movs r2, #2 8000f42: 601a str r2, [r3, #0] PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; 8000f44: 193b adds r3, r7, r4 8000f46: 2200 movs r2, #0 8000f48: 609a str r2, [r3, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8000f4a: 193b adds r3, r7, r4 8000f4c: 0018 movs r0, r3 8000f4e: f002 ff55 bl 8003dfc 8000f52: 1e03 subs r3, r0, #0 8000f54: d001 beq.n 8000f5a { Error_Handler(); 8000f56: f7ff ff41 bl 8000ddc } /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); 8000f5a: 4b1b ldr r3, [pc, #108] @ (8000fc8 ) 8000f5c: 6bda ldr r2, [r3, #60] @ 0x3c 8000f5e: 4b1a ldr r3, [pc, #104] @ (8000fc8 ) 8000f60: 2180 movs r1, #128 @ 0x80 8000f62: 0289 lsls r1, r1, #10 8000f64: 430a orrs r2, r1 8000f66: 63da str r2, [r3, #60] @ 0x3c 8000f68: 4b17 ldr r3, [pc, #92] @ (8000fc8 ) 8000f6a: 6bda ldr r2, [r3, #60] @ 0x3c 8000f6c: 2380 movs r3, #128 @ 0x80 8000f6e: 029b lsls r3, r3, #10 8000f70: 4013 ands r3, r2 8000f72: 60fb str r3, [r7, #12] 8000f74: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f76: 4b14 ldr r3, [pc, #80] @ (8000fc8 ) 8000f78: 6b5a ldr r2, [r3, #52] @ 0x34 8000f7a: 4b13 ldr r3, [pc, #76] @ (8000fc8 ) 8000f7c: 2101 movs r1, #1 8000f7e: 430a orrs r2, r1 8000f80: 635a str r2, [r3, #52] @ 0x34 8000f82: 4b11 ldr r3, [pc, #68] @ (8000fc8 ) 8000f84: 6b5b ldr r3, [r3, #52] @ 0x34 8000f86: 2201 movs r2, #1 8000f88: 4013 ands r3, r2 8000f8a: 60bb str r3, [r7, #8] 8000f8c: 68bb ldr r3, [r7, #8] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = TX_Pin|RX_Pin; 8000f8e: 212c movs r1, #44 @ 0x2c 8000f90: 187b adds r3, r7, r1 8000f92: 220c movs r2, #12 8000f94: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000f96: 187b adds r3, r7, r1 8000f98: 2202 movs r2, #2 8000f9a: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000f9c: 187b adds r3, r7, r1 8000f9e: 2200 movs r2, #0 8000fa0: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000fa2: 187b adds r3, r7, r1 8000fa4: 2200 movs r2, #0 8000fa6: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; 8000fa8: 187b adds r3, r7, r1 8000faa: 2201 movs r2, #1 8000fac: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000fae: 187a adds r2, r7, r1 8000fb0: 23a0 movs r3, #160 @ 0xa0 8000fb2: 05db lsls r3, r3, #23 8000fb4: 0011 movs r1, r2 8000fb6: 0018 movs r0, r3 8000fb8: f000 fa5a bl 8001470 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8000fbc: 46c0 nop @ (mov r8, r8) 8000fbe: 46bd mov sp, r7 8000fc0: b011 add sp, #68 @ 0x44 8000fc2: bd90 pop {r4, r7, pc} 8000fc4: 40004400 .word 0x40004400 8000fc8: 40021000 .word 0x40021000 08000fcc : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000fcc: b580 push {r7, lr} 8000fce: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000fd0: 46c0 nop @ (mov r8, r8) 8000fd2: e7fd b.n 8000fd0 08000fd4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000fd4: b580 push {r7, lr} 8000fd6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000fd8: 46c0 nop @ (mov r8, r8) 8000fda: e7fd b.n 8000fd8 08000fdc : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8000fdc: b580 push {r7, lr} 8000fde: af00 add r7, sp, #0 /* USER CODE END SVC_IRQn 0 */ /* USER CODE BEGIN SVC_IRQn 1 */ /* USER CODE END SVC_IRQn 1 */ } 8000fe0: 46c0 nop @ (mov r8, r8) 8000fe2: 46bd mov sp, r7 8000fe4: bd80 pop {r7, pc} 08000fe6 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8000fe6: b580 push {r7, lr} 8000fe8: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8000fea: 46c0 nop @ (mov r8, r8) 8000fec: 46bd mov sp, r7 8000fee: bd80 pop {r7, pc} 08000ff0 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8000ff0: b580 push {r7, lr} 8000ff2: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8000ff4: f000 f8b6 bl 8001164 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8000ff8: 46c0 nop @ (mov r8, r8) 8000ffa: 46bd mov sp, r7 8000ffc: bd80 pop {r7, pc} ... 08001000 : /** * @brief This function handles I2C1 event global interrupt / I2C1 wake-up interrupt through EXTI line 23. */ void I2C1_IRQHandler(void) { 8001000: b580 push {r7, lr} 8001002: af00 add r7, sp, #0 /* USER CODE BEGIN I2C1_IRQn 0 */ /* USER CODE END I2C1_IRQn 0 */ if (hi2c1.Instance->ISR & (I2C_FLAG_BERR | I2C_FLAG_ARLO | I2C_FLAG_OVR)) { 8001004: 4b09 ldr r3, [pc, #36] @ (800102c ) 8001006: 681b ldr r3, [r3, #0] 8001008: 699a ldr r2, [r3, #24] 800100a: 23e0 movs r3, #224 @ 0xe0 800100c: 00db lsls r3, r3, #3 800100e: 4013 ands r3, r2 8001010: d004 beq.n 800101c HAL_I2C_ER_IRQHandler(&hi2c1); 8001012: 4b06 ldr r3, [pc, #24] @ (800102c ) 8001014: 0018 movs r0, r3 8001016: f000 fe2d bl 8001c74 HAL_I2C_EV_IRQHandler(&hi2c1); } /* USER CODE BEGIN I2C1_IRQn 1 */ /* USER CODE END I2C1_IRQn 1 */ } 800101a: e003 b.n 8001024 HAL_I2C_EV_IRQHandler(&hi2c1); 800101c: 4b03 ldr r3, [pc, #12] @ (800102c ) 800101e: 0018 movs r0, r3 8001020: f000 fe0e bl 8001c40 } 8001024: 46c0 nop @ (mov r8, r8) 8001026: 46bd mov sp, r7 8001028: bd80 pop {r7, pc} 800102a: 46c0 nop @ (mov r8, r8) 800102c: 20000030 .word 0x20000030 08001030 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 8001030: b580 push {r7, lr} 8001032: af00 add r7, sp, #0 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001034: 46c0 nop @ (mov r8, r8) 8001036: 46bd mov sp, r7 8001038: bd80 pop {r7, pc} ... 0800103c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 800103c: 480d ldr r0, [pc, #52] @ (8001074 ) mov sp, r0 /* set stack pointer */ 800103e: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8001040: f7ff fff6 bl 8001030 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8001044: 480c ldr r0, [pc, #48] @ (8001078 ) ldr r1, =_edata 8001046: 490d ldr r1, [pc, #52] @ (800107c ) ldr r2, =_sidata 8001048: 4a0d ldr r2, [pc, #52] @ (8001080 ) movs r3, #0 800104a: 2300 movs r3, #0 b LoopCopyDataInit 800104c: e002 b.n 8001054 0800104e : CopyDataInit: ldr r4, [r2, r3] 800104e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001050: 50c4 str r4, [r0, r3] adds r3, r3, #4 8001052: 3304 adds r3, #4 08001054 : LoopCopyDataInit: adds r4, r0, r3 8001054: 18c4 adds r4, r0, r3 cmp r4, r1 8001056: 428c cmp r4, r1 bcc CopyDataInit 8001058: d3f9 bcc.n 800104e /* Zero fill the bss segment. */ ldr r2, =_sbss 800105a: 4a0a ldr r2, [pc, #40] @ (8001084 ) ldr r4, =_ebss 800105c: 4c0a ldr r4, [pc, #40] @ (8001088 ) movs r3, #0 800105e: 2300 movs r3, #0 b LoopFillZerobss 8001060: e001 b.n 8001066 08001062 : FillZerobss: str r3, [r2] 8001062: 6013 str r3, [r2, #0] adds r2, r2, #4 8001064: 3204 adds r2, #4 08001066 : LoopFillZerobss: cmp r2, r4 8001066: 42a2 cmp r2, r4 bcc FillZerobss 8001068: d3fb bcc.n 8001062 /* Call static constructors */ bl __libc_init_array 800106a: f003 fd4b bl 8004b04 <__libc_init_array> /* Call the application s entry point.*/ bl main 800106e: f7ff f9bd bl 80003ec
08001072 : LoopForever: b LoopForever 8001072: e7fe b.n 8001072 ldr r0, =_estack 8001074: 20009000 .word 0x20009000 ldr r0, =_sdata 8001078: 20000000 .word 0x20000000 ldr r1, =_edata 800107c: 20000010 .word 0x20000010 ldr r2, =_sidata 8001080: 08004c18 .word 0x08004c18 ldr r2, =_sbss 8001084: 20000010 .word 0x20000010 ldr r4, =_ebss 8001088: 2000013c .word 0x2000013c 0800108c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 800108c: e7fe b.n 800108c ... 08001090 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001090: b580 push {r7, lr} 8001092: b082 sub sp, #8 8001094: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8001096: 1dfb adds r3, r7, #7 8001098: 2200 movs r2, #0 800109a: 701a strb r2, [r3, #0] #if (INSTRUCTION_CACHE_ENABLE == 0U) __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 800109c: 4b0b ldr r3, [pc, #44] @ (80010cc ) 800109e: 681a ldr r2, [r3, #0] 80010a0: 4b0a ldr r3, [pc, #40] @ (80010cc ) 80010a2: 2180 movs r1, #128 @ 0x80 80010a4: 0049 lsls r1, r1, #1 80010a6: 430a orrs r2, r1 80010a8: 601a str r2, [r3, #0] #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 80010aa: 2003 movs r0, #3 80010ac: f000 f810 bl 80010d0 80010b0: 1e03 subs r3, r0, #0 80010b2: d003 beq.n 80010bc { status = HAL_ERROR; 80010b4: 1dfb adds r3, r7, #7 80010b6: 2201 movs r2, #1 80010b8: 701a strb r2, [r3, #0] 80010ba: e001 b.n 80010c0 } else { /* Init the low level hardware */ HAL_MspInit(); 80010bc: f7ff fe94 bl 8000de8 } /* Return function status */ return status; 80010c0: 1dfb adds r3, r7, #7 80010c2: 781b ldrb r3, [r3, #0] } 80010c4: 0018 movs r0, r3 80010c6: 46bd mov sp, r7 80010c8: b002 add sp, #8 80010ca: bd80 pop {r7, pc} 80010cc: 40022000 .word 0x40022000 080010d0 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80010d0: b590 push {r4, r7, lr} 80010d2: b085 sub sp, #20 80010d4: af00 add r7, sp, #0 80010d6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80010d8: 230f movs r3, #15 80010da: 18fb adds r3, r7, r3 80010dc: 2200 movs r2, #0 80010de: 701a strb r2, [r3, #0] /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ if ((uint32_t)uwTickFreq != 0U) 80010e0: 4b1d ldr r3, [pc, #116] @ (8001158 ) 80010e2: 781b ldrb r3, [r3, #0] 80010e4: 2b00 cmp r3, #0 80010e6: d02b beq.n 8001140 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) 80010e8: 4b1c ldr r3, [pc, #112] @ (800115c ) 80010ea: 681c ldr r4, [r3, #0] 80010ec: 4b1a ldr r3, [pc, #104] @ (8001158 ) 80010ee: 781b ldrb r3, [r3, #0] 80010f0: 0019 movs r1, r3 80010f2: 23fa movs r3, #250 @ 0xfa 80010f4: 0098 lsls r0, r3, #2 80010f6: f7ff f803 bl 8000100 <__udivsi3> 80010fa: 0003 movs r3, r0 80010fc: 0019 movs r1, r3 80010fe: 0020 movs r0, r4 8001100: f7fe fffe bl 8000100 <__udivsi3> 8001104: 0003 movs r3, r0 8001106: 0018 movs r0, r3 8001108: f000 f92f bl 800136a 800110c: 1e03 subs r3, r0, #0 800110e: d112 bne.n 8001136 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8001110: 687b ldr r3, [r7, #4] 8001112: 2b03 cmp r3, #3 8001114: d80a bhi.n 800112c { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8001116: 6879 ldr r1, [r7, #4] 8001118: 2301 movs r3, #1 800111a: 425b negs r3, r3 800111c: 2200 movs r2, #0 800111e: 0018 movs r0, r3 8001120: f000 f8fe bl 8001320 uwTickPrio = TickPriority; 8001124: 4b0e ldr r3, [pc, #56] @ (8001160 ) 8001126: 687a ldr r2, [r7, #4] 8001128: 601a str r2, [r3, #0] 800112a: e00d b.n 8001148 } else { status = HAL_ERROR; 800112c: 230f movs r3, #15 800112e: 18fb adds r3, r7, r3 8001130: 2201 movs r2, #1 8001132: 701a strb r2, [r3, #0] 8001134: e008 b.n 8001148 } } else { status = HAL_ERROR; 8001136: 230f movs r3, #15 8001138: 18fb adds r3, r7, r3 800113a: 2201 movs r2, #1 800113c: 701a strb r2, [r3, #0] 800113e: e003 b.n 8001148 } } else { status = HAL_ERROR; 8001140: 230f movs r3, #15 8001142: 18fb adds r3, r7, r3 8001144: 2201 movs r2, #1 8001146: 701a strb r2, [r3, #0] } /* Return function status */ return status; 8001148: 230f movs r3, #15 800114a: 18fb adds r3, r7, r3 800114c: 781b ldrb r3, [r3, #0] } 800114e: 0018 movs r0, r3 8001150: 46bd mov sp, r7 8001152: b005 add sp, #20 8001154: bd90 pop {r4, r7, pc} 8001156: 46c0 nop @ (mov r8, r8) 8001158: 2000000c .word 0x2000000c 800115c: 20000004 .word 0x20000004 8001160: 20000008 .word 0x20000008 08001164 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001164: b580 push {r7, lr} 8001166: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8001168: 4b05 ldr r3, [pc, #20] @ (8001180 ) 800116a: 781b ldrb r3, [r3, #0] 800116c: 001a movs r2, r3 800116e: 4b05 ldr r3, [pc, #20] @ (8001184 ) 8001170: 681b ldr r3, [r3, #0] 8001172: 18d2 adds r2, r2, r3 8001174: 4b03 ldr r3, [pc, #12] @ (8001184 ) 8001176: 601a str r2, [r3, #0] } 8001178: 46c0 nop @ (mov r8, r8) 800117a: 46bd mov sp, r7 800117c: bd80 pop {r7, pc} 800117e: 46c0 nop @ (mov r8, r8) 8001180: 2000000c .word 0x2000000c 8001184: 20000138 .word 0x20000138 08001188 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001188: b580 push {r7, lr} 800118a: af00 add r7, sp, #0 return uwTick; 800118c: 4b02 ldr r3, [pc, #8] @ (8001198 ) 800118e: 681b ldr r3, [r3, #0] } 8001190: 0018 movs r0, r3 8001192: 46bd mov sp, r7 8001194: bd80 pop {r7, pc} 8001196: 46c0 nop @ (mov r8, r8) 8001198: 20000138 .word 0x20000138 0800119c : * @arg @ref SYSCFG_UCPD1_STROBE * @arg @ref SYSCFG_UCPD2_STROBE * @retval None */ void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery) { 800119c: b580 push {r7, lr} 800119e: b082 sub sp, #8 80011a0: af00 add r7, sp, #0 80011a2: 6078 str r0, [r7, #4] assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery)); /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */ MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery); 80011a4: 4b06 ldr r3, [pc, #24] @ (80011c0 ) 80011a6: 681b ldr r3, [r3, #0] 80011a8: 4a06 ldr r2, [pc, #24] @ (80011c4 ) 80011aa: 4013 ands r3, r2 80011ac: 0019 movs r1, r3 80011ae: 4b04 ldr r3, [pc, #16] @ (80011c0 ) 80011b0: 687a ldr r2, [r7, #4] 80011b2: 430a orrs r2, r1 80011b4: 601a str r2, [r3, #0] } 80011b6: 46c0 nop @ (mov r8, r8) 80011b8: 46bd mov sp, r7 80011ba: b002 add sp, #8 80011bc: bd80 pop {r7, pc} 80011be: 46c0 nop @ (mov r8, r8) 80011c0: 40010000 .word 0x40010000 80011c4: fffff9ff .word 0xfffff9ff 080011c8 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 80011c8: b580 push {r7, lr} 80011ca: b082 sub sp, #8 80011cc: af00 add r7, sp, #0 80011ce: 0002 movs r2, r0 80011d0: 1dfb adds r3, r7, #7 80011d2: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80011d4: 1dfb adds r3, r7, #7 80011d6: 781b ldrb r3, [r3, #0] 80011d8: 2b7f cmp r3, #127 @ 0x7f 80011da: d809 bhi.n 80011f0 <__NVIC_EnableIRQ+0x28> { __COMPILER_BARRIER(); NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 80011dc: 1dfb adds r3, r7, #7 80011de: 781b ldrb r3, [r3, #0] 80011e0: 001a movs r2, r3 80011e2: 231f movs r3, #31 80011e4: 401a ands r2, r3 80011e6: 4b04 ldr r3, [pc, #16] @ (80011f8 <__NVIC_EnableIRQ+0x30>) 80011e8: 2101 movs r1, #1 80011ea: 4091 lsls r1, r2 80011ec: 000a movs r2, r1 80011ee: 601a str r2, [r3, #0] __COMPILER_BARRIER(); } } 80011f0: 46c0 nop @ (mov r8, r8) 80011f2: 46bd mov sp, r7 80011f4: b002 add sp, #8 80011f6: bd80 pop {r7, pc} 80011f8: e000e100 .word 0xe000e100 080011fc <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 80011fc: b590 push {r4, r7, lr} 80011fe: b083 sub sp, #12 8001200: af00 add r7, sp, #0 8001202: 0002 movs r2, r0 8001204: 6039 str r1, [r7, #0] 8001206: 1dfb adds r3, r7, #7 8001208: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 800120a: 1dfb adds r3, r7, #7 800120c: 781b ldrb r3, [r3, #0] 800120e: 2b7f cmp r3, #127 @ 0x7f 8001210: d828 bhi.n 8001264 <__NVIC_SetPriority+0x68> { NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001212: 4a2f ldr r2, [pc, #188] @ (80012d0 <__NVIC_SetPriority+0xd4>) 8001214: 1dfb adds r3, r7, #7 8001216: 781b ldrb r3, [r3, #0] 8001218: b25b sxtb r3, r3 800121a: 089b lsrs r3, r3, #2 800121c: 33c0 adds r3, #192 @ 0xc0 800121e: 009b lsls r3, r3, #2 8001220: 589b ldr r3, [r3, r2] 8001222: 1dfa adds r2, r7, #7 8001224: 7812 ldrb r2, [r2, #0] 8001226: 0011 movs r1, r2 8001228: 2203 movs r2, #3 800122a: 400a ands r2, r1 800122c: 00d2 lsls r2, r2, #3 800122e: 21ff movs r1, #255 @ 0xff 8001230: 4091 lsls r1, r2 8001232: 000a movs r2, r1 8001234: 43d2 mvns r2, r2 8001236: 401a ands r2, r3 8001238: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800123a: 683b ldr r3, [r7, #0] 800123c: 019b lsls r3, r3, #6 800123e: 22ff movs r2, #255 @ 0xff 8001240: 401a ands r2, r3 8001242: 1dfb adds r3, r7, #7 8001244: 781b ldrb r3, [r3, #0] 8001246: 0018 movs r0, r3 8001248: 2303 movs r3, #3 800124a: 4003 ands r3, r0 800124c: 00db lsls r3, r3, #3 800124e: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001250: 481f ldr r0, [pc, #124] @ (80012d0 <__NVIC_SetPriority+0xd4>) 8001252: 1dfb adds r3, r7, #7 8001254: 781b ldrb r3, [r3, #0] 8001256: b25b sxtb r3, r3 8001258: 089b lsrs r3, r3, #2 800125a: 430a orrs r2, r1 800125c: 33c0 adds r3, #192 @ 0xc0 800125e: 009b lsls r3, r3, #2 8001260: 501a str r2, [r3, r0] else { SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); } } 8001262: e031 b.n 80012c8 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8001264: 4a1b ldr r2, [pc, #108] @ (80012d4 <__NVIC_SetPriority+0xd8>) 8001266: 1dfb adds r3, r7, #7 8001268: 781b ldrb r3, [r3, #0] 800126a: 0019 movs r1, r3 800126c: 230f movs r3, #15 800126e: 400b ands r3, r1 8001270: 3b08 subs r3, #8 8001272: 089b lsrs r3, r3, #2 8001274: 3306 adds r3, #6 8001276: 009b lsls r3, r3, #2 8001278: 18d3 adds r3, r2, r3 800127a: 3304 adds r3, #4 800127c: 681b ldr r3, [r3, #0] 800127e: 1dfa adds r2, r7, #7 8001280: 7812 ldrb r2, [r2, #0] 8001282: 0011 movs r1, r2 8001284: 2203 movs r2, #3 8001286: 400a ands r2, r1 8001288: 00d2 lsls r2, r2, #3 800128a: 21ff movs r1, #255 @ 0xff 800128c: 4091 lsls r1, r2 800128e: 000a movs r2, r1 8001290: 43d2 mvns r2, r2 8001292: 401a ands r2, r3 8001294: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 8001296: 683b ldr r3, [r7, #0] 8001298: 019b lsls r3, r3, #6 800129a: 22ff movs r2, #255 @ 0xff 800129c: 401a ands r2, r3 800129e: 1dfb adds r3, r7, #7 80012a0: 781b ldrb r3, [r3, #0] 80012a2: 0018 movs r0, r3 80012a4: 2303 movs r3, #3 80012a6: 4003 ands r3, r0 80012a8: 00db lsls r3, r3, #3 80012aa: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80012ac: 4809 ldr r0, [pc, #36] @ (80012d4 <__NVIC_SetPriority+0xd8>) 80012ae: 1dfb adds r3, r7, #7 80012b0: 781b ldrb r3, [r3, #0] 80012b2: 001c movs r4, r3 80012b4: 230f movs r3, #15 80012b6: 4023 ands r3, r4 80012b8: 3b08 subs r3, #8 80012ba: 089b lsrs r3, r3, #2 80012bc: 430a orrs r2, r1 80012be: 3306 adds r3, #6 80012c0: 009b lsls r3, r3, #2 80012c2: 18c3 adds r3, r0, r3 80012c4: 3304 adds r3, #4 80012c6: 601a str r2, [r3, #0] } 80012c8: 46c0 nop @ (mov r8, r8) 80012ca: 46bd mov sp, r7 80012cc: b003 add sp, #12 80012ce: bd90 pop {r4, r7, pc} 80012d0: e000e100 .word 0xe000e100 80012d4: e000ed00 .word 0xe000ed00 080012d8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 80012d8: b580 push {r7, lr} 80012da: b082 sub sp, #8 80012dc: af00 add r7, sp, #0 80012de: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 80012e0: 687b ldr r3, [r7, #4] 80012e2: 1e5a subs r2, r3, #1 80012e4: 2380 movs r3, #128 @ 0x80 80012e6: 045b lsls r3, r3, #17 80012e8: 429a cmp r2, r3 80012ea: d301 bcc.n 80012f0 { return (1UL); /* Reload value impossible */ 80012ec: 2301 movs r3, #1 80012ee: e010 b.n 8001312 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 80012f0: 4b0a ldr r3, [pc, #40] @ (800131c ) 80012f2: 687a ldr r2, [r7, #4] 80012f4: 3a01 subs r2, #1 80012f6: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80012f8: 2301 movs r3, #1 80012fa: 425b negs r3, r3 80012fc: 2103 movs r1, #3 80012fe: 0018 movs r0, r3 8001300: f7ff ff7c bl 80011fc <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8001304: 4b05 ldr r3, [pc, #20] @ (800131c ) 8001306: 2200 movs r2, #0 8001308: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800130a: 4b04 ldr r3, [pc, #16] @ (800131c ) 800130c: 2207 movs r2, #7 800130e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8001310: 2300 movs r3, #0 } 8001312: 0018 movs r0, r3 8001314: 46bd mov sp, r7 8001316: b002 add sp, #8 8001318: bd80 pop {r7, pc} 800131a: 46c0 nop @ (mov r8, r8) 800131c: e000e010 .word 0xe000e010 08001320 : * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001320: b580 push {r7, lr} 8001322: b084 sub sp, #16 8001324: af00 add r7, sp, #0 8001326: 60b9 str r1, [r7, #8] 8001328: 607a str r2, [r7, #4] 800132a: 210f movs r1, #15 800132c: 187b adds r3, r7, r1 800132e: 1c02 adds r2, r0, #0 8001330: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 8001332: 68ba ldr r2, [r7, #8] 8001334: 187b adds r3, r7, r1 8001336: 781b ldrb r3, [r3, #0] 8001338: b25b sxtb r3, r3 800133a: 0011 movs r1, r2 800133c: 0018 movs r0, r3 800133e: f7ff ff5d bl 80011fc <__NVIC_SetPriority> } 8001342: 46c0 nop @ (mov r8, r8) 8001344: 46bd mov sp, r7 8001346: b004 add sp, #16 8001348: bd80 pop {r7, pc} 0800134a : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800134a: b580 push {r7, lr} 800134c: b082 sub sp, #8 800134e: af00 add r7, sp, #0 8001350: 0002 movs r2, r0 8001352: 1dfb adds r3, r7, #7 8001354: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8001356: 1dfb adds r3, r7, #7 8001358: 781b ldrb r3, [r3, #0] 800135a: b25b sxtb r3, r3 800135c: 0018 movs r0, r3 800135e: f7ff ff33 bl 80011c8 <__NVIC_EnableIRQ> } 8001362: 46c0 nop @ (mov r8, r8) 8001364: 46bd mov sp, r7 8001366: b002 add sp, #8 8001368: bd80 pop {r7, pc} 0800136a : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 800136a: b580 push {r7, lr} 800136c: b082 sub sp, #8 800136e: af00 add r7, sp, #0 8001370: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 8001372: 687b ldr r3, [r7, #4] 8001374: 0018 movs r0, r3 8001376: f7ff ffaf bl 80012d8 800137a: 0003 movs r3, r0 } 800137c: 0018 movs r0, r3 800137e: 46bd mov sp, r7 8001380: b002 add sp, #8 8001382: bd80 pop {r7, pc} 08001384 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8001384: b580 push {r7, lr} 8001386: b084 sub sp, #16 8001388: af00 add r7, sp, #0 800138a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800138c: 210f movs r1, #15 800138e: 187b adds r3, r7, r1 8001390: 2200 movs r2, #0 8001392: 701a strb r2, [r3, #0] if (hdma->State != HAL_DMA_STATE_BUSY) 8001394: 687b ldr r3, [r7, #4] 8001396: 2225 movs r2, #37 @ 0x25 8001398: 5c9b ldrb r3, [r3, r2] 800139a: b2db uxtb r3, r3 800139c: 2b02 cmp r3, #2 800139e: d006 beq.n 80013ae { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80013a0: 687b ldr r3, [r7, #4] 80013a2: 2204 movs r2, #4 80013a4: 63da str r2, [r3, #60] @ 0x3c status = HAL_ERROR; 80013a6: 187b adds r3, r7, r1 80013a8: 2201 movs r2, #1 80013aa: 701a strb r2, [r3, #0] 80013ac: e049 b.n 8001442 } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80013ae: 687b ldr r3, [r7, #4] 80013b0: 681b ldr r3, [r3, #0] 80013b2: 681a ldr r2, [r3, #0] 80013b4: 687b ldr r3, [r7, #4] 80013b6: 681b ldr r3, [r3, #0] 80013b8: 210e movs r1, #14 80013ba: 438a bics r2, r1 80013bc: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 80013be: 687b ldr r3, [r7, #4] 80013c0: 681b ldr r3, [r3, #0] 80013c2: 681a ldr r2, [r3, #0] 80013c4: 687b ldr r3, [r7, #4] 80013c6: 681b ldr r3, [r3, #0] 80013c8: 2101 movs r1, #1 80013ca: 438a bics r2, r1 80013cc: 601a str r2, [r3, #0] /* disable the DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80013ce: 687b ldr r3, [r7, #4] 80013d0: 6c5b ldr r3, [r3, #68] @ 0x44 80013d2: 681a ldr r2, [r3, #0] 80013d4: 687b ldr r3, [r7, #4] 80013d6: 6c5b ldr r3, [r3, #68] @ 0x44 80013d8: 491d ldr r1, [pc, #116] @ (8001450 ) 80013da: 400a ands r2, r1 80013dc: 601a str r2, [r3, #0] /* Clear all flags */ #if defined(DMA2) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); 80013de: 4b1d ldr r3, [pc, #116] @ (8001454 ) 80013e0: 6859 ldr r1, [r3, #4] 80013e2: 687b ldr r3, [r7, #4] 80013e4: 6c1b ldr r3, [r3, #64] @ 0x40 80013e6: 221c movs r2, #28 80013e8: 4013 ands r3, r2 80013ea: 2201 movs r2, #1 80013ec: 409a lsls r2, r3 80013ee: 4b19 ldr r3, [pc, #100] @ (8001454 ) 80013f0: 430a orrs r2, r1 80013f2: 605a str r2, [r3, #4] #endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80013f4: 687b ldr r3, [r7, #4] 80013f6: 6c9b ldr r3, [r3, #72] @ 0x48 80013f8: 687a ldr r2, [r7, #4] 80013fa: 6cd2 ldr r2, [r2, #76] @ 0x4c 80013fc: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 80013fe: 687b ldr r3, [r7, #4] 8001400: 6d1b ldr r3, [r3, #80] @ 0x50 8001402: 2b00 cmp r3, #0 8001404: d00c beq.n 8001420 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8001406: 687b ldr r3, [r7, #4] 8001408: 6d1b ldr r3, [r3, #80] @ 0x50 800140a: 681a ldr r2, [r3, #0] 800140c: 687b ldr r3, [r7, #4] 800140e: 6d1b ldr r3, [r3, #80] @ 0x50 8001410: 490f ldr r1, [pc, #60] @ (8001450 ) 8001412: 400a ands r2, r1 8001414: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8001416: 687b ldr r3, [r7, #4] 8001418: 6d5b ldr r3, [r3, #84] @ 0x54 800141a: 687a ldr r2, [r7, #4] 800141c: 6d92 ldr r2, [r2, #88] @ 0x58 800141e: 605a str r2, [r3, #4] } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8001420: 687b ldr r3, [r7, #4] 8001422: 2225 movs r2, #37 @ 0x25 8001424: 2101 movs r1, #1 8001426: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8001428: 687b ldr r3, [r7, #4] 800142a: 2224 movs r2, #36 @ 0x24 800142c: 2100 movs r1, #0 800142e: 5499 strb r1, [r3, r2] /* Call User Abort callback */ if (hdma->XferAbortCallback != NULL) 8001430: 687b ldr r3, [r7, #4] 8001432: 6b9b ldr r3, [r3, #56] @ 0x38 8001434: 2b00 cmp r3, #0 8001436: d004 beq.n 8001442 { hdma->XferAbortCallback(hdma); 8001438: 687b ldr r3, [r7, #4] 800143a: 6b9b ldr r3, [r3, #56] @ 0x38 800143c: 687a ldr r2, [r7, #4] 800143e: 0010 movs r0, r2 8001440: 4798 blx r3 } } return status; 8001442: 230f movs r3, #15 8001444: 18fb adds r3, r7, r3 8001446: 781b ldrb r3, [r3, #0] } 8001448: 0018 movs r0, r3 800144a: 46bd mov sp, r7 800144c: b004 add sp, #16 800144e: bd80 pop {r7, pc} 8001450: fffffeff .word 0xfffffeff 8001454: 40020000 .word 0x40020000 08001458 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { 8001458: b580 push {r7, lr} 800145a: b082 sub sp, #8 800145c: af00 add r7, sp, #0 800145e: 6078 str r0, [r7, #4] /* Return DMA handle state */ return hdma->State; 8001460: 687b ldr r3, [r7, #4] 8001462: 2225 movs r2, #37 @ 0x25 8001464: 5c9b ldrb r3, [r3, r2] 8001466: b2db uxtb r3, r3 } 8001468: 0018 movs r0, r3 800146a: 46bd mov sp, r7 800146c: b002 add sp, #8 800146e: bd80 pop {r7, pc} 08001470 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001470: b580 push {r7, lr} 8001472: b086 sub sp, #24 8001474: af00 add r7, sp, #0 8001476: 6078 str r0, [r7, #4] 8001478: 6039 str r1, [r7, #0] uint32_t position = 0x00u; 800147a: 2300 movs r3, #0 800147c: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) 800147e: e147 b.n 8001710 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1uL << position); 8001480: 683b ldr r3, [r7, #0] 8001482: 681b ldr r3, [r3, #0] 8001484: 2101 movs r1, #1 8001486: 697a ldr r2, [r7, #20] 8001488: 4091 lsls r1, r2 800148a: 000a movs r2, r1 800148c: 4013 ands r3, r2 800148e: 60fb str r3, [r7, #12] if (iocurrent != 0x00u) 8001490: 68fb ldr r3, [r7, #12] 8001492: 2b00 cmp r3, #0 8001494: d100 bne.n 8001498 8001496: e138 b.n 800170a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8001498: 683b ldr r3, [r7, #0] 800149a: 685b ldr r3, [r3, #4] 800149c: 2203 movs r2, #3 800149e: 4013 ands r3, r2 80014a0: 2b01 cmp r3, #1 80014a2: d005 beq.n 80014b0 80014a4: 683b ldr r3, [r7, #0] 80014a6: 685b ldr r3, [r3, #4] 80014a8: 2203 movs r2, #3 80014aa: 4013 ands r3, r2 80014ac: 2b02 cmp r3, #2 80014ae: d130 bne.n 8001512 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80014b0: 687b ldr r3, [r7, #4] 80014b2: 689b ldr r3, [r3, #8] 80014b4: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); 80014b6: 697b ldr r3, [r7, #20] 80014b8: 005b lsls r3, r3, #1 80014ba: 2203 movs r2, #3 80014bc: 409a lsls r2, r3 80014be: 0013 movs r3, r2 80014c0: 43da mvns r2, r3 80014c2: 693b ldr r3, [r7, #16] 80014c4: 4013 ands r3, r2 80014c6: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2u)); 80014c8: 683b ldr r3, [r7, #0] 80014ca: 68da ldr r2, [r3, #12] 80014cc: 697b ldr r3, [r7, #20] 80014ce: 005b lsls r3, r3, #1 80014d0: 409a lsls r2, r3 80014d2: 0013 movs r3, r2 80014d4: 693a ldr r2, [r7, #16] 80014d6: 4313 orrs r3, r2 80014d8: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 80014da: 687b ldr r3, [r7, #4] 80014dc: 693a ldr r2, [r7, #16] 80014de: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 80014e0: 687b ldr r3, [r7, #4] 80014e2: 685b ldr r3, [r3, #4] 80014e4: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 80014e6: 2201 movs r2, #1 80014e8: 697b ldr r3, [r7, #20] 80014ea: 409a lsls r2, r3 80014ec: 0013 movs r3, r2 80014ee: 43da mvns r2, r3 80014f0: 693b ldr r3, [r7, #16] 80014f2: 4013 ands r3, r2 80014f4: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80014f6: 683b ldr r3, [r7, #0] 80014f8: 685b ldr r3, [r3, #4] 80014fa: 091b lsrs r3, r3, #4 80014fc: 2201 movs r2, #1 80014fe: 401a ands r2, r3 8001500: 697b ldr r3, [r7, #20] 8001502: 409a lsls r2, r3 8001504: 0013 movs r3, r2 8001506: 693a ldr r2, [r7, #16] 8001508: 4313 orrs r3, r2 800150a: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 800150c: 687b ldr r3, [r7, #4] 800150e: 693a ldr r2, [r7, #16] 8001510: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001512: 683b ldr r3, [r7, #0] 8001514: 685b ldr r3, [r3, #4] 8001516: 2203 movs r2, #3 8001518: 4013 ands r3, r2 800151a: 2b03 cmp r3, #3 800151c: d017 beq.n 800154e { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800151e: 687b ldr r3, [r7, #4] 8001520: 68db ldr r3, [r3, #12] 8001522: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); 8001524: 697b ldr r3, [r7, #20] 8001526: 005b lsls r3, r3, #1 8001528: 2203 movs r2, #3 800152a: 409a lsls r2, r3 800152c: 0013 movs r3, r2 800152e: 43da mvns r2, r3 8001530: 693b ldr r3, [r7, #16] 8001532: 4013 ands r3, r2 8001534: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2u)); 8001536: 683b ldr r3, [r7, #0] 8001538: 689a ldr r2, [r3, #8] 800153a: 697b ldr r3, [r7, #20] 800153c: 005b lsls r3, r3, #1 800153e: 409a lsls r2, r3 8001540: 0013 movs r3, r2 8001542: 693a ldr r2, [r7, #16] 8001544: 4313 orrs r3, r2 8001546: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8001548: 687b ldr r3, [r7, #4] 800154a: 693a ldr r2, [r7, #16] 800154c: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800154e: 683b ldr r3, [r7, #0] 8001550: 685b ldr r3, [r3, #4] 8001552: 2203 movs r2, #3 8001554: 4013 ands r3, r2 8001556: 2b02 cmp r3, #2 8001558: d123 bne.n 80015a2 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3u]; 800155a: 697b ldr r3, [r7, #20] 800155c: 08da lsrs r2, r3, #3 800155e: 687b ldr r3, [r7, #4] 8001560: 3208 adds r2, #8 8001562: 0092 lsls r2, r2, #2 8001564: 58d3 ldr r3, [r2, r3] 8001566: 613b str r3, [r7, #16] temp &= ~(0xFu << ((position & 0x07u) * 4u)); 8001568: 697b ldr r3, [r7, #20] 800156a: 2207 movs r2, #7 800156c: 4013 ands r3, r2 800156e: 009b lsls r3, r3, #2 8001570: 220f movs r2, #15 8001572: 409a lsls r2, r3 8001574: 0013 movs r3, r2 8001576: 43da mvns r2, r3 8001578: 693b ldr r3, [r7, #16] 800157a: 4013 ands r3, r2 800157c: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); 800157e: 683b ldr r3, [r7, #0] 8001580: 691a ldr r2, [r3, #16] 8001582: 697b ldr r3, [r7, #20] 8001584: 2107 movs r1, #7 8001586: 400b ands r3, r1 8001588: 009b lsls r3, r3, #2 800158a: 409a lsls r2, r3 800158c: 0013 movs r3, r2 800158e: 693a ldr r2, [r7, #16] 8001590: 4313 orrs r3, r2 8001592: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3u] = temp; 8001594: 697b ldr r3, [r7, #20] 8001596: 08da lsrs r2, r3, #3 8001598: 687b ldr r3, [r7, #4] 800159a: 3208 adds r2, #8 800159c: 0092 lsls r2, r2, #2 800159e: 6939 ldr r1, [r7, #16] 80015a0: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80015a2: 687b ldr r3, [r7, #4] 80015a4: 681b ldr r3, [r3, #0] 80015a6: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); 80015a8: 697b ldr r3, [r7, #20] 80015aa: 005b lsls r3, r3, #1 80015ac: 2203 movs r2, #3 80015ae: 409a lsls r2, r3 80015b0: 0013 movs r3, r2 80015b2: 43da mvns r2, r3 80015b4: 693b ldr r3, [r7, #16] 80015b6: 4013 ands r3, r2 80015b8: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); 80015ba: 683b ldr r3, [r7, #0] 80015bc: 685b ldr r3, [r3, #4] 80015be: 2203 movs r2, #3 80015c0: 401a ands r2, r3 80015c2: 697b ldr r3, [r7, #20] 80015c4: 005b lsls r3, r3, #1 80015c6: 409a lsls r2, r3 80015c8: 0013 movs r3, r2 80015ca: 693a ldr r2, [r7, #16] 80015cc: 4313 orrs r3, r2 80015ce: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80015d0: 687b ldr r3, [r7, #4] 80015d2: 693a ldr r2, [r7, #16] 80015d4: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) 80015d6: 683b ldr r3, [r7, #0] 80015d8: 685a ldr r2, [r3, #4] 80015da: 23c0 movs r3, #192 @ 0xc0 80015dc: 029b lsls r3, r3, #10 80015de: 4013 ands r3, r2 80015e0: d100 bne.n 80015e4 80015e2: e092 b.n 800170a { temp = EXTI->EXTICR[position >> 2u]; 80015e4: 4a50 ldr r2, [pc, #320] @ (8001728 ) 80015e6: 697b ldr r3, [r7, #20] 80015e8: 089b lsrs r3, r3, #2 80015ea: 3318 adds r3, #24 80015ec: 009b lsls r3, r3, #2 80015ee: 589b ldr r3, [r3, r2] 80015f0: 613b str r3, [r7, #16] temp &= ~(0x0FuL << (8u * (position & 0x03u))); 80015f2: 697b ldr r3, [r7, #20] 80015f4: 2203 movs r2, #3 80015f6: 4013 ands r3, r2 80015f8: 00db lsls r3, r3, #3 80015fa: 220f movs r2, #15 80015fc: 409a lsls r2, r3 80015fe: 0013 movs r3, r2 8001600: 43da mvns r2, r3 8001602: 693b ldr r3, [r7, #16] 8001604: 4013 ands r3, r2 8001606: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); 8001608: 687a ldr r2, [r7, #4] 800160a: 23a0 movs r3, #160 @ 0xa0 800160c: 05db lsls r3, r3, #23 800160e: 429a cmp r2, r3 8001610: d013 beq.n 800163a 8001612: 687b ldr r3, [r7, #4] 8001614: 4a45 ldr r2, [pc, #276] @ (800172c ) 8001616: 4293 cmp r3, r2 8001618: d00d beq.n 8001636 800161a: 687b ldr r3, [r7, #4] 800161c: 4a44 ldr r2, [pc, #272] @ (8001730 ) 800161e: 4293 cmp r3, r2 8001620: d007 beq.n 8001632 8001622: 687b ldr r3, [r7, #4] 8001624: 4a43 ldr r2, [pc, #268] @ (8001734 ) 8001626: 4293 cmp r3, r2 8001628: d101 bne.n 800162e 800162a: 2303 movs r3, #3 800162c: e006 b.n 800163c 800162e: 2305 movs r3, #5 8001630: e004 b.n 800163c 8001632: 2302 movs r3, #2 8001634: e002 b.n 800163c 8001636: 2301 movs r3, #1 8001638: e000 b.n 800163c 800163a: 2300 movs r3, #0 800163c: 697a ldr r2, [r7, #20] 800163e: 2103 movs r1, #3 8001640: 400a ands r2, r1 8001642: 00d2 lsls r2, r2, #3 8001644: 4093 lsls r3, r2 8001646: 693a ldr r2, [r7, #16] 8001648: 4313 orrs r3, r2 800164a: 613b str r3, [r7, #16] EXTI->EXTICR[position >> 2u] = temp; 800164c: 4936 ldr r1, [pc, #216] @ (8001728 ) 800164e: 697b ldr r3, [r7, #20] 8001650: 089b lsrs r3, r3, #2 8001652: 3318 adds r3, #24 8001654: 009b lsls r3, r3, #2 8001656: 693a ldr r2, [r7, #16] 8001658: 505a str r2, [r3, r1] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800165a: 4b33 ldr r3, [pc, #204] @ (8001728 ) 800165c: 681b ldr r3, [r3, #0] 800165e: 613b str r3, [r7, #16] temp &= ~(iocurrent); 8001660: 68fb ldr r3, [r7, #12] 8001662: 43da mvns r2, r3 8001664: 693b ldr r3, [r7, #16] 8001666: 4013 ands r3, r2 8001668: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) 800166a: 683b ldr r3, [r7, #0] 800166c: 685a ldr r2, [r3, #4] 800166e: 2380 movs r3, #128 @ 0x80 8001670: 035b lsls r3, r3, #13 8001672: 4013 ands r3, r2 8001674: d003 beq.n 800167e { temp |= iocurrent; 8001676: 693a ldr r2, [r7, #16] 8001678: 68fb ldr r3, [r7, #12] 800167a: 4313 orrs r3, r2 800167c: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 800167e: 4b2a ldr r3, [pc, #168] @ (8001728 ) 8001680: 693a ldr r2, [r7, #16] 8001682: 601a str r2, [r3, #0] temp = EXTI->FTSR1; 8001684: 4b28 ldr r3, [pc, #160] @ (8001728 ) 8001686: 685b ldr r3, [r3, #4] 8001688: 613b str r3, [r7, #16] temp &= ~(iocurrent); 800168a: 68fb ldr r3, [r7, #12] 800168c: 43da mvns r2, r3 800168e: 693b ldr r3, [r7, #16] 8001690: 4013 ands r3, r2 8001692: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) 8001694: 683b ldr r3, [r7, #0] 8001696: 685a ldr r2, [r3, #4] 8001698: 2380 movs r3, #128 @ 0x80 800169a: 039b lsls r3, r3, #14 800169c: 4013 ands r3, r2 800169e: d003 beq.n 80016a8 { temp |= iocurrent; 80016a0: 693a ldr r2, [r7, #16] 80016a2: 68fb ldr r3, [r7, #12] 80016a4: 4313 orrs r3, r2 80016a6: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 80016a8: 4b1f ldr r3, [pc, #124] @ (8001728 ) 80016aa: 693a ldr r2, [r7, #16] 80016ac: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI->EMR1; 80016ae: 4a1e ldr r2, [pc, #120] @ (8001728 ) 80016b0: 2384 movs r3, #132 @ 0x84 80016b2: 58d3 ldr r3, [r2, r3] 80016b4: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80016b6: 68fb ldr r3, [r7, #12] 80016b8: 43da mvns r2, r3 80016ba: 693b ldr r3, [r7, #16] 80016bc: 4013 ands r3, r2 80016be: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) 80016c0: 683b ldr r3, [r7, #0] 80016c2: 685a ldr r2, [r3, #4] 80016c4: 2380 movs r3, #128 @ 0x80 80016c6: 029b lsls r3, r3, #10 80016c8: 4013 ands r3, r2 80016ca: d003 beq.n 80016d4 { temp |= iocurrent; 80016cc: 693a ldr r2, [r7, #16] 80016ce: 68fb ldr r3, [r7, #12] 80016d0: 4313 orrs r3, r2 80016d2: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 80016d4: 4914 ldr r1, [pc, #80] @ (8001728 ) 80016d6: 2284 movs r2, #132 @ 0x84 80016d8: 693b ldr r3, [r7, #16] 80016da: 508b str r3, [r1, r2] temp = EXTI->IMR1; 80016dc: 4a12 ldr r2, [pc, #72] @ (8001728 ) 80016de: 2380 movs r3, #128 @ 0x80 80016e0: 58d3 ldr r3, [r2, r3] 80016e2: 613b str r3, [r7, #16] temp &= ~(iocurrent); 80016e4: 68fb ldr r3, [r7, #12] 80016e6: 43da mvns r2, r3 80016e8: 693b ldr r3, [r7, #16] 80016ea: 4013 ands r3, r2 80016ec: 613b str r3, [r7, #16] if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) 80016ee: 683b ldr r3, [r7, #0] 80016f0: 685a ldr r2, [r3, #4] 80016f2: 2380 movs r3, #128 @ 0x80 80016f4: 025b lsls r3, r3, #9 80016f6: 4013 ands r3, r2 80016f8: d003 beq.n 8001702 { temp |= iocurrent; 80016fa: 693a ldr r2, [r7, #16] 80016fc: 68fb ldr r3, [r7, #12] 80016fe: 4313 orrs r3, r2 8001700: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 8001702: 4909 ldr r1, [pc, #36] @ (8001728 ) 8001704: 2280 movs r2, #128 @ 0x80 8001706: 693b ldr r3, [r7, #16] 8001708: 508b str r3, [r1, r2] } } position++; 800170a: 697b ldr r3, [r7, #20] 800170c: 3301 adds r3, #1 800170e: 617b str r3, [r7, #20] while (((GPIO_Init->Pin) >> position) != 0x00u) 8001710: 683b ldr r3, [r7, #0] 8001712: 681a ldr r2, [r3, #0] 8001714: 697b ldr r3, [r7, #20] 8001716: 40da lsrs r2, r3 8001718: 1e13 subs r3, r2, #0 800171a: d000 beq.n 800171e 800171c: e6b0 b.n 8001480 } } 800171e: 46c0 nop @ (mov r8, r8) 8001720: 46c0 nop @ (mov r8, r8) 8001722: 46bd mov sp, r7 8001724: b006 add sp, #24 8001726: bd80 pop {r7, pc} 8001728: 40021800 .word 0x40021800 800172c: 50000400 .word 0x50000400 8001730: 50000800 .word 0x50000800 8001734: 50000c00 .word 0x50000c00 08001738 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8001738: b580 push {r7, lr} 800173a: b084 sub sp, #16 800173c: af00 add r7, sp, #0 800173e: 6078 str r0, [r7, #4] 8001740: 000a movs r2, r1 8001742: 1cbb adds r3, r7, #2 8001744: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00u) 8001746: 687b ldr r3, [r7, #4] 8001748: 691b ldr r3, [r3, #16] 800174a: 1cba adds r2, r7, #2 800174c: 8812 ldrh r2, [r2, #0] 800174e: 4013 ands r3, r2 8001750: d004 beq.n 800175c { bitstatus = GPIO_PIN_SET; 8001752: 230f movs r3, #15 8001754: 18fb adds r3, r7, r3 8001756: 2201 movs r2, #1 8001758: 701a strb r2, [r3, #0] 800175a: e003 b.n 8001764 } else { bitstatus = GPIO_PIN_RESET; 800175c: 230f movs r3, #15 800175e: 18fb adds r3, r7, r3 8001760: 2200 movs r2, #0 8001762: 701a strb r2, [r3, #0] } return bitstatus; 8001764: 230f movs r3, #15 8001766: 18fb adds r3, r7, r3 8001768: 781b ldrb r3, [r3, #0] } 800176a: 0018 movs r0, r3 800176c: 46bd mov sp, r7 800176e: b004 add sp, #16 8001770: bd80 pop {r7, pc} 08001772 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8001772: b580 push {r7, lr} 8001774: b082 sub sp, #8 8001776: af00 add r7, sp, #0 8001778: 6078 str r0, [r7, #4] 800177a: 0008 movs r0, r1 800177c: 0011 movs r1, r2 800177e: 1cbb adds r3, r7, #2 8001780: 1c02 adds r2, r0, #0 8001782: 801a strh r2, [r3, #0] 8001784: 1c7b adds r3, r7, #1 8001786: 1c0a adds r2, r1, #0 8001788: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800178a: 1c7b adds r3, r7, #1 800178c: 781b ldrb r3, [r3, #0] 800178e: 2b00 cmp r3, #0 8001790: d004 beq.n 800179c { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8001792: 1cbb adds r3, r7, #2 8001794: 881a ldrh r2, [r3, #0] 8001796: 687b ldr r3, [r7, #4] 8001798: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 800179a: e003 b.n 80017a4 GPIOx->BRR = (uint32_t)GPIO_Pin; 800179c: 1cbb adds r3, r7, #2 800179e: 881a ldrh r2, [r3, #0] 80017a0: 687b ldr r3, [r7, #4] 80017a2: 629a str r2, [r3, #40] @ 0x28 } 80017a4: 46c0 nop @ (mov r8, r8) 80017a6: 46bd mov sp, r7 80017a8: b002 add sp, #8 80017aa: bd80 pop {r7, pc} 080017ac : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 80017ac: b580 push {r7, lr} 80017ae: b082 sub sp, #8 80017b0: af00 add r7, sp, #0 80017b2: 6078 str r0, [r7, #4] /* Check the I2C handle allocation */ if (hi2c == NULL) 80017b4: 687b ldr r3, [r7, #4] 80017b6: 2b00 cmp r3, #0 80017b8: d101 bne.n 80017be { return HAL_ERROR; 80017ba: 2301 movs r3, #1 80017bc: e08f b.n 80018de assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 80017be: 687b ldr r3, [r7, #4] 80017c0: 2241 movs r2, #65 @ 0x41 80017c2: 5c9b ldrb r3, [r3, r2] 80017c4: b2db uxtb r3, r3 80017c6: 2b00 cmp r3, #0 80017c8: d107 bne.n 80017da { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 80017ca: 687b ldr r3, [r7, #4] 80017cc: 2240 movs r2, #64 @ 0x40 80017ce: 2100 movs r1, #0 80017d0: 5499 strb r1, [r3, r2] /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); 80017d2: 687b ldr r3, [r7, #4] 80017d4: 0018 movs r0, r3 80017d6: f7ff fb2f bl 8000e38 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 80017da: 687b ldr r3, [r7, #4] 80017dc: 2241 movs r2, #65 @ 0x41 80017de: 2124 movs r1, #36 @ 0x24 80017e0: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80017e2: 687b ldr r3, [r7, #4] 80017e4: 681b ldr r3, [r3, #0] 80017e6: 681a ldr r2, [r3, #0] 80017e8: 687b ldr r3, [r7, #4] 80017ea: 681b ldr r3, [r3, #0] 80017ec: 2101 movs r1, #1 80017ee: 438a bics r2, r1 80017f0: 601a str r2, [r3, #0] /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ /* Configure I2Cx: Frequency range */ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; 80017f2: 687b ldr r3, [r7, #4] 80017f4: 685a ldr r2, [r3, #4] 80017f6: 687b ldr r3, [r7, #4] 80017f8: 681b ldr r3, [r3, #0] 80017fa: 493b ldr r1, [pc, #236] @ (80018e8 ) 80017fc: 400a ands r2, r1 80017fe: 611a str r2, [r3, #16] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Disable Own Address1 before set the Own Address1 configuration */ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; 8001800: 687b ldr r3, [r7, #4] 8001802: 681b ldr r3, [r3, #0] 8001804: 689a ldr r2, [r3, #8] 8001806: 687b ldr r3, [r7, #4] 8001808: 681b ldr r3, [r3, #0] 800180a: 4938 ldr r1, [pc, #224] @ (80018ec ) 800180c: 400a ands r2, r1 800180e: 609a str r2, [r3, #8] /* Configure I2Cx: Own Address1 and ack own address1 mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 8001810: 687b ldr r3, [r7, #4] 8001812: 68db ldr r3, [r3, #12] 8001814: 2b01 cmp r3, #1 8001816: d108 bne.n 800182a { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); 8001818: 687b ldr r3, [r7, #4] 800181a: 689a ldr r2, [r3, #8] 800181c: 687b ldr r3, [r7, #4] 800181e: 681b ldr r3, [r3, #0] 8001820: 2180 movs r1, #128 @ 0x80 8001822: 0209 lsls r1, r1, #8 8001824: 430a orrs r2, r1 8001826: 609a str r2, [r3, #8] 8001828: e007 b.n 800183a } else /* I2C_ADDRESSINGMODE_10BIT */ { hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); 800182a: 687b ldr r3, [r7, #4] 800182c: 689a ldr r2, [r3, #8] 800182e: 687b ldr r3, [r7, #4] 8001830: 681b ldr r3, [r3, #0] 8001832: 2184 movs r1, #132 @ 0x84 8001834: 0209 lsls r1, r1, #8 8001836: 430a orrs r2, r1 8001838: 609a str r2, [r3, #8] } /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 800183a: 687b ldr r3, [r7, #4] 800183c: 68db ldr r3, [r3, #12] 800183e: 2b02 cmp r3, #2 8001840: d109 bne.n 8001856 { SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001842: 687b ldr r3, [r7, #4] 8001844: 681b ldr r3, [r3, #0] 8001846: 685a ldr r2, [r3, #4] 8001848: 687b ldr r3, [r7, #4] 800184a: 681b ldr r3, [r3, #0] 800184c: 2180 movs r1, #128 @ 0x80 800184e: 0109 lsls r1, r1, #4 8001850: 430a orrs r2, r1 8001852: 605a str r2, [r3, #4] 8001854: e007 b.n 8001866 } else { /* Clear the I2C ADD10 bit */ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); 8001856: 687b ldr r3, [r7, #4] 8001858: 681b ldr r3, [r3, #0] 800185a: 685a ldr r2, [r3, #4] 800185c: 687b ldr r3, [r7, #4] 800185e: 681b ldr r3, [r3, #0] 8001860: 4923 ldr r1, [pc, #140] @ (80018f0 ) 8001862: 400a ands r2, r1 8001864: 605a str r2, [r3, #4] } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); 8001866: 687b ldr r3, [r7, #4] 8001868: 681b ldr r3, [r3, #0] 800186a: 685a ldr r2, [r3, #4] 800186c: 687b ldr r3, [r7, #4] 800186e: 681b ldr r3, [r3, #0] 8001870: 4920 ldr r1, [pc, #128] @ (80018f4 ) 8001872: 430a orrs r2, r1 8001874: 605a str r2, [r3, #4] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Disable Own Address2 before set the Own Address2 configuration */ hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; 8001876: 687b ldr r3, [r7, #4] 8001878: 681b ldr r3, [r3, #0] 800187a: 68da ldr r2, [r3, #12] 800187c: 687b ldr r3, [r7, #4] 800187e: 681b ldr r3, [r3, #0] 8001880: 491a ldr r1, [pc, #104] @ (80018ec ) 8001882: 400a ands r2, r1 8001884: 60da str r2, [r3, #12] /* Configure I2Cx: Dual mode and Own Address2 */ hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001886: 687b ldr r3, [r7, #4] 8001888: 691a ldr r2, [r3, #16] 800188a: 687b ldr r3, [r7, #4] 800188c: 695b ldr r3, [r3, #20] 800188e: 431a orrs r2, r3 8001890: 0011 movs r1, r2 (hi2c->Init.OwnAddress2Masks << 8)); 8001892: 687b ldr r3, [r7, #4] 8001894: 699b ldr r3, [r3, #24] 8001896: 021a lsls r2, r3, #8 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ 8001898: 687b ldr r3, [r7, #4] 800189a: 681b ldr r3, [r3, #0] 800189c: 430a orrs r2, r1 800189e: 60da str r2, [r3, #12] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); 80018a0: 687b ldr r3, [r7, #4] 80018a2: 69d9 ldr r1, [r3, #28] 80018a4: 687b ldr r3, [r7, #4] 80018a6: 6a1a ldr r2, [r3, #32] 80018a8: 687b ldr r3, [r7, #4] 80018aa: 681b ldr r3, [r3, #0] 80018ac: 430a orrs r2, r1 80018ae: 601a str r2, [r3, #0] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 80018b0: 687b ldr r3, [r7, #4] 80018b2: 681b ldr r3, [r3, #0] 80018b4: 681a ldr r2, [r3, #0] 80018b6: 687b ldr r3, [r7, #4] 80018b8: 681b ldr r3, [r3, #0] 80018ba: 2101 movs r1, #1 80018bc: 430a orrs r2, r1 80018be: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80018c0: 687b ldr r3, [r7, #4] 80018c2: 2200 movs r2, #0 80018c4: 645a str r2, [r3, #68] @ 0x44 hi2c->State = HAL_I2C_STATE_READY; 80018c6: 687b ldr r3, [r7, #4] 80018c8: 2241 movs r2, #65 @ 0x41 80018ca: 2120 movs r1, #32 80018cc: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 80018ce: 687b ldr r3, [r7, #4] 80018d0: 2200 movs r2, #0 80018d2: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 80018d4: 687b ldr r3, [r7, #4] 80018d6: 2242 movs r2, #66 @ 0x42 80018d8: 2100 movs r1, #0 80018da: 5499 strb r1, [r3, r2] return HAL_OK; 80018dc: 2300 movs r3, #0 } 80018de: 0018 movs r0, r3 80018e0: 46bd mov sp, r7 80018e2: b002 add sp, #8 80018e4: bd80 pop {r7, pc} 80018e6: 46c0 nop @ (mov r8, r8) 80018e8: f0ffffff .word 0xf0ffffff 80018ec: ffff7fff .word 0xffff7fff 80018f0: fffff7ff .word 0xfffff7ff 80018f4: 02008000 .word 0x02008000 080018f8 : * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { 80018f8: b580 push {r7, lr} 80018fa: b086 sub sp, #24 80018fc: af00 add r7, sp, #0 80018fe: 60f8 str r0, [r7, #12] 8001900: 60b9 str r1, [r7, #8] 8001902: 603b str r3, [r7, #0] 8001904: 1dbb adds r3, r7, #6 8001906: 801a strh r2, [r3, #0] FlagStatus tmp; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 8001908: 68fb ldr r3, [r7, #12] 800190a: 2241 movs r2, #65 @ 0x41 800190c: 5c9b ldrb r3, [r3, r2] 800190e: b2db uxtb r3, r3 8001910: 001a movs r2, r3 8001912: 2328 movs r3, #40 @ 0x28 8001914: 4013 ands r3, r2 8001916: 2b28 cmp r3, #40 @ 0x28 8001918: d000 beq.n 800191c 800191a: e09f b.n 8001a5c { if ((pData == NULL) || (Size == 0U)) 800191c: 68bb ldr r3, [r7, #8] 800191e: 2b00 cmp r3, #0 8001920: d003 beq.n 800192a 8001922: 1dbb adds r3, r7, #6 8001924: 881b ldrh r3, [r3, #0] 8001926: 2b00 cmp r3, #0 8001928: d105 bne.n 8001936 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 800192a: 68fb ldr r3, [r7, #12] 800192c: 2280 movs r2, #128 @ 0x80 800192e: 0092 lsls r2, r2, #2 8001930: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8001932: 2301 movs r3, #1 8001934: e093 b.n 8001a5e } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 8001936: 4a4c ldr r2, [pc, #304] @ (8001a68 ) 8001938: 68fb ldr r3, [r7, #12] 800193a: 0011 movs r1, r2 800193c: 0018 movs r0, r3 800193e: f001 fc5b bl 80031f8 /* Process Locked */ __HAL_LOCK(hi2c); 8001942: 68fb ldr r3, [r7, #12] 8001944: 2240 movs r2, #64 @ 0x40 8001946: 5c9b ldrb r3, [r3, r2] 8001948: 2b01 cmp r3, #1 800194a: d101 bne.n 8001950 800194c: 2302 movs r3, #2 800194e: e086 b.n 8001a5e 8001950: 68fb ldr r3, [r7, #12] 8001952: 2240 movs r2, #64 @ 0x40 8001954: 2101 movs r1, #1 8001956: 5499 strb r1, [r3, r2] /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave RX state to TX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 8001958: 68fb ldr r3, [r7, #12] 800195a: 2241 movs r2, #65 @ 0x41 800195c: 5c9b ldrb r3, [r3, r2] 800195e: b2db uxtb r3, r3 8001960: 2b2a cmp r3, #42 @ 0x2a 8001962: d12c bne.n 80019be { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8001964: 68fb ldr r3, [r7, #12] 8001966: 2102 movs r1, #2 8001968: 0018 movs r0, r3 800196a: f001 fc45 bl 80031f8 /* Abort DMA Xfer if any */ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 800196e: 68fb ldr r3, [r7, #12] 8001970: 681b ldr r3, [r3, #0] 8001972: 681a ldr r2, [r3, #0] 8001974: 2380 movs r3, #128 @ 0x80 8001976: 021b lsls r3, r3, #8 8001978: 401a ands r2, r3 800197a: 2380 movs r3, #128 @ 0x80 800197c: 021b lsls r3, r3, #8 800197e: 429a cmp r2, r3 8001980: d11d bne.n 80019be { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8001982: 68fb ldr r3, [r7, #12] 8001984: 681b ldr r3, [r3, #0] 8001986: 681a ldr r2, [r3, #0] 8001988: 68fb ldr r3, [r7, #12] 800198a: 681b ldr r3, [r3, #0] 800198c: 4937 ldr r1, [pc, #220] @ (8001a6c ) 800198e: 400a ands r2, r1 8001990: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 8001992: 68fb ldr r3, [r7, #12] 8001994: 6bdb ldr r3, [r3, #60] @ 0x3c 8001996: 2b00 cmp r3, #0 8001998: d011 beq.n 80019be { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 800199a: 68fb ldr r3, [r7, #12] 800199c: 6bdb ldr r3, [r3, #60] @ 0x3c 800199e: 4a34 ldr r2, [pc, #208] @ (8001a70 ) 80019a0: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 80019a2: 68fb ldr r3, [r7, #12] 80019a4: 6bdb ldr r3, [r3, #60] @ 0x3c 80019a6: 0018 movs r0, r3 80019a8: f7ff fcec bl 8001384 80019ac: 1e03 subs r3, r0, #0 80019ae: d006 beq.n 80019be { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 80019b0: 68fb ldr r3, [r7, #12] 80019b2: 6bdb ldr r3, [r3, #60] @ 0x3c 80019b4: 6b9a ldr r2, [r3, #56] @ 0x38 80019b6: 68fb ldr r3, [r7, #12] 80019b8: 6bdb ldr r3, [r3, #60] @ 0x3c 80019ba: 0018 movs r0, r3 80019bc: 4790 blx r2 } } } } hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; 80019be: 68fb ldr r3, [r7, #12] 80019c0: 2241 movs r2, #65 @ 0x41 80019c2: 2129 movs r1, #41 @ 0x29 80019c4: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_SLAVE; 80019c6: 68fb ldr r3, [r7, #12] 80019c8: 2242 movs r2, #66 @ 0x42 80019ca: 2120 movs r1, #32 80019cc: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 80019ce: 68fb ldr r3, [r7, #12] 80019d0: 2200 movs r2, #0 80019d2: 645a str r2, [r3, #68] @ 0x44 /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; 80019d4: 68fb ldr r3, [r7, #12] 80019d6: 681b ldr r3, [r3, #0] 80019d8: 685a ldr r2, [r3, #4] 80019da: 68fb ldr r3, [r7, #12] 80019dc: 681b ldr r3, [r3, #0] 80019de: 4923 ldr r1, [pc, #140] @ (8001a6c ) 80019e0: 400a ands r2, r1 80019e2: 605a str r2, [r3, #4] /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 80019e4: 68fb ldr r3, [r7, #12] 80019e6: 68ba ldr r2, [r7, #8] 80019e8: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 80019ea: 68fb ldr r3, [r7, #12] 80019ec: 1dba adds r2, r7, #6 80019ee: 8812 ldrh r2, [r2, #0] 80019f0: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize = hi2c->XferCount; 80019f2: 68fb ldr r3, [r7, #12] 80019f4: 8d5b ldrh r3, [r3, #42] @ 0x2a 80019f6: b29a uxth r2, r3 80019f8: 68fb ldr r3, [r7, #12] 80019fa: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferOptions = XferOptions; 80019fc: 68fb ldr r3, [r7, #12] 80019fe: 683a ldr r2, [r7, #0] 8001a00: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Slave_ISR_IT; 8001a02: 68fb ldr r3, [r7, #12] 8001a04: 4a1b ldr r2, [pc, #108] @ (8001a74 ) 8001a06: 635a str r2, [r3, #52] @ 0x34 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 8001a08: 68fb ldr r3, [r7, #12] 8001a0a: 681b ldr r3, [r3, #0] 8001a0c: 699b ldr r3, [r3, #24] 8001a0e: 2208 movs r2, #8 8001a10: 4013 ands r3, r2 8001a12: 3b08 subs r3, #8 8001a14: 425a negs r2, r3 8001a16: 4153 adcs r3, r2 8001a18: b2da uxtb r2, r3 8001a1a: 2117 movs r1, #23 8001a1c: 187b adds r3, r7, r1 8001a1e: 701a strb r2, [r3, #0] if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) 8001a20: 68fb ldr r3, [r7, #12] 8001a22: 681b ldr r3, [r3, #0] 8001a24: 699b ldr r3, [r3, #24] 8001a26: 0c1b lsrs r3, r3, #16 8001a28: b2db uxtb r3, r3 8001a2a: 2201 movs r2, #1 8001a2c: 4013 ands r3, r2 8001a2e: b2db uxtb r3, r3 8001a30: 2b01 cmp r3, #1 8001a32: d107 bne.n 8001a44 8001a34: 187b adds r3, r7, r1 8001a36: 781b ldrb r3, [r3, #0] 8001a38: 2b00 cmp r3, #0 8001a3a: d003 beq.n 8001a44 { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8001a3c: 68fb ldr r3, [r7, #12] 8001a3e: 681b ldr r3, [r3, #0] 8001a40: 2208 movs r2, #8 8001a42: 61da str r2, [r3, #28] } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001a44: 68fb ldr r3, [r7, #12] 8001a46: 2240 movs r2, #64 @ 0x40 8001a48: 2100 movs r1, #0 8001a4a: 5499 strb r1, [r3, r2] /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); 8001a4c: 4a06 ldr r2, [pc, #24] @ (8001a68 ) 8001a4e: 68fb ldr r3, [r7, #12] 8001a50: 0011 movs r1, r2 8001a52: 0018 movs r0, r3 8001a54: f001 fb46 bl 80030e4 return HAL_OK; 8001a58: 2300 movs r3, #0 8001a5a: e000 b.n 8001a5e } else { return HAL_ERROR; 8001a5c: 2301 movs r3, #1 } } 8001a5e: 0018 movs r0, r3 8001a60: 46bd mov sp, r7 8001a62: b006 add sp, #24 8001a64: bd80 pop {r7, pc} 8001a66: 46c0 nop @ (mov r8, r8) 8001a68: 00008001 .word 0x00008001 8001a6c: ffff7fff .word 0xffff7fff 8001a70: 08003033 .word 0x08003033 8001a74: 08001d89 .word 0x08001d89 08001a78 : * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { 8001a78: b580 push {r7, lr} 8001a7a: b086 sub sp, #24 8001a7c: af00 add r7, sp, #0 8001a7e: 60f8 str r0, [r7, #12] 8001a80: 60b9 str r1, [r7, #8] 8001a82: 603b str r3, [r7, #0] 8001a84: 1dbb adds r3, r7, #6 8001a86: 801a strh r2, [r3, #0] FlagStatus tmp; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 8001a88: 68fb ldr r3, [r7, #12] 8001a8a: 2241 movs r2, #65 @ 0x41 8001a8c: 5c9b ldrb r3, [r3, r2] 8001a8e: b2db uxtb r3, r3 8001a90: 001a movs r2, r3 8001a92: 2328 movs r3, #40 @ 0x28 8001a94: 4013 ands r3, r2 8001a96: 2b28 cmp r3, #40 @ 0x28 8001a98: d000 beq.n 8001a9c 8001a9a: e09f b.n 8001bdc { if ((pData == NULL) || (Size == 0U)) 8001a9c: 68bb ldr r3, [r7, #8] 8001a9e: 2b00 cmp r3, #0 8001aa0: d003 beq.n 8001aaa 8001aa2: 1dbb adds r3, r7, #6 8001aa4: 881b ldrh r3, [r3, #0] 8001aa6: 2b00 cmp r3, #0 8001aa8: d105 bne.n 8001ab6 { hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; 8001aaa: 68fb ldr r3, [r7, #12] 8001aac: 2280 movs r2, #128 @ 0x80 8001aae: 0092 lsls r2, r2, #2 8001ab0: 645a str r2, [r3, #68] @ 0x44 return HAL_ERROR; 8001ab2: 2301 movs r3, #1 8001ab4: e093 b.n 8001bde } /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 8001ab6: 4a4c ldr r2, [pc, #304] @ (8001be8 ) 8001ab8: 68fb ldr r3, [r7, #12] 8001aba: 0011 movs r1, r2 8001abc: 0018 movs r0, r3 8001abe: f001 fb9b bl 80031f8 /* Process Locked */ __HAL_LOCK(hi2c); 8001ac2: 68fb ldr r3, [r7, #12] 8001ac4: 2240 movs r2, #64 @ 0x40 8001ac6: 5c9b ldrb r3, [r3, r2] 8001ac8: 2b01 cmp r3, #1 8001aca: d101 bne.n 8001ad0 8001acc: 2302 movs r3, #2 8001ace: e086 b.n 8001bde 8001ad0: 68fb ldr r3, [r7, #12] 8001ad2: 2240 movs r2, #64 @ 0x40 8001ad4: 2101 movs r1, #1 8001ad6: 5499 strb r1, [r3, r2] /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ /* and then toggle the HAL slave TX state to RX state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 8001ad8: 68fb ldr r3, [r7, #12] 8001ada: 2241 movs r2, #65 @ 0x41 8001adc: 5c9b ldrb r3, [r3, r2] 8001ade: b2db uxtb r3, r3 8001ae0: 2b29 cmp r3, #41 @ 0x29 8001ae2: d12c bne.n 8001b3e { /* Disable associated Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8001ae4: 68fb ldr r3, [r7, #12] 8001ae6: 2101 movs r1, #1 8001ae8: 0018 movs r0, r3 8001aea: f001 fb85 bl 80031f8 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 8001aee: 68fb ldr r3, [r7, #12] 8001af0: 681b ldr r3, [r3, #0] 8001af2: 681a ldr r2, [r3, #0] 8001af4: 2380 movs r3, #128 @ 0x80 8001af6: 01db lsls r3, r3, #7 8001af8: 401a ands r2, r3 8001afa: 2380 movs r3, #128 @ 0x80 8001afc: 01db lsls r3, r3, #7 8001afe: 429a cmp r2, r3 8001b00: d11d bne.n 8001b3e { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8001b02: 68fb ldr r3, [r7, #12] 8001b04: 681b ldr r3, [r3, #0] 8001b06: 681a ldr r2, [r3, #0] 8001b08: 68fb ldr r3, [r7, #12] 8001b0a: 681b ldr r3, [r3, #0] 8001b0c: 4937 ldr r1, [pc, #220] @ (8001bec ) 8001b0e: 400a ands r2, r1 8001b10: 601a str r2, [r3, #0] /* Abort DMA Xfer if any */ if (hi2c->hdmatx != NULL) 8001b12: 68fb ldr r3, [r7, #12] 8001b14: 6b9b ldr r3, [r3, #56] @ 0x38 8001b16: 2b00 cmp r3, #0 8001b18: d011 beq.n 8001b3e { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 8001b1a: 68fb ldr r3, [r7, #12] 8001b1c: 6b9b ldr r3, [r3, #56] @ 0x38 8001b1e: 4a34 ldr r2, [pc, #208] @ (8001bf0 ) 8001b20: 639a str r2, [r3, #56] @ 0x38 /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 8001b22: 68fb ldr r3, [r7, #12] 8001b24: 6b9b ldr r3, [r3, #56] @ 0x38 8001b26: 0018 movs r0, r3 8001b28: f7ff fc2c bl 8001384 8001b2c: 1e03 subs r3, r0, #0 8001b2e: d006 beq.n 8001b3e { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 8001b30: 68fb ldr r3, [r7, #12] 8001b32: 6b9b ldr r3, [r3, #56] @ 0x38 8001b34: 6b9a ldr r2, [r3, #56] @ 0x38 8001b36: 68fb ldr r3, [r7, #12] 8001b38: 6b9b ldr r3, [r3, #56] @ 0x38 8001b3a: 0018 movs r0, r3 8001b3c: 4790 blx r2 } } } } hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; 8001b3e: 68fb ldr r3, [r7, #12] 8001b40: 2241 movs r2, #65 @ 0x41 8001b42: 212a movs r1, #42 @ 0x2a 8001b44: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_SLAVE; 8001b46: 68fb ldr r3, [r7, #12] 8001b48: 2242 movs r2, #66 @ 0x42 8001b4a: 2120 movs r1, #32 8001b4c: 5499 strb r1, [r3, r2] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8001b4e: 68fb ldr r3, [r7, #12] 8001b50: 2200 movs r2, #0 8001b52: 645a str r2, [r3, #68] @ 0x44 /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; 8001b54: 68fb ldr r3, [r7, #12] 8001b56: 681b ldr r3, [r3, #0] 8001b58: 685a ldr r2, [r3, #4] 8001b5a: 68fb ldr r3, [r7, #12] 8001b5c: 681b ldr r3, [r3, #0] 8001b5e: 4925 ldr r1, [pc, #148] @ (8001bf4 ) 8001b60: 400a ands r2, r1 8001b62: 605a str r2, [r3, #4] /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; 8001b64: 68fb ldr r3, [r7, #12] 8001b66: 68ba ldr r2, [r7, #8] 8001b68: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount = Size; 8001b6a: 68fb ldr r3, [r7, #12] 8001b6c: 1dba adds r2, r7, #6 8001b6e: 8812 ldrh r2, [r2, #0] 8001b70: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize = hi2c->XferCount; 8001b72: 68fb ldr r3, [r7, #12] 8001b74: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001b76: b29a uxth r2, r3 8001b78: 68fb ldr r3, [r7, #12] 8001b7a: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferOptions = XferOptions; 8001b7c: 68fb ldr r3, [r7, #12] 8001b7e: 683a ldr r2, [r7, #0] 8001b80: 62da str r2, [r3, #44] @ 0x2c hi2c->XferISR = I2C_Slave_ISR_IT; 8001b82: 68fb ldr r3, [r7, #12] 8001b84: 4a1c ldr r2, [pc, #112] @ (8001bf8 ) 8001b86: 635a str r2, [r3, #52] @ 0x34 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 8001b88: 68fb ldr r3, [r7, #12] 8001b8a: 681b ldr r3, [r3, #0] 8001b8c: 699b ldr r3, [r3, #24] 8001b8e: 2208 movs r2, #8 8001b90: 4013 ands r3, r2 8001b92: 3b08 subs r3, #8 8001b94: 425a negs r2, r3 8001b96: 4153 adcs r3, r2 8001b98: b2da uxtb r2, r3 8001b9a: 2117 movs r1, #23 8001b9c: 187b adds r3, r7, r1 8001b9e: 701a strb r2, [r3, #0] if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) 8001ba0: 68fb ldr r3, [r7, #12] 8001ba2: 681b ldr r3, [r3, #0] 8001ba4: 699b ldr r3, [r3, #24] 8001ba6: 0c1b lsrs r3, r3, #16 8001ba8: b2db uxtb r3, r3 8001baa: 2201 movs r2, #1 8001bac: 4013 ands r3, r2 8001bae: b2db uxtb r3, r3 8001bb0: 2b00 cmp r3, #0 8001bb2: d107 bne.n 8001bc4 8001bb4: 187b adds r3, r7, r1 8001bb6: 781b ldrb r3, [r3, #0] 8001bb8: 2b00 cmp r3, #0 8001bba: d003 beq.n 8001bc4 { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8001bbc: 68fb ldr r3, [r7, #12] 8001bbe: 681b ldr r3, [r3, #0] 8001bc0: 2208 movs r2, #8 8001bc2: 61da str r2, [r3, #28] } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001bc4: 68fb ldr r3, [r7, #12] 8001bc6: 2240 movs r2, #64 @ 0x40 8001bc8: 2100 movs r1, #0 8001bca: 5499 strb r1, [r3, r2] /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); 8001bcc: 4a06 ldr r2, [pc, #24] @ (8001be8 ) 8001bce: 68fb ldr r3, [r7, #12] 8001bd0: 0011 movs r1, r2 8001bd2: 0018 movs r0, r3 8001bd4: f001 fa86 bl 80030e4 return HAL_OK; 8001bd8: 2300 movs r3, #0 8001bda: e000 b.n 8001bde } else { return HAL_ERROR; 8001bdc: 2301 movs r3, #1 } } 8001bde: 0018 movs r0, r3 8001be0: 46bd mov sp, r7 8001be2: b006 add sp, #24 8001be4: bd80 pop {r7, pc} 8001be6: 46c0 nop @ (mov r8, r8) 8001be8: 00008002 .word 0x00008002 8001bec: ffffbfff .word 0xffffbfff 8001bf0: 08003033 .word 0x08003033 8001bf4: ffff7fff .word 0xffff7fff 8001bf8: 08001d89 .word 0x08001d89 08001bfc : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) { 8001bfc: b580 push {r7, lr} 8001bfe: b082 sub sp, #8 8001c00: af00 add r7, sp, #0 8001c02: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_READY) 8001c04: 687b ldr r3, [r7, #4] 8001c06: 2241 movs r2, #65 @ 0x41 8001c08: 5c9b ldrb r3, [r3, r2] 8001c0a: b2db uxtb r3, r3 8001c0c: 2b20 cmp r3, #32 8001c0e: d10f bne.n 8001c30 { hi2c->State = HAL_I2C_STATE_LISTEN; 8001c10: 687b ldr r3, [r7, #4] 8001c12: 2241 movs r2, #65 @ 0x41 8001c14: 2128 movs r1, #40 @ 0x28 8001c16: 5499 strb r1, [r3, r2] hi2c->XferISR = I2C_Slave_ISR_IT; 8001c18: 687b ldr r3, [r7, #4] 8001c1a: 4a08 ldr r2, [pc, #32] @ (8001c3c ) 8001c1c: 635a str r2, [r3, #52] @ 0x34 /* Enable the Address Match interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8001c1e: 2380 movs r3, #128 @ 0x80 8001c20: 021a lsls r2, r3, #8 8001c22: 687b ldr r3, [r7, #4] 8001c24: 0011 movs r1, r2 8001c26: 0018 movs r0, r3 8001c28: f001 fa5c bl 80030e4 return HAL_OK; 8001c2c: 2300 movs r3, #0 8001c2e: e000 b.n 8001c32 } else { return HAL_BUSY; 8001c30: 2302 movs r3, #2 } } 8001c32: 0018 movs r0, r3 8001c34: 46bd mov sp, r7 8001c36: b002 add sp, #8 8001c38: bd80 pop {r7, pc} 8001c3a: 46c0 nop @ (mov r8, r8) 8001c3c: 08001d89 .word 0x08001d89 08001c40 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ { 8001c40: b580 push {r7, lr} 8001c42: b084 sub sp, #16 8001c44: af00 add r7, sp, #0 8001c46: 6078 str r0, [r7, #4] /* Get current IT Flags and IT sources value */ uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8001c48: 687b ldr r3, [r7, #4] 8001c4a: 681b ldr r3, [r3, #0] 8001c4c: 699b ldr r3, [r3, #24] 8001c4e: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8001c50: 687b ldr r3, [r7, #4] 8001c52: 681b ldr r3, [r3, #0] 8001c54: 681b ldr r3, [r3, #0] 8001c56: 60bb str r3, [r7, #8] /* I2C events treatment -------------------------------------*/ if (hi2c->XferISR != NULL) 8001c58: 687b ldr r3, [r7, #4] 8001c5a: 6b5b ldr r3, [r3, #52] @ 0x34 8001c5c: 2b00 cmp r3, #0 8001c5e: d005 beq.n 8001c6c { hi2c->XferISR(hi2c, itflags, itsources); 8001c60: 687b ldr r3, [r7, #4] 8001c62: 6b5b ldr r3, [r3, #52] @ 0x34 8001c64: 68ba ldr r2, [r7, #8] 8001c66: 68f9 ldr r1, [r7, #12] 8001c68: 6878 ldr r0, [r7, #4] 8001c6a: 4798 blx r3 } } 8001c6c: 46c0 nop @ (mov r8, r8) 8001c6e: 46bd mov sp, r7 8001c70: b004 add sp, #16 8001c72: bd80 pop {r7, pc} 08001c74 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { 8001c74: b580 push {r7, lr} 8001c76: b086 sub sp, #24 8001c78: af00 add r7, sp, #0 8001c7a: 6078 str r0, [r7, #4] uint32_t itflags = READ_REG(hi2c->Instance->ISR); 8001c7c: 687b ldr r3, [r7, #4] 8001c7e: 681b ldr r3, [r3, #0] 8001c80: 699b ldr r3, [r3, #24] 8001c82: 617b str r3, [r7, #20] uint32_t itsources = READ_REG(hi2c->Instance->CR1); 8001c84: 687b ldr r3, [r7, #4] 8001c86: 681b ldr r3, [r3, #0] 8001c88: 681b ldr r3, [r3, #0] 8001c8a: 613b str r3, [r7, #16] uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8001c8c: 697a ldr r2, [r7, #20] 8001c8e: 2380 movs r3, #128 @ 0x80 8001c90: 005b lsls r3, r3, #1 8001c92: 4013 ands r3, r2 8001c94: d00e beq.n 8001cb4 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001c96: 693b ldr r3, [r7, #16] 8001c98: 2280 movs r2, #128 @ 0x80 8001c9a: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ 8001c9c: d00a beq.n 8001cb4 { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; 8001c9e: 687b ldr r3, [r7, #4] 8001ca0: 6c5b ldr r3, [r3, #68] @ 0x44 8001ca2: 2201 movs r2, #1 8001ca4: 431a orrs r2, r3 8001ca6: 687b ldr r3, [r7, #4] 8001ca8: 645a str r2, [r3, #68] @ 0x44 /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 8001caa: 687b ldr r3, [r7, #4] 8001cac: 681b ldr r3, [r3, #0] 8001cae: 2280 movs r2, #128 @ 0x80 8001cb0: 0052 lsls r2, r2, #1 8001cb2: 61da str r2, [r3, #28] } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8001cb4: 697a ldr r2, [r7, #20] 8001cb6: 2380 movs r3, #128 @ 0x80 8001cb8: 00db lsls r3, r3, #3 8001cba: 4013 ands r3, r2 8001cbc: d00e beq.n 8001cdc (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001cbe: 693b ldr r3, [r7, #16] 8001cc0: 2280 movs r2, #128 @ 0x80 8001cc2: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ 8001cc4: d00a beq.n 8001cdc { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; 8001cc6: 687b ldr r3, [r7, #4] 8001cc8: 6c5b ldr r3, [r3, #68] @ 0x44 8001cca: 2208 movs r2, #8 8001ccc: 431a orrs r2, r3 8001cce: 687b ldr r3, [r7, #4] 8001cd0: 645a str r2, [r3, #68] @ 0x44 /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 8001cd2: 687b ldr r3, [r7, #4] 8001cd4: 681b ldr r3, [r3, #0] 8001cd6: 2280 movs r2, #128 @ 0x80 8001cd8: 00d2 lsls r2, r2, #3 8001cda: 61da str r2, [r3, #28] } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8001cdc: 697a ldr r2, [r7, #20] 8001cde: 2380 movs r3, #128 @ 0x80 8001ce0: 009b lsls r3, r3, #2 8001ce2: 4013 ands r3, r2 8001ce4: d00e beq.n 8001d04 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) 8001ce6: 693b ldr r3, [r7, #16] 8001ce8: 2280 movs r2, #128 @ 0x80 8001cea: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ 8001cec: d00a beq.n 8001d04 { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; 8001cee: 687b ldr r3, [r7, #4] 8001cf0: 6c5b ldr r3, [r3, #68] @ 0x44 8001cf2: 2202 movs r2, #2 8001cf4: 431a orrs r2, r3 8001cf6: 687b ldr r3, [r7, #4] 8001cf8: 645a str r2, [r3, #68] @ 0x44 /* Clear ARLO flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 8001cfa: 687b ldr r3, [r7, #4] 8001cfc: 681b ldr r3, [r3, #0] 8001cfe: 2280 movs r2, #128 @ 0x80 8001d00: 0092 lsls r2, r2, #2 8001d02: 61da str r2, [r3, #28] } /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 8001d04: 687b ldr r3, [r7, #4] 8001d06: 6c5b ldr r3, [r3, #68] @ 0x44 8001d08: 60fb str r3, [r7, #12] /* Call the Error Callback in case of Error detected */ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) 8001d0a: 68fb ldr r3, [r7, #12] 8001d0c: 220b movs r2, #11 8001d0e: 4013 ands r3, r2 8001d10: d005 beq.n 8001d1e { I2C_ITError(hi2c, tmperror); 8001d12: 68fa ldr r2, [r7, #12] 8001d14: 687b ldr r3, [r7, #4] 8001d16: 0011 movs r1, r2 8001d18: 0018 movs r0, r3 8001d1a: f001 f83d bl 8002d98 } } 8001d1e: 46c0 nop @ (mov r8, r8) 8001d20: 46bd mov sp, r7 8001d22: b006 add sp, #24 8001d24: bd80 pop {r7, pc} 08001d26 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8001d26: b580 push {r7, lr} 8001d28: b082 sub sp, #8 8001d2a: af00 add r7, sp, #0 8001d2c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterTxCpltCallback could be implemented in the user file */ } 8001d2e: 46c0 nop @ (mov r8, r8) 8001d30: 46bd mov sp, r7 8001d32: b002 add sp, #8 8001d34: bd80 pop {r7, pc} 08001d36 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { 8001d36: b580 push {r7, lr} 8001d38: b082 sub sp, #8 8001d3a: af00 add r7, sp, #0 8001d3c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MasterRxCpltCallback could be implemented in the user file */ } 8001d3e: 46c0 nop @ (mov r8, r8) 8001d40: 46bd mov sp, r7 8001d42: b002 add sp, #8 8001d44: bd80 pop {r7, pc} 08001d46 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { 8001d46: b580 push {r7, lr} 8001d48: b082 sub sp, #8 8001d4a: af00 add r7, sp, #0 8001d4c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemTxCpltCallback could be implemented in the user file */ } 8001d4e: 46c0 nop @ (mov r8, r8) 8001d50: 46bd mov sp, r7 8001d52: b002 add sp, #8 8001d54: bd80 pop {r7, pc} 08001d56 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { 8001d56: b580 push {r7, lr} 8001d58: b082 sub sp, #8 8001d5a: af00 add r7, sp, #0 8001d5c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_MemRxCpltCallback could be implemented in the user file */ } 8001d5e: 46c0 nop @ (mov r8, r8) 8001d60: 46bd mov sp, r7 8001d62: b002 add sp, #8 8001d64: bd80 pop {r7, pc} 08001d66 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { 8001d66: b580 push {r7, lr} 8001d68: b082 sub sp, #8 8001d6a: af00 add r7, sp, #0 8001d6c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_ErrorCallback could be implemented in the user file */ } 8001d6e: 46c0 nop @ (mov r8, r8) 8001d70: 46bd mov sp, r7 8001d72: b002 add sp, #8 8001d74: bd80 pop {r7, pc} 08001d76 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { 8001d76: b580 push {r7, lr} 8001d78: b082 sub sp, #8 8001d7a: af00 add r7, sp, #0 8001d7c: 6078 str r0, [r7, #4] UNUSED(hi2c); /* NOTE : This function should not be modified, when the callback is needed, the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } 8001d7e: 46c0 nop @ (mov r8, r8) 8001d80: 46bd mov sp, r7 8001d82: b002 add sp, #8 8001d84: bd80 pop {r7, pc} ... 08001d88 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8001d88: b580 push {r7, lr} 8001d8a: b086 sub sp, #24 8001d8c: af00 add r7, sp, #0 8001d8e: 60f8 str r0, [r7, #12] 8001d90: 60b9 str r1, [r7, #8] 8001d92: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 8001d94: 68fb ldr r3, [r7, #12] 8001d96: 6adb ldr r3, [r3, #44] @ 0x2c 8001d98: 617b str r3, [r7, #20] uint32_t tmpITFlags = ITFlags; 8001d9a: 68bb ldr r3, [r7, #8] 8001d9c: 613b str r3, [r7, #16] /* Process locked */ __HAL_LOCK(hi2c); 8001d9e: 68fb ldr r3, [r7, #12] 8001da0: 2240 movs r2, #64 @ 0x40 8001da2: 5c9b ldrb r3, [r3, r2] 8001da4: 2b01 cmp r3, #1 8001da6: d101 bne.n 8001dac 8001da8: 2302 movs r3, #2 8001daa: e0e7 b.n 8001f7c 8001dac: 68fb ldr r3, [r7, #12] 8001dae: 2240 movs r2, #64 @ 0x40 8001db0: 2101 movs r1, #1 8001db2: 5499 strb r1, [r3, r2] /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8001db4: 693b ldr r3, [r7, #16] 8001db6: 2220 movs r2, #32 8001db8: 4013 ands r3, r2 8001dba: d00a beq.n 8001dd2 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8001dbc: 687b ldr r3, [r7, #4] 8001dbe: 2220 movs r2, #32 8001dc0: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ 8001dc2: d006 beq.n 8001dd2 { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); 8001dc4: 693a ldr r2, [r7, #16] 8001dc6: 68fb ldr r3, [r7, #12] 8001dc8: 0011 movs r1, r2 8001dca: 0018 movs r0, r3 8001dcc: f000 fe04 bl 80029d8 8001dd0: e0cf b.n 8001f72 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8001dd2: 693b ldr r3, [r7, #16] 8001dd4: 2210 movs r2, #16 8001dd6: 4013 ands r3, r2 8001dd8: d052 beq.n 8001e80 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8001dda: 687b ldr r3, [r7, #4] 8001ddc: 2210 movs r2, #16 8001dde: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8001de0: d04e beq.n 8001e80 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8001de2: 68fb ldr r3, [r7, #12] 8001de4: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001de6: b29b uxth r3, r3 8001de8: 2b00 cmp r3, #0 8001dea: d12d bne.n 8001e48 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8001dec: 68fb ldr r3, [r7, #12] 8001dee: 2241 movs r2, #65 @ 0x41 8001df0: 5c9b ldrb r3, [r3, r2] 8001df2: b2db uxtb r3, r3 8001df4: 2b28 cmp r3, #40 @ 0x28 8001df6: d10b bne.n 8001e10 8001df8: 697a ldr r2, [r7, #20] 8001dfa: 2380 movs r3, #128 @ 0x80 8001dfc: 049b lsls r3, r3, #18 8001dfe: 429a cmp r2, r3 8001e00: d106 bne.n 8001e10 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8001e02: 693a ldr r2, [r7, #16] 8001e04: 68fb ldr r3, [r7, #12] 8001e06: 0011 movs r1, r2 8001e08: 0018 movs r0, r3 8001e0a: f000 ff6d bl 8002ce8 8001e0e: e036 b.n 8001e7e } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8001e10: 68fb ldr r3, [r7, #12] 8001e12: 2241 movs r2, #65 @ 0x41 8001e14: 5c9b ldrb r3, [r3, r2] 8001e16: b2db uxtb r3, r3 8001e18: 2b29 cmp r3, #41 @ 0x29 8001e1a: d110 bne.n 8001e3e 8001e1c: 697b ldr r3, [r7, #20] 8001e1e: 4a59 ldr r2, [pc, #356] @ (8001f84 ) 8001e20: 4293 cmp r3, r2 8001e22: d00c beq.n 8001e3e { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001e24: 68fb ldr r3, [r7, #12] 8001e26: 681b ldr r3, [r3, #0] 8001e28: 2210 movs r2, #16 8001e2a: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8001e2c: 68fb ldr r3, [r7, #12] 8001e2e: 0018 movs r0, r3 8001e30: f001 f8dd bl 8002fee /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8001e34: 68fb ldr r3, [r7, #12] 8001e36: 0018 movs r0, r3 8001e38: f000 fc9c bl 8002774 8001e3c: e01f b.n 8001e7e } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001e3e: 68fb ldr r3, [r7, #12] 8001e40: 681b ldr r3, [r3, #0] 8001e42: 2210 movs r2, #16 8001e44: 61da str r2, [r3, #28] if (hi2c->XferCount == 0U) 8001e46: e091 b.n 8001f6c } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001e48: 68fb ldr r3, [r7, #12] 8001e4a: 681b ldr r3, [r3, #0] 8001e4c: 2210 movs r2, #16 8001e4e: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8001e50: 68fb ldr r3, [r7, #12] 8001e52: 6c5b ldr r3, [r3, #68] @ 0x44 8001e54: 2204 movs r2, #4 8001e56: 431a orrs r2, r3 8001e58: 68fb ldr r3, [r7, #12] 8001e5a: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8001e5c: 697b ldr r3, [r7, #20] 8001e5e: 2b00 cmp r3, #0 8001e60: d005 beq.n 8001e6e 8001e62: 697a ldr r2, [r7, #20] 8001e64: 2380 movs r3, #128 @ 0x80 8001e66: 045b lsls r3, r3, #17 8001e68: 429a cmp r2, r3 8001e6a: d000 beq.n 8001e6e 8001e6c: e07e b.n 8001f6c { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8001e6e: 68fb ldr r3, [r7, #12] 8001e70: 6c5a ldr r2, [r3, #68] @ 0x44 8001e72: 68fb ldr r3, [r7, #12] 8001e74: 0011 movs r1, r2 8001e76: 0018 movs r0, r3 8001e78: f000 ff8e bl 8002d98 if (hi2c->XferCount == 0U) 8001e7c: e076 b.n 8001f6c 8001e7e: e075 b.n 8001f6c } } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 8001e80: 693b ldr r3, [r7, #16] 8001e82: 2204 movs r2, #4 8001e84: 4013 ands r3, r2 8001e86: d02f beq.n 8001ee8 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) 8001e88: 687b ldr r3, [r7, #4] 8001e8a: 2204 movs r2, #4 8001e8c: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ 8001e8e: d02b beq.n 8001ee8 { if (hi2c->XferCount > 0U) 8001e90: 68fb ldr r3, [r7, #12] 8001e92: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001e94: b29b uxth r3, r3 8001e96: 2b00 cmp r3, #0 8001e98: d018 beq.n 8001ecc { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8001e9a: 68fb ldr r3, [r7, #12] 8001e9c: 681b ldr r3, [r3, #0] 8001e9e: 6a5a ldr r2, [r3, #36] @ 0x24 8001ea0: 68fb ldr r3, [r7, #12] 8001ea2: 6a5b ldr r3, [r3, #36] @ 0x24 8001ea4: b2d2 uxtb r2, r2 8001ea6: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8001ea8: 68fb ldr r3, [r7, #12] 8001eaa: 6a5b ldr r3, [r3, #36] @ 0x24 8001eac: 1c5a adds r2, r3, #1 8001eae: 68fb ldr r3, [r7, #12] 8001eb0: 625a str r2, [r3, #36] @ 0x24 hi2c->XferSize--; 8001eb2: 68fb ldr r3, [r7, #12] 8001eb4: 8d1b ldrh r3, [r3, #40] @ 0x28 8001eb6: 3b01 subs r3, #1 8001eb8: b29a uxth r2, r3 8001eba: 68fb ldr r3, [r7, #12] 8001ebc: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8001ebe: 68fb ldr r3, [r7, #12] 8001ec0: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001ec2: b29b uxth r3, r3 8001ec4: 3b01 subs r3, #1 8001ec6: b29a uxth r2, r3 8001ec8: 68fb ldr r3, [r7, #12] 8001eca: 855a strh r2, [r3, #42] @ 0x2a } if ((hi2c->XferCount == 0U) && \ 8001ecc: 68fb ldr r3, [r7, #12] 8001ece: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001ed0: b29b uxth r3, r3 8001ed2: 2b00 cmp r3, #0 8001ed4: d14c bne.n 8001f70 8001ed6: 697b ldr r3, [r7, #20] 8001ed8: 4a2a ldr r2, [pc, #168] @ (8001f84 ) 8001eda: 4293 cmp r3, r2 8001edc: d048 beq.n 8001f70 (tmpoptions != I2C_NO_OPTION_FRAME)) { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8001ede: 68fb ldr r3, [r7, #12] 8001ee0: 0018 movs r0, r3 8001ee2: f000 fc47 bl 8002774 if ((hi2c->XferCount == 0U) && \ 8001ee6: e043 b.n 8001f70 } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8001ee8: 693b ldr r3, [r7, #16] 8001eea: 2208 movs r2, #8 8001eec: 4013 ands r3, r2 8001eee: d00a beq.n 8001f06 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 8001ef0: 687b ldr r3, [r7, #4] 8001ef2: 2208 movs r2, #8 8001ef4: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ 8001ef6: d006 beq.n 8001f06 { I2C_ITAddrCplt(hi2c, tmpITFlags); 8001ef8: 693a ldr r2, [r7, #16] 8001efa: 68fb ldr r3, [r7, #12] 8001efc: 0011 movs r1, r2 8001efe: 0018 movs r0, r3 8001f00: f000 fb52 bl 80025a8 8001f04: e035 b.n 8001f72 } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8001f06: 693b ldr r3, [r7, #16] 8001f08: 2202 movs r2, #2 8001f0a: 4013 ands r3, r2 8001f0c: d031 beq.n 8001f72 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 8001f0e: 687b ldr r3, [r7, #4] 8001f10: 2202 movs r2, #2 8001f12: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ 8001f14: d02d beq.n 8001f72 { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) 8001f16: 68fb ldr r3, [r7, #12] 8001f18: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001f1a: b29b uxth r3, r3 8001f1c: 2b00 cmp r3, #0 8001f1e: d018 beq.n 8001f52 { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; 8001f20: 68fb ldr r3, [r7, #12] 8001f22: 6a5b ldr r3, [r3, #36] @ 0x24 8001f24: 781a ldrb r2, [r3, #0] 8001f26: 68fb ldr r3, [r7, #12] 8001f28: 681b ldr r3, [r3, #0] 8001f2a: 629a str r2, [r3, #40] @ 0x28 /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8001f2c: 68fb ldr r3, [r7, #12] 8001f2e: 6a5b ldr r3, [r3, #36] @ 0x24 8001f30: 1c5a adds r2, r3, #1 8001f32: 68fb ldr r3, [r7, #12] 8001f34: 625a str r2, [r3, #36] @ 0x24 hi2c->XferCount--; 8001f36: 68fb ldr r3, [r7, #12] 8001f38: 8d5b ldrh r3, [r3, #42] @ 0x2a 8001f3a: b29b uxth r3, r3 8001f3c: 3b01 subs r3, #1 8001f3e: b29a uxth r2, r3 8001f40: 68fb ldr r3, [r7, #12] 8001f42: 855a strh r2, [r3, #42] @ 0x2a hi2c->XferSize--; 8001f44: 68fb ldr r3, [r7, #12] 8001f46: 8d1b ldrh r3, [r3, #40] @ 0x28 8001f48: 3b01 subs r3, #1 8001f4a: b29a uxth r2, r3 8001f4c: 68fb ldr r3, [r7, #12] 8001f4e: 851a strh r2, [r3, #40] @ 0x28 8001f50: e00f b.n 8001f72 } else { if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) 8001f52: 697a ldr r2, [r7, #20] 8001f54: 2380 movs r3, #128 @ 0x80 8001f56: 045b lsls r3, r3, #17 8001f58: 429a cmp r2, r3 8001f5a: d002 beq.n 8001f62 8001f5c: 697b ldr r3, [r7, #20] 8001f5e: 2b00 cmp r3, #0 8001f60: d107 bne.n 8001f72 { /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8001f62: 68fb ldr r3, [r7, #12] 8001f64: 0018 movs r0, r3 8001f66: f000 fc05 bl 8002774 8001f6a: e002 b.n 8001f72 if (hi2c->XferCount == 0U) 8001f6c: 46c0 nop @ (mov r8, r8) 8001f6e: e000 b.n 8001f72 if ((hi2c->XferCount == 0U) && \ 8001f70: 46c0 nop @ (mov r8, r8) { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8001f72: 68fb ldr r3, [r7, #12] 8001f74: 2240 movs r2, #64 @ 0x40 8001f76: 2100 movs r1, #0 8001f78: 5499 strb r1, [r3, r2] return HAL_OK; 8001f7a: 2300 movs r3, #0 } 8001f7c: 0018 movs r0, r3 8001f7e: 46bd mov sp, r7 8001f80: b006 add sp, #24 8001f82: bd80 pop {r7, pc} 8001f84: ffff0000 .word 0xffff0000 08001f88 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8001f88: b590 push {r4, r7, lr} 8001f8a: b089 sub sp, #36 @ 0x24 8001f8c: af02 add r7, sp, #8 8001f8e: 60f8 str r0, [r7, #12] 8001f90: 60b9 str r1, [r7, #8] 8001f92: 607a str r2, [r7, #4] uint16_t devaddress; uint32_t xfermode; /* Process Locked */ __HAL_LOCK(hi2c); 8001f94: 68fb ldr r3, [r7, #12] 8001f96: 2240 movs r2, #64 @ 0x40 8001f98: 5c9b ldrb r3, [r3, r2] 8001f9a: 2b01 cmp r3, #1 8001f9c: d101 bne.n 8001fa2 8001f9e: 2302 movs r3, #2 8001fa0: e0e7 b.n 8002172 8001fa2: 68fb ldr r3, [r7, #12] 8001fa4: 2240 movs r2, #64 @ 0x40 8001fa6: 2101 movs r1, #1 8001fa8: 5499 strb r1, [r3, r2] if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8001faa: 68bb ldr r3, [r7, #8] 8001fac: 2210 movs r2, #16 8001fae: 4013 ands r3, r2 8001fb0: d017 beq.n 8001fe2 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 8001fb2: 687b ldr r3, [r7, #4] 8001fb4: 2210 movs r2, #16 8001fb6: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8001fb8: d013 beq.n 8001fe2 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8001fba: 68fb ldr r3, [r7, #12] 8001fbc: 681b ldr r3, [r3, #0] 8001fbe: 2210 movs r2, #16 8001fc0: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8001fc2: 68fb ldr r3, [r7, #12] 8001fc4: 6c5b ldr r3, [r3, #68] @ 0x44 8001fc6: 2204 movs r2, #4 8001fc8: 431a orrs r2, r3 8001fca: 68fb ldr r3, [r7, #12] 8001fcc: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 8001fce: 68fb ldr r3, [r7, #12] 8001fd0: 2120 movs r1, #32 8001fd2: 0018 movs r0, r3 8001fd4: f001 f886 bl 80030e4 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8001fd8: 68fb ldr r3, [r7, #12] 8001fda: 0018 movs r0, r3 8001fdc: f001 f807 bl 8002fee 8001fe0: e0c2 b.n 8002168 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8001fe2: 68bb ldr r3, [r7, #8] 8001fe4: 2280 movs r2, #128 @ 0x80 8001fe6: 4013 ands r3, r2 8001fe8: d100 bne.n 8001fec 8001fea: e07c b.n 80020e6 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 8001fec: 687b ldr r3, [r7, #4] 8001fee: 2240 movs r2, #64 @ 0x40 8001ff0: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8001ff2: d100 bne.n 8001ff6 8001ff4: e077 b.n 80020e6 { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); 8001ff6: 68fb ldr r3, [r7, #12] 8001ff8: 681b ldr r3, [r3, #0] 8001ffa: 681a ldr r2, [r3, #0] 8001ffc: 68fb ldr r3, [r7, #12] 8001ffe: 681b ldr r3, [r3, #0] 8002000: 2140 movs r1, #64 @ 0x40 8002002: 438a bics r2, r1 8002004: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 8002006: 68fb ldr r3, [r7, #12] 8002008: 8d5b ldrh r3, [r3, #42] @ 0x2a 800200a: b29b uxth r3, r3 800200c: 2b00 cmp r3, #0 800200e: d055 beq.n 80020bc { /* Recover Slave address */ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); 8002010: 68fb ldr r3, [r7, #12] 8002012: 681b ldr r3, [r3, #0] 8002014: 685b ldr r3, [r3, #4] 8002016: b29a uxth r2, r3 8002018: 2312 movs r3, #18 800201a: 18fb adds r3, r7, r3 800201c: 0592 lsls r2, r2, #22 800201e: 0d92 lsrs r2, r2, #22 8002020: 801a strh r2, [r3, #0] /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8002022: 68fb ldr r3, [r7, #12] 8002024: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002026: b29b uxth r3, r3 8002028: 2bff cmp r3, #255 @ 0xff 800202a: d906 bls.n 800203a { hi2c->XferSize = MAX_NBYTE_SIZE; 800202c: 68fb ldr r3, [r7, #12] 800202e: 22ff movs r2, #255 @ 0xff 8002030: 851a strh r2, [r3, #40] @ 0x28 xfermode = I2C_RELOAD_MODE; 8002032: 2380 movs r3, #128 @ 0x80 8002034: 045b lsls r3, r3, #17 8002036: 617b str r3, [r7, #20] 8002038: e010 b.n 800205c } else { hi2c->XferSize = hi2c->XferCount; 800203a: 68fb ldr r3, [r7, #12] 800203c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800203e: b29a uxth r2, r3 8002040: 68fb ldr r3, [r7, #12] 8002042: 851a strh r2, [r3, #40] @ 0x28 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8002044: 68fb ldr r3, [r7, #12] 8002046: 6adb ldr r3, [r3, #44] @ 0x2c 8002048: 4a4c ldr r2, [pc, #304] @ (800217c ) 800204a: 4293 cmp r3, r2 800204c: d003 beq.n 8002056 { xfermode = hi2c->XferOptions; 800204e: 68fb ldr r3, [r7, #12] 8002050: 6adb ldr r3, [r3, #44] @ 0x2c 8002052: 617b str r3, [r7, #20] 8002054: e002 b.n 800205c } else { xfermode = I2C_AUTOEND_MODE; 8002056: 2380 movs r3, #128 @ 0x80 8002058: 049b lsls r3, r3, #18 800205a: 617b str r3, [r7, #20] } } /* Set the new XferSize in Nbytes register */ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); 800205c: 68fb ldr r3, [r7, #12] 800205e: 8d1b ldrh r3, [r3, #40] @ 0x28 8002060: b2da uxtb r2, r3 8002062: 697c ldr r4, [r7, #20] 8002064: 2312 movs r3, #18 8002066: 18fb adds r3, r7, r3 8002068: 8819 ldrh r1, [r3, #0] 800206a: 68f8 ldr r0, [r7, #12] 800206c: 2300 movs r3, #0 800206e: 9300 str r3, [sp, #0] 8002070: 0023 movs r3, r4 8002072: f000 fffd bl 8003070 /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8002076: 68fb ldr r3, [r7, #12] 8002078: 8d5b ldrh r3, [r3, #42] @ 0x2a 800207a: b29a uxth r2, r3 800207c: 68fb ldr r3, [r7, #12] 800207e: 8d1b ldrh r3, [r3, #40] @ 0x28 8002080: 1ad3 subs r3, r2, r3 8002082: b29a uxth r2, r3 8002084: 68fb ldr r3, [r7, #12] 8002086: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8002088: 68fb ldr r3, [r7, #12] 800208a: 2241 movs r2, #65 @ 0x41 800208c: 5c9b ldrb r3, [r3, r2] 800208e: b2db uxtb r3, r3 8002090: 2b22 cmp r3, #34 @ 0x22 8002092: d109 bne.n 80020a8 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8002094: 68fb ldr r3, [r7, #12] 8002096: 681b ldr r3, [r3, #0] 8002098: 681a ldr r2, [r3, #0] 800209a: 68fb ldr r3, [r7, #12] 800209c: 681b ldr r3, [r3, #0] 800209e: 2180 movs r1, #128 @ 0x80 80020a0: 0209 lsls r1, r1, #8 80020a2: 430a orrs r2, r1 80020a4: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80020a6: e05f b.n 8002168 } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 80020a8: 68fb ldr r3, [r7, #12] 80020aa: 681b ldr r3, [r3, #0] 80020ac: 681a ldr r2, [r3, #0] 80020ae: 68fb ldr r3, [r7, #12] 80020b0: 681b ldr r3, [r3, #0] 80020b2: 2180 movs r1, #128 @ 0x80 80020b4: 01c9 lsls r1, r1, #7 80020b6: 430a orrs r2, r1 80020b8: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80020ba: e055 b.n 8002168 } } else { /* Call TxCpltCallback() if no stop mode is set */ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 80020bc: 68fb ldr r3, [r7, #12] 80020be: 681b ldr r3, [r3, #0] 80020c0: 685a ldr r2, [r3, #4] 80020c2: 2380 movs r3, #128 @ 0x80 80020c4: 049b lsls r3, r3, #18 80020c6: 401a ands r2, r3 80020c8: 2380 movs r3, #128 @ 0x80 80020ca: 049b lsls r3, r3, #18 80020cc: 429a cmp r2, r3 80020ce: d004 beq.n 80020da { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 80020d0: 68fb ldr r3, [r7, #12] 80020d2: 0018 movs r0, r3 80020d4: f000 fb0c bl 80026f0 if (hi2c->XferCount != 0U) 80020d8: e046 b.n 8002168 } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 80020da: 68fb ldr r3, [r7, #12] 80020dc: 2140 movs r1, #64 @ 0x40 80020de: 0018 movs r0, r3 80020e0: f000 fe5a bl 8002d98 if (hi2c->XferCount != 0U) 80020e4: e040 b.n 8002168 } } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 80020e6: 68bb ldr r3, [r7, #8] 80020e8: 2240 movs r2, #64 @ 0x40 80020ea: 4013 ands r3, r2 80020ec: d02c beq.n 8002148 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 80020ee: 687b ldr r3, [r7, #4] 80020f0: 2240 movs r2, #64 @ 0x40 80020f2: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 80020f4: d028 beq.n 8002148 { if (hi2c->XferCount == 0U) 80020f6: 68fb ldr r3, [r7, #12] 80020f8: 8d5b ldrh r3, [r3, #42] @ 0x2a 80020fa: b29b uxth r3, r3 80020fc: 2b00 cmp r3, #0 80020fe: d11d bne.n 800213c { if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) 8002100: 68fb ldr r3, [r7, #12] 8002102: 681b ldr r3, [r3, #0] 8002104: 685a ldr r2, [r3, #4] 8002106: 2380 movs r3, #128 @ 0x80 8002108: 049b lsls r3, r3, #18 800210a: 401a ands r2, r3 800210c: 2380 movs r3, #128 @ 0x80 800210e: 049b lsls r3, r3, #18 8002110: 429a cmp r2, r3 8002112: d028 beq.n 8002166 { /* Generate a stop condition in case of no transfer option */ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) 8002114: 68fb ldr r3, [r7, #12] 8002116: 6adb ldr r3, [r3, #44] @ 0x2c 8002118: 4a18 ldr r2, [pc, #96] @ (800217c ) 800211a: 4293 cmp r3, r2 800211c: d109 bne.n 8002132 { /* Generate Stop */ hi2c->Instance->CR2 |= I2C_CR2_STOP; 800211e: 68fb ldr r3, [r7, #12] 8002120: 681b ldr r3, [r3, #0] 8002122: 685a ldr r2, [r3, #4] 8002124: 68fb ldr r3, [r7, #12] 8002126: 681b ldr r3, [r3, #0] 8002128: 2180 movs r1, #128 @ 0x80 800212a: 01c9 lsls r1, r1, #7 800212c: 430a orrs r2, r1 800212e: 605a str r2, [r3, #4] if (hi2c->XferCount == 0U) 8002130: e019 b.n 8002166 } else { /* Call I2C Master Sequential complete process */ I2C_ITMasterSeqCplt(hi2c); 8002132: 68fb ldr r3, [r7, #12] 8002134: 0018 movs r0, r3 8002136: f000 fadb bl 80026f0 if (hi2c->XferCount == 0U) 800213a: e014 b.n 8002166 } else { /* Wrong size Status regarding TC flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 800213c: 68fb ldr r3, [r7, #12] 800213e: 2140 movs r1, #64 @ 0x40 8002140: 0018 movs r0, r3 8002142: f000 fe29 bl 8002d98 if (hi2c->XferCount == 0U) 8002146: e00e b.n 8002166 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8002148: 68bb ldr r3, [r7, #8] 800214a: 2220 movs r2, #32 800214c: 4013 ands r3, r2 800214e: d00b beq.n 8002168 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 8002150: 687b ldr r3, [r7, #4] 8002152: 2220 movs r2, #32 8002154: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8002156: d007 beq.n 8002168 { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 8002158: 68ba ldr r2, [r7, #8] 800215a: 68fb ldr r3, [r7, #12] 800215c: 0011 movs r1, r2 800215e: 0018 movs r0, r3 8002160: f000 fb6c bl 800283c 8002164: e000 b.n 8002168 if (hi2c->XferCount == 0U) 8002166: 46c0 nop @ (mov r8, r8) { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002168: 68fb ldr r3, [r7, #12] 800216a: 2240 movs r2, #64 @ 0x40 800216c: 2100 movs r1, #0 800216e: 5499 strb r1, [r3, r2] return HAL_OK; 8002170: 2300 movs r3, #0 } 8002172: 0018 movs r0, r3 8002174: 46bd mov sp, r7 8002176: b007 add sp, #28 8002178: bd90 pop {r4, r7, pc} 800217a: 46c0 nop @ (mov r8, r8) 800217c: ffff0000 .word 0xffff0000 08002180 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 8002180: b590 push {r4, r7, lr} 8002182: b089 sub sp, #36 @ 0x24 8002184: af02 add r7, sp, #8 8002186: 60f8 str r0, [r7, #12] 8002188: 60b9 str r1, [r7, #8] 800218a: 607a str r2, [r7, #4] uint32_t direction = I2C_GENERATE_START_WRITE; 800218c: 4b90 ldr r3, [pc, #576] @ (80023d0 ) 800218e: 617b str r3, [r7, #20] /* Process Locked */ __HAL_LOCK(hi2c); 8002190: 68fb ldr r3, [r7, #12] 8002192: 2240 movs r2, #64 @ 0x40 8002194: 5c9b ldrb r3, [r3, r2] 8002196: 2b01 cmp r3, #1 8002198: d101 bne.n 800219e 800219a: 2302 movs r3, #2 800219c: e113 b.n 80023c6 800219e: 68fb ldr r3, [r7, #12] 80021a0: 2240 movs r2, #64 @ 0x40 80021a2: 2101 movs r1, #1 80021a4: 5499 strb r1, [r3, r2] if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80021a6: 68bb ldr r3, [r7, #8] 80021a8: 2210 movs r2, #16 80021aa: 4013 ands r3, r2 80021ac: d017 beq.n 80021de (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 80021ae: 687b ldr r3, [r7, #4] 80021b0: 2210 movs r2, #16 80021b2: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 80021b4: d013 beq.n 80021de { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80021b6: 68fb ldr r3, [r7, #12] 80021b8: 681b ldr r3, [r3, #0] 80021ba: 2210 movs r2, #16 80021bc: 61da str r2, [r3, #28] /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80021be: 68fb ldr r3, [r7, #12] 80021c0: 6c5b ldr r3, [r3, #68] @ 0x44 80021c2: 2204 movs r2, #4 80021c4: 431a orrs r2, r3 80021c6: 68fb ldr r3, [r7, #12] 80021c8: 645a str r2, [r3, #68] @ 0x44 /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); 80021ca: 68fb ldr r3, [r7, #12] 80021cc: 2120 movs r1, #32 80021ce: 0018 movs r0, r3 80021d0: f000 ff88 bl 80030e4 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80021d4: 68fb ldr r3, [r7, #12] 80021d6: 0018 movs r0, r3 80021d8: f000 ff09 bl 8002fee 80021dc: e0ee b.n 80023bc } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 80021de: 68bb ldr r3, [r7, #8] 80021e0: 2202 movs r2, #2 80021e2: 4013 ands r3, r2 80021e4: d00d beq.n 8002202 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) 80021e6: 687b ldr r3, [r7, #4] 80021e8: 2202 movs r2, #2 80021ea: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ 80021ec: d009 beq.n 8002202 { /* Write LSB part of Memory Address */ hi2c->Instance->TXDR = hi2c->Memaddress; 80021ee: 68fb ldr r3, [r7, #12] 80021f0: 681b ldr r3, [r3, #0] 80021f2: 68fa ldr r2, [r7, #12] 80021f4: 6d12 ldr r2, [r2, #80] @ 0x50 80021f6: 629a str r2, [r3, #40] @ 0x28 /* Reset Memaddress content */ hi2c->Memaddress = 0xFFFFFFFFU; 80021f8: 68fb ldr r3, [r7, #12] 80021fa: 2201 movs r2, #1 80021fc: 4252 negs r2, r2 80021fe: 651a str r2, [r3, #80] @ 0x50 8002200: e0dc b.n 80023bc } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8002202: 68bb ldr r3, [r7, #8] 8002204: 2280 movs r2, #128 @ 0x80 8002206: 4013 ands r3, r2 8002208: d063 beq.n 80022d2 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 800220a: 687b ldr r3, [r7, #4] 800220c: 2240 movs r2, #64 @ 0x40 800220e: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ 8002210: d05f beq.n 80022d2 { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8002212: 68fb ldr r3, [r7, #12] 8002214: 2101 movs r1, #1 8002216: 0018 movs r0, r3 8002218: f000 ffee bl 80031f8 /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 800221c: 68fb ldr r3, [r7, #12] 800221e: 2110 movs r1, #16 8002220: 0018 movs r0, r3 8002222: f000 ff5f bl 80030e4 if (hi2c->XferCount != 0U) 8002226: 68fb ldr r3, [r7, #12] 8002228: 8d5b ldrh r3, [r3, #42] @ 0x2a 800222a: b29b uxth r3, r3 800222c: 2b00 cmp r3, #0 800222e: d04a beq.n 80022c6 { /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) 8002230: 68fb ldr r3, [r7, #12] 8002232: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002234: b29b uxth r3, r3 8002236: 2bff cmp r3, #255 @ 0xff 8002238: d910 bls.n 800225c { hi2c->XferSize = MAX_NBYTE_SIZE; 800223a: 68fb ldr r3, [r7, #12] 800223c: 22ff movs r2, #255 @ 0xff 800223e: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8002240: 68fb ldr r3, [r7, #12] 8002242: 6cdb ldr r3, [r3, #76] @ 0x4c 8002244: b299 uxth r1, r3 8002246: 68fb ldr r3, [r7, #12] 8002248: 8d1b ldrh r3, [r3, #40] @ 0x28 800224a: b2da uxtb r2, r3 800224c: 2380 movs r3, #128 @ 0x80 800224e: 045b lsls r3, r3, #17 8002250: 68f8 ldr r0, [r7, #12] 8002252: 2400 movs r4, #0 8002254: 9400 str r4, [sp, #0] 8002256: f000 ff0b bl 8003070 800225a: e011 b.n 8002280 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; 800225c: 68fb ldr r3, [r7, #12] 800225e: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002260: b29a uxth r2, r3 8002262: 68fb ldr r3, [r7, #12] 8002264: 851a strh r2, [r3, #40] @ 0x28 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8002266: 68fb ldr r3, [r7, #12] 8002268: 6cdb ldr r3, [r3, #76] @ 0x4c 800226a: b299 uxth r1, r3 800226c: 68fb ldr r3, [r7, #12] 800226e: 8d1b ldrh r3, [r3, #40] @ 0x28 8002270: b2da uxtb r2, r3 8002272: 2380 movs r3, #128 @ 0x80 8002274: 049b lsls r3, r3, #18 8002276: 68f8 ldr r0, [r7, #12] 8002278: 2400 movs r4, #0 800227a: 9400 str r4, [sp, #0] 800227c: f000 fef8 bl 8003070 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 8002280: 68fb ldr r3, [r7, #12] 8002282: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002284: b29a uxth r2, r3 8002286: 68fb ldr r3, [r7, #12] 8002288: 8d1b ldrh r3, [r3, #40] @ 0x28 800228a: 1ad3 subs r3, r2, r3 800228c: b29a uxth r2, r3 800228e: 68fb ldr r3, [r7, #12] 8002290: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8002292: 68fb ldr r3, [r7, #12] 8002294: 2241 movs r2, #65 @ 0x41 8002296: 5c9b ldrb r3, [r3, r2] 8002298: b2db uxtb r3, r3 800229a: 2b22 cmp r3, #34 @ 0x22 800229c: d109 bne.n 80022b2 { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 800229e: 68fb ldr r3, [r7, #12] 80022a0: 681b ldr r3, [r3, #0] 80022a2: 681a ldr r2, [r3, #0] 80022a4: 68fb ldr r3, [r7, #12] 80022a6: 681b ldr r3, [r3, #0] 80022a8: 2180 movs r1, #128 @ 0x80 80022aa: 0209 lsls r1, r1, #8 80022ac: 430a orrs r2, r1 80022ae: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80022b0: e084 b.n 80023bc } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 80022b2: 68fb ldr r3, [r7, #12] 80022b4: 681b ldr r3, [r3, #0] 80022b6: 681a ldr r2, [r3, #0] 80022b8: 68fb ldr r3, [r7, #12] 80022ba: 681b ldr r3, [r3, #0] 80022bc: 2180 movs r1, #128 @ 0x80 80022be: 01c9 lsls r1, r1, #7 80022c0: 430a orrs r2, r1 80022c2: 601a str r2, [r3, #0] if (hi2c->XferCount != 0U) 80022c4: e07a b.n 80023bc } else { /* Wrong size Status regarding TCR flag event */ /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); 80022c6: 68fb ldr r3, [r7, #12] 80022c8: 2140 movs r1, #64 @ 0x40 80022ca: 0018 movs r0, r3 80022cc: f000 fd64 bl 8002d98 if (hi2c->XferCount != 0U) 80022d0: e074 b.n 80023bc } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 80022d2: 68bb ldr r3, [r7, #8] 80022d4: 2240 movs r2, #64 @ 0x40 80022d6: 4013 ands r3, r2 80022d8: d062 beq.n 80023a0 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) 80022da: 687b ldr r3, [r7, #4] 80022dc: 2240 movs r2, #64 @ 0x40 80022de: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ 80022e0: d05e beq.n 80023a0 { /* Disable Interrupt related to address step */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80022e2: 68fb ldr r3, [r7, #12] 80022e4: 2101 movs r1, #1 80022e6: 0018 movs r0, r3 80022e8: f000 ff86 bl 80031f8 /* Enable only Error and NACK interrupt for data transfer */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); 80022ec: 68fb ldr r3, [r7, #12] 80022ee: 2110 movs r1, #16 80022f0: 0018 movs r0, r3 80022f2: f000 fef7 bl 80030e4 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 80022f6: 68fb ldr r3, [r7, #12] 80022f8: 2241 movs r2, #65 @ 0x41 80022fa: 5c9b ldrb r3, [r3, r2] 80022fc: b2db uxtb r3, r3 80022fe: 2b22 cmp r3, #34 @ 0x22 8002300: d101 bne.n 8002306 { direction = I2C_GENERATE_START_READ; 8002302: 4b34 ldr r3, [pc, #208] @ (80023d4 ) 8002304: 617b str r3, [r7, #20] } if (hi2c->XferCount > MAX_NBYTE_SIZE) 8002306: 68fb ldr r3, [r7, #12] 8002308: 8d5b ldrh r3, [r3, #42] @ 0x2a 800230a: b29b uxth r3, r3 800230c: 2bff cmp r3, #255 @ 0xff 800230e: d911 bls.n 8002334 { hi2c->XferSize = MAX_NBYTE_SIZE; 8002310: 68fb ldr r3, [r7, #12] 8002312: 22ff movs r2, #255 @ 0xff 8002314: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 8002316: 68fb ldr r3, [r7, #12] 8002318: 6cdb ldr r3, [r3, #76] @ 0x4c 800231a: b299 uxth r1, r3 800231c: 68fb ldr r3, [r7, #12] 800231e: 8d1b ldrh r3, [r3, #40] @ 0x28 8002320: b2da uxtb r2, r3 8002322: 2380 movs r3, #128 @ 0x80 8002324: 045c lsls r4, r3, #17 8002326: 68f8 ldr r0, [r7, #12] 8002328: 697b ldr r3, [r7, #20] 800232a: 9300 str r3, [sp, #0] 800232c: 0023 movs r3, r4 800232e: f000 fe9f bl 8003070 8002332: e012 b.n 800235a I2C_RELOAD_MODE, direction); } else { hi2c->XferSize = hi2c->XferCount; 8002334: 68fb ldr r3, [r7, #12] 8002336: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002338: b29a uxth r2, r3 800233a: 68fb ldr r3, [r7, #12] 800233c: 851a strh r2, [r3, #40] @ 0x28 /* Set NBYTES to write and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, 800233e: 68fb ldr r3, [r7, #12] 8002340: 6cdb ldr r3, [r3, #76] @ 0x4c 8002342: b299 uxth r1, r3 8002344: 68fb ldr r3, [r7, #12] 8002346: 8d1b ldrh r3, [r3, #40] @ 0x28 8002348: b2da uxtb r2, r3 800234a: 2380 movs r3, #128 @ 0x80 800234c: 049c lsls r4, r3, #18 800234e: 68f8 ldr r0, [r7, #12] 8002350: 697b ldr r3, [r7, #20] 8002352: 9300 str r3, [sp, #0] 8002354: 0023 movs r3, r4 8002356: f000 fe8b bl 8003070 I2C_AUTOEND_MODE, direction); } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; 800235a: 68fb ldr r3, [r7, #12] 800235c: 8d5b ldrh r3, [r3, #42] @ 0x2a 800235e: b29a uxth r2, r3 8002360: 68fb ldr r3, [r7, #12] 8002362: 8d1b ldrh r3, [r3, #40] @ 0x28 8002364: 1ad3 subs r3, r2, r3 8002366: b29a uxth r2, r3 8002368: 68fb ldr r3, [r7, #12] 800236a: 855a strh r2, [r3, #42] @ 0x2a /* Enable DMA Request */ if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800236c: 68fb ldr r3, [r7, #12] 800236e: 2241 movs r2, #65 @ 0x41 8002370: 5c9b ldrb r3, [r3, r2] 8002372: b2db uxtb r3, r3 8002374: 2b22 cmp r3, #34 @ 0x22 8002376: d109 bne.n 800238c { hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; 8002378: 68fb ldr r3, [r7, #12] 800237a: 681b ldr r3, [r3, #0] 800237c: 681a ldr r2, [r3, #0] 800237e: 68fb ldr r3, [r7, #12] 8002380: 681b ldr r3, [r3, #0] 8002382: 2180 movs r1, #128 @ 0x80 8002384: 0209 lsls r1, r1, #8 8002386: 430a orrs r2, r1 8002388: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800238a: e017 b.n 80023bc } else { hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 800238c: 68fb ldr r3, [r7, #12] 800238e: 681b ldr r3, [r3, #0] 8002390: 681a ldr r2, [r3, #0] 8002392: 68fb ldr r3, [r7, #12] 8002394: 681b ldr r3, [r3, #0] 8002396: 2180 movs r1, #128 @ 0x80 8002398: 01c9 lsls r1, r1, #7 800239a: 430a orrs r2, r1 800239c: 601a str r2, [r3, #0] if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800239e: e00d b.n 80023bc } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 80023a0: 68bb ldr r3, [r7, #8] 80023a2: 2220 movs r2, #32 80023a4: 4013 ands r3, r2 80023a6: d009 beq.n 80023bc (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 80023a8: 687b ldr r3, [r7, #4] 80023aa: 2220 movs r2, #32 80023ac: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 80023ae: d005 beq.n 80023bc { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); 80023b0: 68ba ldr r2, [r7, #8] 80023b2: 68fb ldr r3, [r7, #12] 80023b4: 0011 movs r1, r2 80023b6: 0018 movs r0, r3 80023b8: f000 fa40 bl 800283c { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80023bc: 68fb ldr r3, [r7, #12] 80023be: 2240 movs r2, #64 @ 0x40 80023c0: 2100 movs r1, #0 80023c2: 5499 strb r1, [r3, r2] return HAL_OK; 80023c4: 2300 movs r3, #0 } 80023c6: 0018 movs r0, r3 80023c8: 46bd mov sp, r7 80023ca: b007 add sp, #28 80023cc: bd90 pop {r4, r7, pc} 80023ce: 46c0 nop @ (mov r8, r8) 80023d0: 80002000 .word 0x80002000 80023d4: 80002400 .word 0x80002400 080023d8 : * @param ITSources Interrupt sources enabled. * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) { 80023d8: b580 push {r7, lr} 80023da: b088 sub sp, #32 80023dc: af00 add r7, sp, #0 80023de: 60f8 str r0, [r7, #12] 80023e0: 60b9 str r1, [r7, #8] 80023e2: 607a str r2, [r7, #4] uint32_t tmpoptions = hi2c->XferOptions; 80023e4: 68fb ldr r3, [r7, #12] 80023e6: 6adb ldr r3, [r3, #44] @ 0x2c 80023e8: 61bb str r3, [r7, #24] uint32_t treatdmanack = 0U; 80023ea: 2300 movs r3, #0 80023ec: 61fb str r3, [r7, #28] HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); 80023ee: 68fb ldr r3, [r7, #12] 80023f0: 2240 movs r2, #64 @ 0x40 80023f2: 5c9b ldrb r3, [r3, r2] 80023f4: 2b01 cmp r3, #1 80023f6: d101 bne.n 80023fc 80023f8: 2302 movs r3, #2 80023fa: e0ce b.n 800259a 80023fc: 68fb ldr r3, [r7, #12] 80023fe: 2240 movs r2, #64 @ 0x40 8002400: 2101 movs r1, #1 8002402: 5499 strb r1, [r3, r2] /* Check if STOPF is set */ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8002404: 68bb ldr r3, [r7, #8] 8002406: 2220 movs r2, #32 8002408: 4013 ands r3, r2 800240a: d00a beq.n 8002422 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) 800240c: 687b ldr r3, [r7, #4] 800240e: 2220 movs r2, #32 8002410: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ 8002412: d006 beq.n 8002422 { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); 8002414: 68ba ldr r2, [r7, #8] 8002416: 68fb ldr r3, [r7, #12] 8002418: 0011 movs r1, r2 800241a: 0018 movs r0, r3 800241c: f000 fadc bl 80029d8 8002420: e0b6 b.n 8002590 } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8002422: 68bb ldr r3, [r7, #8] 8002424: 2210 movs r2, #16 8002426: 4013 ands r3, r2 8002428: d100 bne.n 800242c 800242a: e0a3 b.n 8002574 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) 800242c: 687b ldr r3, [r7, #4] 800242e: 2210 movs r2, #16 8002430: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ 8002432: d100 bne.n 8002436 8002434: e09e b.n 8002574 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0 */ /* So clear Flag NACKF only */ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8002436: 687a ldr r2, [r7, #4] 8002438: 2380 movs r3, #128 @ 0x80 800243a: 01db lsls r3, r3, #7 800243c: 4013 ands r3, r2 800243e: d105 bne.n 800244c (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) 8002440: 687a ldr r2, [r7, #4] 8002442: 2380 movs r3, #128 @ 0x80 8002444: 021b lsls r3, r3, #8 8002446: 4013 ands r3, r2 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8002448: d100 bne.n 800244c 800244a: e08c b.n 8002566 { /* Split check of hdmarx, for MISRA compliance */ if (hi2c->hdmarx != NULL) 800244c: 68fb ldr r3, [r7, #12] 800244e: 6bdb ldr r3, [r3, #60] @ 0x3c 8002450: 2b00 cmp r3, #0 8002452: d00c beq.n 800246e { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) 8002454: 687a ldr r2, [r7, #4] 8002456: 2380 movs r3, #128 @ 0x80 8002458: 021b lsls r3, r3, #8 800245a: 4013 ands r3, r2 800245c: d007 beq.n 800246e { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) 800245e: 68fb ldr r3, [r7, #12] 8002460: 6bdb ldr r3, [r3, #60] @ 0x3c 8002462: 681b ldr r3, [r3, #0] 8002464: 685b ldr r3, [r3, #4] 8002466: 2b00 cmp r3, #0 8002468: d101 bne.n 800246e { treatdmanack = 1U; 800246a: 2301 movs r3, #1 800246c: 61fb str r3, [r7, #28] } } } /* Split check of hdmatx, for MISRA compliance */ if (hi2c->hdmatx != NULL) 800246e: 68fb ldr r3, [r7, #12] 8002470: 6b9b ldr r3, [r3, #56] @ 0x38 8002472: 2b00 cmp r3, #0 8002474: d00c beq.n 8002490 { if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) 8002476: 687a ldr r2, [r7, #4] 8002478: 2380 movs r3, #128 @ 0x80 800247a: 01db lsls r3, r3, #7 800247c: 4013 ands r3, r2 800247e: d007 beq.n 8002490 { if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) 8002480: 68fb ldr r3, [r7, #12] 8002482: 6b9b ldr r3, [r3, #56] @ 0x38 8002484: 681b ldr r3, [r3, #0] 8002486: 685b ldr r3, [r3, #4] 8002488: 2b00 cmp r3, #0 800248a: d101 bne.n 8002490 { treatdmanack = 1U; 800248c: 2301 movs r3, #1 800248e: 61fb str r3, [r7, #28] } } } if (treatdmanack == 1U) 8002490: 69fb ldr r3, [r7, #28] 8002492: 2b01 cmp r3, #1 8002494: d12d bne.n 80024f2 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8002496: 68fb ldr r3, [r7, #12] 8002498: 2241 movs r2, #65 @ 0x41 800249a: 5c9b ldrb r3, [r3, r2] 800249c: b2db uxtb r3, r3 800249e: 2b28 cmp r3, #40 @ 0x28 80024a0: d10b bne.n 80024ba 80024a2: 69ba ldr r2, [r7, #24] 80024a4: 2380 movs r3, #128 @ 0x80 80024a6: 049b lsls r3, r3, #18 80024a8: 429a cmp r2, r3 80024aa: d106 bne.n 80024ba /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); 80024ac: 68ba ldr r2, [r7, #8] 80024ae: 68fb ldr r3, [r7, #12] 80024b0: 0011 movs r1, r2 80024b2: 0018 movs r0, r3 80024b4: f000 fc18 bl 8002ce8 80024b8: e054 b.n 8002564 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 80024ba: 68fb ldr r3, [r7, #12] 80024bc: 2241 movs r2, #65 @ 0x41 80024be: 5c9b ldrb r3, [r3, r2] 80024c0: b2db uxtb r3, r3 80024c2: 2b29 cmp r3, #41 @ 0x29 80024c4: d110 bne.n 80024e8 80024c6: 69bb ldr r3, [r7, #24] 80024c8: 4a36 ldr r2, [pc, #216] @ (80025a4 ) 80024ca: 4293 cmp r3, r2 80024cc: d00c beq.n 80024e8 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80024ce: 68fb ldr r3, [r7, #12] 80024d0: 681b ldr r3, [r3, #0] 80024d2: 2210 movs r2, #16 80024d4: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80024d6: 68fb ldr r3, [r7, #12] 80024d8: 0018 movs r0, r3 80024da: f000 fd88 bl 8002fee /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 80024de: 68fb ldr r3, [r7, #12] 80024e0: 0018 movs r0, r3 80024e2: f000 f947 bl 8002774 80024e6: e03d b.n 8002564 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80024e8: 68fb ldr r3, [r7, #12] 80024ea: 681b ldr r3, [r3, #0] 80024ec: 2210 movs r2, #16 80024ee: 61da str r2, [r3, #28] if (treatdmanack == 1U) 80024f0: e03e b.n 8002570 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80024f2: 68fb ldr r3, [r7, #12] 80024f4: 681b ldr r3, [r3, #0] 80024f6: 2210 movs r2, #16 80024f8: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80024fa: 68fb ldr r3, [r7, #12] 80024fc: 6c5b ldr r3, [r3, #68] @ 0x44 80024fe: 2204 movs r2, #4 8002500: 431a orrs r2, r3 8002502: 68fb ldr r3, [r7, #12] 8002504: 645a str r2, [r3, #68] @ 0x44 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ tmpstate = hi2c->State; 8002506: 2317 movs r3, #23 8002508: 18fb adds r3, r7, r3 800250a: 68fa ldr r2, [r7, #12] 800250c: 2141 movs r1, #65 @ 0x41 800250e: 5c52 ldrb r2, [r2, r1] 8002510: 701a strb r2, [r3, #0] if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8002512: 69bb ldr r3, [r7, #24] 8002514: 2b00 cmp r3, #0 8002516: d004 beq.n 8002522 8002518: 69ba ldr r2, [r7, #24] 800251a: 2380 movs r3, #128 @ 0x80 800251c: 045b lsls r3, r3, #17 800251e: 429a cmp r2, r3 8002520: d126 bne.n 8002570 { if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8002522: 2217 movs r2, #23 8002524: 18bb adds r3, r7, r2 8002526: 781b ldrb r3, [r3, #0] 8002528: 2b21 cmp r3, #33 @ 0x21 800252a: d003 beq.n 8002534 800252c: 18bb adds r3, r7, r2 800252e: 781b ldrb r3, [r3, #0] 8002530: 2b29 cmp r3, #41 @ 0x29 8002532: d103 bne.n 800253c { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8002534: 68fb ldr r3, [r7, #12] 8002536: 2221 movs r2, #33 @ 0x21 8002538: 631a str r2, [r3, #48] @ 0x30 800253a: e00b b.n 8002554 } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 800253c: 2217 movs r2, #23 800253e: 18bb adds r3, r7, r2 8002540: 781b ldrb r3, [r3, #0] 8002542: 2b22 cmp r3, #34 @ 0x22 8002544: d003 beq.n 800254e 8002546: 18bb adds r3, r7, r2 8002548: 781b ldrb r3, [r3, #0] 800254a: 2b2a cmp r3, #42 @ 0x2a 800254c: d102 bne.n 8002554 { hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 800254e: 68fb ldr r3, [r7, #12] 8002550: 2222 movs r2, #34 @ 0x22 8002552: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002554: 68fb ldr r3, [r7, #12] 8002556: 6c5a ldr r2, [r3, #68] @ 0x44 8002558: 68fb ldr r3, [r7, #12] 800255a: 0011 movs r1, r2 800255c: 0018 movs r0, r3 800255e: f000 fc1b bl 8002d98 if (treatdmanack == 1U) 8002562: e005 b.n 8002570 8002564: e004 b.n 8002570 } } else { /* Only Clear NACK Flag, no DMA treatment is pending */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002566: 68fb ldr r3, [r7, #12] 8002568: 681b ldr r3, [r3, #0] 800256a: 2210 movs r2, #16 800256c: 61da str r2, [r3, #28] if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 800256e: e00f b.n 8002590 if (treatdmanack == 1U) 8002570: 46c0 nop @ (mov r8, r8) if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || 8002572: e00d b.n 8002590 } } else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8002574: 68bb ldr r3, [r7, #8] 8002576: 2208 movs r2, #8 8002578: 4013 ands r3, r2 800257a: d009 beq.n 8002590 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) 800257c: 687b ldr r3, [r7, #4] 800257e: 2208 movs r2, #8 8002580: 4013 ands r3, r2 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ 8002582: d005 beq.n 8002590 { I2C_ITAddrCplt(hi2c, ITFlags); 8002584: 68ba ldr r2, [r7, #8] 8002586: 68fb ldr r3, [r7, #12] 8002588: 0011 movs r1, r2 800258a: 0018 movs r0, r3 800258c: f000 f80c bl 80025a8 { /* Nothing to do */ } /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002590: 68fb ldr r3, [r7, #12] 8002592: 2240 movs r2, #64 @ 0x40 8002594: 2100 movs r1, #0 8002596: 5499 strb r1, [r3, r2] return HAL_OK; 8002598: 2300 movs r3, #0 } 800259a: 0018 movs r0, r3 800259c: 46bd mov sp, r7 800259e: b008 add sp, #32 80025a0: bd80 pop {r7, pc} 80025a2: 46c0 nop @ (mov r8, r8) 80025a4: ffff0000 .word 0xffff0000 080025a8 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80025a8: b5b0 push {r4, r5, r7, lr} 80025aa: b084 sub sp, #16 80025ac: af00 add r7, sp, #0 80025ae: 6078 str r0, [r7, #4] 80025b0: 6039 str r1, [r7, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(ITFlags); /* In case of Listen state, need to inform upper layer of address match code event */ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 80025b2: 687b ldr r3, [r7, #4] 80025b4: 2241 movs r2, #65 @ 0x41 80025b6: 5c9b ldrb r3, [r3, r2] 80025b8: b2db uxtb r3, r3 80025ba: 001a movs r2, r3 80025bc: 2328 movs r3, #40 @ 0x28 80025be: 4013 ands r3, r2 80025c0: 2b28 cmp r3, #40 @ 0x28 80025c2: d000 beq.n 80025c6 80025c4: e088 b.n 80026d8 { transferdirection = I2C_GET_DIR(hi2c); 80025c6: 687b ldr r3, [r7, #4] 80025c8: 681b ldr r3, [r3, #0] 80025ca: 699b ldr r3, [r3, #24] 80025cc: 0c1b lsrs r3, r3, #16 80025ce: b2da uxtb r2, r3 80025d0: 250f movs r5, #15 80025d2: 197b adds r3, r7, r5 80025d4: 2101 movs r1, #1 80025d6: 400a ands r2, r1 80025d8: 701a strb r2, [r3, #0] slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); 80025da: 687b ldr r3, [r7, #4] 80025dc: 681b ldr r3, [r3, #0] 80025de: 699b ldr r3, [r3, #24] 80025e0: 0c1b lsrs r3, r3, #16 80025e2: b29a uxth r2, r3 80025e4: 200c movs r0, #12 80025e6: 183b adds r3, r7, r0 80025e8: 21fe movs r1, #254 @ 0xfe 80025ea: 400a ands r2, r1 80025ec: 801a strh r2, [r3, #0] ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); 80025ee: 687b ldr r3, [r7, #4] 80025f0: 681b ldr r3, [r3, #0] 80025f2: 689b ldr r3, [r3, #8] 80025f4: b29a uxth r2, r3 80025f6: 240a movs r4, #10 80025f8: 193b adds r3, r7, r4 80025fa: 0592 lsls r2, r2, #22 80025fc: 0d92 lsrs r2, r2, #22 80025fe: 801a strh r2, [r3, #0] ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); 8002600: 687b ldr r3, [r7, #4] 8002602: 681b ldr r3, [r3, #0] 8002604: 68db ldr r3, [r3, #12] 8002606: b29a uxth r2, r3 8002608: 2308 movs r3, #8 800260a: 18fb adds r3, r7, r3 800260c: 21fe movs r1, #254 @ 0xfe 800260e: 400a ands r2, r1 8002610: 801a strh r2, [r3, #0] /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 8002612: 687b ldr r3, [r7, #4] 8002614: 68db ldr r3, [r3, #12] 8002616: 2b02 cmp r3, #2 8002618: d148 bne.n 80026ac { if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) 800261a: 0021 movs r1, r4 800261c: 187b adds r3, r7, r1 800261e: 881b ldrh r3, [r3, #0] 8002620: 09db lsrs r3, r3, #7 8002622: b29a uxth r2, r3 8002624: 183b adds r3, r7, r0 8002626: 881b ldrh r3, [r3, #0] 8002628: 4053 eors r3, r2 800262a: b29b uxth r3, r3 800262c: 001a movs r2, r3 800262e: 2306 movs r3, #6 8002630: 4013 ands r3, r2 8002632: d120 bne.n 8002676 { slaveaddrcode = ownadd1code; 8002634: 183b adds r3, r7, r0 8002636: 187a adds r2, r7, r1 8002638: 8812 ldrh r2, [r2, #0] 800263a: 801a strh r2, [r3, #0] hi2c->AddrEventCount++; 800263c: 687b ldr r3, [r7, #4] 800263e: 6c9b ldr r3, [r3, #72] @ 0x48 8002640: 1c5a adds r2, r3, #1 8002642: 687b ldr r3, [r7, #4] 8002644: 649a str r2, [r3, #72] @ 0x48 if (hi2c->AddrEventCount == 2U) 8002646: 687b ldr r3, [r7, #4] 8002648: 6c9b ldr r3, [r3, #72] @ 0x48 800264a: 2b02 cmp r3, #2 800264c: d14c bne.n 80026e8 { /* Reset Address Event counter */ hi2c->AddrEventCount = 0U; 800264e: 687b ldr r3, [r7, #4] 8002650: 2200 movs r2, #0 8002652: 649a str r2, [r3, #72] @ 0x48 /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 8002654: 687b ldr r3, [r7, #4] 8002656: 681b ldr r3, [r3, #0] 8002658: 2208 movs r2, #8 800265a: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800265c: 687b ldr r3, [r7, #4] 800265e: 2240 movs r2, #64 @ 0x40 8002660: 2100 movs r1, #0 8002662: 5499 strb r1, [r3, r2] /* Call Slave Addr callback */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); #else HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8002664: 183b adds r3, r7, r0 8002666: 881a ldrh r2, [r3, #0] 8002668: 197b adds r3, r7, r5 800266a: 7819 ldrb r1, [r3, #0] 800266c: 687b ldr r3, [r7, #4] 800266e: 0018 movs r0, r3 8002670: f7fe f880 bl 8000774 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); /* Process Unlocked */ __HAL_UNLOCK(hi2c); } } 8002674: e038 b.n 80026e8 slaveaddrcode = ownadd2code; 8002676: 240c movs r4, #12 8002678: 193b adds r3, r7, r4 800267a: 2208 movs r2, #8 800267c: 18ba adds r2, r7, r2 800267e: 8812 ldrh r2, [r2, #0] 8002680: 801a strh r2, [r3, #0] I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 8002682: 2380 movs r3, #128 @ 0x80 8002684: 021a lsls r2, r3, #8 8002686: 687b ldr r3, [r7, #4] 8002688: 0011 movs r1, r2 800268a: 0018 movs r0, r3 800268c: f000 fdb4 bl 80031f8 __HAL_UNLOCK(hi2c); 8002690: 687b ldr r3, [r7, #4] 8002692: 2240 movs r2, #64 @ 0x40 8002694: 2100 movs r1, #0 8002696: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 8002698: 193b adds r3, r7, r4 800269a: 881a ldrh r2, [r3, #0] 800269c: 230f movs r3, #15 800269e: 18fb adds r3, r7, r3 80026a0: 7819 ldrb r1, [r3, #0] 80026a2: 687b ldr r3, [r7, #4] 80026a4: 0018 movs r0, r3 80026a6: f7fe f865 bl 8000774 } 80026aa: e01d b.n 80026e8 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); 80026ac: 2380 movs r3, #128 @ 0x80 80026ae: 021a lsls r2, r3, #8 80026b0: 687b ldr r3, [r7, #4] 80026b2: 0011 movs r1, r2 80026b4: 0018 movs r0, r3 80026b6: f000 fd9f bl 80031f8 __HAL_UNLOCK(hi2c); 80026ba: 687b ldr r3, [r7, #4] 80026bc: 2240 movs r2, #64 @ 0x40 80026be: 2100 movs r1, #0 80026c0: 5499 strb r1, [r3, r2] HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); 80026c2: 230c movs r3, #12 80026c4: 18fb adds r3, r7, r3 80026c6: 881a ldrh r2, [r3, #0] 80026c8: 230f movs r3, #15 80026ca: 18fb adds r3, r7, r3 80026cc: 7819 ldrb r1, [r3, #0] 80026ce: 687b ldr r3, [r7, #4] 80026d0: 0018 movs r0, r3 80026d2: f7fe f84f bl 8000774 } 80026d6: e007 b.n 80026e8 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); 80026d8: 687b ldr r3, [r7, #4] 80026da: 681b ldr r3, [r3, #0] 80026dc: 2208 movs r2, #8 80026de: 61da str r2, [r3, #28] __HAL_UNLOCK(hi2c); 80026e0: 687b ldr r3, [r7, #4] 80026e2: 2240 movs r2, #64 @ 0x40 80026e4: 2100 movs r1, #0 80026e6: 5499 strb r1, [r3, r2] } 80026e8: 46c0 nop @ (mov r8, r8) 80026ea: 46bd mov sp, r7 80026ec: b004 add sp, #16 80026ee: bdb0 pop {r4, r5, r7, pc} 080026f0 : * @brief I2C Master sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) { 80026f0: b580 push {r7, lr} 80026f2: b082 sub sp, #8 80026f4: af00 add r7, sp, #0 80026f6: 6078 str r0, [r7, #4] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 80026f8: 687b ldr r3, [r7, #4] 80026fa: 2242 movs r2, #66 @ 0x42 80026fc: 2100 movs r1, #0 80026fe: 5499 strb r1, [r3, r2] /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8002700: 687b ldr r3, [r7, #4] 8002702: 2241 movs r2, #65 @ 0x41 8002704: 5c9b ldrb r3, [r3, r2] 8002706: b2db uxtb r3, r3 8002708: 2b21 cmp r3, #33 @ 0x21 800270a: d117 bne.n 800273c { hi2c->State = HAL_I2C_STATE_READY; 800270c: 687b ldr r3, [r7, #4] 800270e: 2241 movs r2, #65 @ 0x41 8002710: 2120 movs r1, #32 8002712: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 8002714: 687b ldr r3, [r7, #4] 8002716: 2211 movs r2, #17 8002718: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 800271a: 687b ldr r3, [r7, #4] 800271c: 2200 movs r2, #0 800271e: 635a str r2, [r3, #52] @ 0x34 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 8002720: 687b ldr r3, [r7, #4] 8002722: 2101 movs r1, #1 8002724: 0018 movs r0, r3 8002726: f000 fd67 bl 80031f8 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800272a: 687b ldr r3, [r7, #4] 800272c: 2240 movs r2, #64 @ 0x40 800272e: 2100 movs r1, #0 8002730: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->MasterTxCpltCallback(hi2c); #else HAL_I2C_MasterTxCpltCallback(hi2c); 8002732: 687b ldr r3, [r7, #4] 8002734: 0018 movs r0, r3 8002736: f7ff faf6 bl 8001d26 hi2c->MasterRxCpltCallback(hi2c); #else HAL_I2C_MasterRxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 800273a: e016 b.n 800276a hi2c->State = HAL_I2C_STATE_READY; 800273c: 687b ldr r3, [r7, #4] 800273e: 2241 movs r2, #65 @ 0x41 8002740: 2120 movs r1, #32 8002742: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 8002744: 687b ldr r3, [r7, #4] 8002746: 2212 movs r2, #18 8002748: 631a str r2, [r3, #48] @ 0x30 hi2c->XferISR = NULL; 800274a: 687b ldr r3, [r7, #4] 800274c: 2200 movs r2, #0 800274e: 635a str r2, [r3, #52] @ 0x34 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8002750: 687b ldr r3, [r7, #4] 8002752: 2102 movs r1, #2 8002754: 0018 movs r0, r3 8002756: f000 fd4f bl 80031f8 __HAL_UNLOCK(hi2c); 800275a: 687b ldr r3, [r7, #4] 800275c: 2240 movs r2, #64 @ 0x40 800275e: 2100 movs r1, #0 8002760: 5499 strb r1, [r3, r2] HAL_I2C_MasterRxCpltCallback(hi2c); 8002762: 687b ldr r3, [r7, #4] 8002764: 0018 movs r0, r3 8002766: f7ff fae6 bl 8001d36 } 800276a: 46c0 nop @ (mov r8, r8) 800276c: 46bd mov sp, r7 800276e: b002 add sp, #8 8002770: bd80 pop {r7, pc} ... 08002774 : * @brief I2C Slave sequential complete process. * @param hi2c I2C handle. * @retval None */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { 8002774: b580 push {r7, lr} 8002776: b084 sub sp, #16 8002778: af00 add r7, sp, #0 800277a: 6078 str r0, [r7, #4] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 800277c: 687b ldr r3, [r7, #4] 800277e: 681b ldr r3, [r3, #0] 8002780: 681b ldr r3, [r3, #0] 8002782: 60fb str r3, [r7, #12] /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; 8002784: 687b ldr r3, [r7, #4] 8002786: 2242 movs r2, #66 @ 0x42 8002788: 2100 movs r1, #0 800278a: 5499 strb r1, [r3, r2] /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 800278c: 68fa ldr r2, [r7, #12] 800278e: 2380 movs r3, #128 @ 0x80 8002790: 01db lsls r3, r3, #7 8002792: 4013 ands r3, r2 8002794: d008 beq.n 80027a8 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8002796: 687b ldr r3, [r7, #4] 8002798: 681b ldr r3, [r3, #0] 800279a: 681a ldr r2, [r3, #0] 800279c: 687b ldr r3, [r7, #4] 800279e: 681b ldr r3, [r3, #0] 80027a0: 4924 ldr r1, [pc, #144] @ (8002834 ) 80027a2: 400a ands r2, r1 80027a4: 601a str r2, [r3, #0] 80027a6: e00c b.n 80027c2 } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 80027a8: 68fa ldr r2, [r7, #12] 80027aa: 2380 movs r3, #128 @ 0x80 80027ac: 021b lsls r3, r3, #8 80027ae: 4013 ands r3, r2 80027b0: d007 beq.n 80027c2 { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 80027b2: 687b ldr r3, [r7, #4] 80027b4: 681b ldr r3, [r3, #0] 80027b6: 681a ldr r2, [r3, #0] 80027b8: 687b ldr r3, [r7, #4] 80027ba: 681b ldr r3, [r3, #0] 80027bc: 491e ldr r1, [pc, #120] @ (8002838 ) 80027be: 400a ands r2, r1 80027c0: 601a str r2, [r3, #0] else { /* Do nothing */ } if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 80027c2: 687b ldr r3, [r7, #4] 80027c4: 2241 movs r2, #65 @ 0x41 80027c6: 5c9b ldrb r3, [r3, r2] 80027c8: b2db uxtb r3, r3 80027ca: 2b29 cmp r3, #41 @ 0x29 80027cc: d114 bne.n 80027f8 { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ hi2c->State = HAL_I2C_STATE_LISTEN; 80027ce: 687b ldr r3, [r7, #4] 80027d0: 2241 movs r2, #65 @ 0x41 80027d2: 2128 movs r1, #40 @ 0x28 80027d4: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 80027d6: 687b ldr r3, [r7, #4] 80027d8: 2221 movs r2, #33 @ 0x21 80027da: 631a str r2, [r3, #48] @ 0x30 /* Disable Interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 80027dc: 687b ldr r3, [r7, #4] 80027de: 2101 movs r1, #1 80027e0: 0018 movs r0, r3 80027e2: f000 fd09 bl 80031f8 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80027e6: 687b ldr r3, [r7, #4] 80027e8: 2240 movs r2, #64 @ 0x40 80027ea: 2100 movs r1, #0 80027ec: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); 80027ee: 687b ldr r3, [r7, #4] 80027f0: 0018 movs r0, r3 80027f2: f7fe f8f5 bl 80009e0 } else { /* Nothing to do */ } } 80027f6: e019 b.n 800282c else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 80027f8: 687b ldr r3, [r7, #4] 80027fa: 2241 movs r2, #65 @ 0x41 80027fc: 5c9b ldrb r3, [r3, r2] 80027fe: b2db uxtb r3, r3 8002800: 2b2a cmp r3, #42 @ 0x2a 8002802: d113 bne.n 800282c hi2c->State = HAL_I2C_STATE_LISTEN; 8002804: 687b ldr r3, [r7, #4] 8002806: 2241 movs r2, #65 @ 0x41 8002808: 2128 movs r1, #40 @ 0x28 800280a: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 800280c: 687b ldr r3, [r7, #4] 800280e: 2222 movs r2, #34 @ 0x22 8002810: 631a str r2, [r3, #48] @ 0x30 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 8002812: 687b ldr r3, [r7, #4] 8002814: 2102 movs r1, #2 8002816: 0018 movs r0, r3 8002818: f000 fcee bl 80031f8 __HAL_UNLOCK(hi2c); 800281c: 687b ldr r3, [r7, #4] 800281e: 2240 movs r2, #64 @ 0x40 8002820: 2100 movs r1, #0 8002822: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 8002824: 687b ldr r3, [r7, #4] 8002826: 0018 movs r0, r3 8002828: f7fe f88a bl 8000940 } 800282c: 46c0 nop @ (mov r8, r8) 800282e: 46bd mov sp, r7 8002830: b004 add sp, #16 8002832: bd80 pop {r7, pc} 8002834: ffffbfff .word 0xffffbfff 8002838: ffff7fff .word 0xffff7fff 0800283c : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 800283c: b580 push {r7, lr} 800283e: b086 sub sp, #24 8002840: af00 add r7, sp, #0 8002842: 6078 str r0, [r7, #4] 8002844: 6039 str r1, [r7, #0] uint32_t tmperror; uint32_t tmpITFlags = ITFlags; 8002846: 683b ldr r3, [r7, #0] 8002848: 617b str r3, [r7, #20] __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 800284a: 687b ldr r3, [r7, #4] 800284c: 681b ldr r3, [r3, #0] 800284e: 2220 movs r2, #32 8002850: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8002852: 687b ldr r3, [r7, #4] 8002854: 2241 movs r2, #65 @ 0x41 8002856: 5c9b ldrb r3, [r3, r2] 8002858: b2db uxtb r3, r3 800285a: 2b21 cmp r3, #33 @ 0x21 800285c: d108 bne.n 8002870 { I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); 800285e: 687b ldr r3, [r7, #4] 8002860: 2101 movs r1, #1 8002862: 0018 movs r0, r3 8002864: f000 fcc8 bl 80031f8 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 8002868: 687b ldr r3, [r7, #4] 800286a: 2211 movs r2, #17 800286c: 631a str r2, [r3, #48] @ 0x30 800286e: e00d b.n 800288c } else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8002870: 687b ldr r3, [r7, #4] 8002872: 2241 movs r2, #65 @ 0x41 8002874: 5c9b ldrb r3, [r3, r2] 8002876: b2db uxtb r3, r3 8002878: 2b22 cmp r3, #34 @ 0x22 800287a: d107 bne.n 800288c { I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); 800287c: 687b ldr r3, [r7, #4] 800287e: 2102 movs r1, #2 8002880: 0018 movs r0, r3 8002882: f000 fcb9 bl 80031f8 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 8002886: 687b ldr r3, [r7, #4] 8002888: 2212 movs r2, #18 800288a: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 800288c: 687b ldr r3, [r7, #4] 800288e: 681b ldr r3, [r3, #0] 8002890: 685a ldr r2, [r3, #4] 8002892: 687b ldr r3, [r7, #4] 8002894: 681b ldr r3, [r3, #0] 8002896: 494e ldr r1, [pc, #312] @ (80029d0 ) 8002898: 400a ands r2, r1 800289a: 605a str r2, [r3, #4] /* Reset handle parameters */ hi2c->XferISR = NULL; 800289c: 687b ldr r3, [r7, #4] 800289e: 2200 movs r2, #0 80028a0: 635a str r2, [r3, #52] @ 0x34 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 80028a2: 687b ldr r3, [r7, #4] 80028a4: 4a4b ldr r2, [pc, #300] @ (80029d4 ) 80028a6: 62da str r2, [r3, #44] @ 0x2c if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) 80028a8: 697b ldr r3, [r7, #20] 80028aa: 2210 movs r2, #16 80028ac: 4013 ands r3, r2 80028ae: d009 beq.n 80028c4 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 80028b0: 687b ldr r3, [r7, #4] 80028b2: 681b ldr r3, [r3, #0] 80028b4: 2210 movs r2, #16 80028b6: 61da str r2, [r3, #28] /* Set acknowledge error code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 80028b8: 687b ldr r3, [r7, #4] 80028ba: 6c5b ldr r3, [r3, #68] @ 0x44 80028bc: 2204 movs r2, #4 80028be: 431a orrs r2, r3 80028c0: 687b ldr r3, [r7, #4] 80028c2: 645a str r2, [r3, #68] @ 0x44 } /* Fetch Last receive data if any */ if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) 80028c4: 687b ldr r3, [r7, #4] 80028c6: 2241 movs r2, #65 @ 0x41 80028c8: 5c9b ldrb r3, [r3, r2] 80028ca: b2db uxtb r3, r3 80028cc: 2b60 cmp r3, #96 @ 0x60 80028ce: d109 bne.n 80028e4 80028d0: 697b ldr r3, [r7, #20] 80028d2: 2204 movs r2, #4 80028d4: 4013 ands r3, r2 80028d6: d005 beq.n 80028e4 { /* Read data from RXDR */ tmpreg = (uint8_t)hi2c->Instance->RXDR; 80028d8: 687b ldr r3, [r7, #4] 80028da: 681b ldr r3, [r3, #0] 80028dc: 6a5b ldr r3, [r3, #36] @ 0x24 80028de: b2db uxtb r3, r3 80028e0: 60fb str r3, [r7, #12] UNUSED(tmpreg); 80028e2: 68fb ldr r3, [r7, #12] } /* Flush TX register */ I2C_Flush_TXDR(hi2c); 80028e4: 687b ldr r3, [r7, #4] 80028e6: 0018 movs r0, r3 80028e8: f000 fb81 bl 8002fee /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; 80028ec: 687b ldr r3, [r7, #4] 80028ee: 6c5b ldr r3, [r3, #68] @ 0x44 80028f0: 613b str r3, [r7, #16] /* Call the corresponding callback to inform upper layer of End of Transfer */ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) 80028f2: 687b ldr r3, [r7, #4] 80028f4: 2241 movs r2, #65 @ 0x41 80028f6: 5c9b ldrb r3, [r3, r2] 80028f8: b2db uxtb r3, r3 80028fa: 2b60 cmp r3, #96 @ 0x60 80028fc: d002 beq.n 8002904 80028fe: 693b ldr r3, [r7, #16] 8002900: 2b00 cmp r3, #0 8002902: d007 beq.n 8002914 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002904: 687b ldr r3, [r7, #4] 8002906: 6c5a ldr r2, [r3, #68] @ 0x44 8002908: 687b ldr r3, [r7, #4] 800290a: 0011 movs r1, r2 800290c: 0018 movs r0, r3 800290e: f000 fa43 bl 8002d98 } else { /* Nothing to do */ } } 8002912: e058 b.n 80029c6 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 8002914: 687b ldr r3, [r7, #4] 8002916: 2241 movs r2, #65 @ 0x41 8002918: 5c9b ldrb r3, [r3, r2] 800291a: b2db uxtb r3, r3 800291c: 2b21 cmp r3, #33 @ 0x21 800291e: d126 bne.n 800296e hi2c->State = HAL_I2C_STATE_READY; 8002920: 687b ldr r3, [r7, #4] 8002922: 2241 movs r2, #65 @ 0x41 8002924: 2120 movs r1, #32 8002926: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002928: 687b ldr r3, [r7, #4] 800292a: 2200 movs r2, #0 800292c: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 800292e: 687b ldr r3, [r7, #4] 8002930: 2242 movs r2, #66 @ 0x42 8002932: 5c9b ldrb r3, [r3, r2] 8002934: b2db uxtb r3, r3 8002936: 2b40 cmp r3, #64 @ 0x40 8002938: d10c bne.n 8002954 hi2c->Mode = HAL_I2C_MODE_NONE; 800293a: 687b ldr r3, [r7, #4] 800293c: 2242 movs r2, #66 @ 0x42 800293e: 2100 movs r1, #0 8002940: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 8002942: 687b ldr r3, [r7, #4] 8002944: 2240 movs r2, #64 @ 0x40 8002946: 2100 movs r1, #0 8002948: 5499 strb r1, [r3, r2] HAL_I2C_MemTxCpltCallback(hi2c); 800294a: 687b ldr r3, [r7, #4] 800294c: 0018 movs r0, r3 800294e: f7ff f9fa bl 8001d46 } 8002952: e038 b.n 80029c6 hi2c->Mode = HAL_I2C_MODE_NONE; 8002954: 687b ldr r3, [r7, #4] 8002956: 2242 movs r2, #66 @ 0x42 8002958: 2100 movs r1, #0 800295a: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 800295c: 687b ldr r3, [r7, #4] 800295e: 2240 movs r2, #64 @ 0x40 8002960: 2100 movs r1, #0 8002962: 5499 strb r1, [r3, r2] HAL_I2C_MasterTxCpltCallback(hi2c); 8002964: 687b ldr r3, [r7, #4] 8002966: 0018 movs r0, r3 8002968: f7ff f9dd bl 8001d26 } 800296c: e02b b.n 80029c6 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 800296e: 687b ldr r3, [r7, #4] 8002970: 2241 movs r2, #65 @ 0x41 8002972: 5c9b ldrb r3, [r3, r2] 8002974: b2db uxtb r3, r3 8002976: 2b22 cmp r3, #34 @ 0x22 8002978: d125 bne.n 80029c6 hi2c->State = HAL_I2C_STATE_READY; 800297a: 687b ldr r3, [r7, #4] 800297c: 2241 movs r2, #65 @ 0x41 800297e: 2120 movs r1, #32 8002980: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002982: 687b ldr r3, [r7, #4] 8002984: 2200 movs r2, #0 8002986: 631a str r2, [r3, #48] @ 0x30 if (hi2c->Mode == HAL_I2C_MODE_MEM) 8002988: 687b ldr r3, [r7, #4] 800298a: 2242 movs r2, #66 @ 0x42 800298c: 5c9b ldrb r3, [r3, r2] 800298e: b2db uxtb r3, r3 8002990: 2b40 cmp r3, #64 @ 0x40 8002992: d10c bne.n 80029ae hi2c->Mode = HAL_I2C_MODE_NONE; 8002994: 687b ldr r3, [r7, #4] 8002996: 2242 movs r2, #66 @ 0x42 8002998: 2100 movs r1, #0 800299a: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 800299c: 687b ldr r3, [r7, #4] 800299e: 2240 movs r2, #64 @ 0x40 80029a0: 2100 movs r1, #0 80029a2: 5499 strb r1, [r3, r2] HAL_I2C_MemRxCpltCallback(hi2c); 80029a4: 687b ldr r3, [r7, #4] 80029a6: 0018 movs r0, r3 80029a8: f7ff f9d5 bl 8001d56 } 80029ac: e00b b.n 80029c6 hi2c->Mode = HAL_I2C_MODE_NONE; 80029ae: 687b ldr r3, [r7, #4] 80029b0: 2242 movs r2, #66 @ 0x42 80029b2: 2100 movs r1, #0 80029b4: 5499 strb r1, [r3, r2] __HAL_UNLOCK(hi2c); 80029b6: 687b ldr r3, [r7, #4] 80029b8: 2240 movs r2, #64 @ 0x40 80029ba: 2100 movs r1, #0 80029bc: 5499 strb r1, [r3, r2] HAL_I2C_MasterRxCpltCallback(hi2c); 80029be: 687b ldr r3, [r7, #4] 80029c0: 0018 movs r0, r3 80029c2: f7ff f9b8 bl 8001d36 } 80029c6: 46c0 nop @ (mov r8, r8) 80029c8: 46bd mov sp, r7 80029ca: b006 add sp, #24 80029cc: bd80 pop {r7, pc} 80029ce: 46c0 nop @ (mov r8, r8) 80029d0: fe00e800 .word 0xfe00e800 80029d4: ffff0000 .word 0xffff0000 080029d8 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 80029d8: b580 push {r7, lr} 80029da: b086 sub sp, #24 80029dc: af00 add r7, sp, #0 80029de: 6078 str r0, [r7, #4] 80029e0: 6039 str r1, [r7, #0] uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); 80029e2: 687b ldr r3, [r7, #4] 80029e4: 681b ldr r3, [r3, #0] 80029e6: 681b ldr r3, [r3, #0] 80029e8: 613b str r3, [r7, #16] uint32_t tmpITFlags = ITFlags; 80029ea: 683b ldr r3, [r7, #0] 80029ec: 617b str r3, [r7, #20] uint32_t tmpoptions = hi2c->XferOptions; 80029ee: 687b ldr r3, [r7, #4] 80029f0: 6adb ldr r3, [r3, #44] @ 0x2c 80029f2: 60fb str r3, [r7, #12] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 80029f4: 200b movs r0, #11 80029f6: 183b adds r3, r7, r0 80029f8: 687a ldr r2, [r7, #4] 80029fa: 2141 movs r1, #65 @ 0x41 80029fc: 5c52 ldrb r2, [r2, r1] 80029fe: 701a strb r2, [r3, #0] /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8002a00: 687b ldr r3, [r7, #4] 8002a02: 681b ldr r3, [r3, #0] 8002a04: 2220 movs r2, #32 8002a06: 61da str r2, [r3, #28] /* Disable Interrupts and Store Previous state */ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) 8002a08: 183b adds r3, r7, r0 8002a0a: 781b ldrb r3, [r3, #0] 8002a0c: 2b21 cmp r3, #33 @ 0x21 8002a0e: d003 beq.n 8002a18 8002a10: 183b adds r3, r7, r0 8002a12: 781b ldrb r3, [r3, #0] 8002a14: 2b29 cmp r3, #41 @ 0x29 8002a16: d109 bne.n 8002a2c { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); 8002a18: 4aac ldr r2, [pc, #688] @ (8002ccc ) 8002a1a: 687b ldr r3, [r7, #4] 8002a1c: 0011 movs r1, r2 8002a1e: 0018 movs r0, r3 8002a20: f000 fbea bl 80031f8 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 8002a24: 687b ldr r3, [r7, #4] 8002a26: 2221 movs r2, #33 @ 0x21 8002a28: 631a str r2, [r3, #48] @ 0x30 8002a2a: e020 b.n 8002a6e } else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) 8002a2c: 220b movs r2, #11 8002a2e: 18bb adds r3, r7, r2 8002a30: 781b ldrb r3, [r3, #0] 8002a32: 2b22 cmp r3, #34 @ 0x22 8002a34: d003 beq.n 8002a3e 8002a36: 18bb adds r3, r7, r2 8002a38: 781b ldrb r3, [r3, #0] 8002a3a: 2b2a cmp r3, #42 @ 0x2a 8002a3c: d109 bne.n 8002a52 { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); 8002a3e: 4aa4 ldr r2, [pc, #656] @ (8002cd0 ) 8002a40: 687b ldr r3, [r7, #4] 8002a42: 0011 movs r1, r2 8002a44: 0018 movs r0, r3 8002a46: f000 fbd7 bl 80031f8 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 8002a4a: 687b ldr r3, [r7, #4] 8002a4c: 2222 movs r2, #34 @ 0x22 8002a4e: 631a str r2, [r3, #48] @ 0x30 8002a50: e00d b.n 8002a6e } else if (tmpstate == HAL_I2C_STATE_LISTEN) 8002a52: 230b movs r3, #11 8002a54: 18fb adds r3, r7, r3 8002a56: 781b ldrb r3, [r3, #0] 8002a58: 2b28 cmp r3, #40 @ 0x28 8002a5a: d108 bne.n 8002a6e { I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); 8002a5c: 4a9d ldr r2, [pc, #628] @ (8002cd4 ) 8002a5e: 687b ldr r3, [r7, #4] 8002a60: 0011 movs r1, r2 8002a62: 0018 movs r0, r3 8002a64: f000 fbc8 bl 80031f8 hi2c->PreviousState = I2C_STATE_NONE; 8002a68: 687b ldr r3, [r7, #4] 8002a6a: 2200 movs r2, #0 8002a6c: 631a str r2, [r3, #48] @ 0x30 { /* Do nothing */ } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; 8002a6e: 687b ldr r3, [r7, #4] 8002a70: 681b ldr r3, [r3, #0] 8002a72: 685a ldr r2, [r3, #4] 8002a74: 687b ldr r3, [r7, #4] 8002a76: 681b ldr r3, [r3, #0] 8002a78: 2180 movs r1, #128 @ 0x80 8002a7a: 0209 lsls r1, r1, #8 8002a7c: 430a orrs r2, r1 8002a7e: 605a str r2, [r3, #4] /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); 8002a80: 687b ldr r3, [r7, #4] 8002a82: 681b ldr r3, [r3, #0] 8002a84: 685a ldr r2, [r3, #4] 8002a86: 687b ldr r3, [r7, #4] 8002a88: 681b ldr r3, [r3, #0] 8002a8a: 4993 ldr r1, [pc, #588] @ (8002cd8 ) 8002a8c: 400a ands r2, r1 8002a8e: 605a str r2, [r3, #4] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8002a90: 687b ldr r3, [r7, #4] 8002a92: 0018 movs r0, r3 8002a94: f000 faab bl 8002fee /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) 8002a98: 693a ldr r2, [r7, #16] 8002a9a: 2380 movs r3, #128 @ 0x80 8002a9c: 01db lsls r3, r3, #7 8002a9e: 4013 ands r3, r2 8002aa0: d013 beq.n 8002aca { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8002aa2: 687b ldr r3, [r7, #4] 8002aa4: 681b ldr r3, [r3, #0] 8002aa6: 681a ldr r2, [r3, #0] 8002aa8: 687b ldr r3, [r7, #4] 8002aaa: 681b ldr r3, [r3, #0] 8002aac: 498b ldr r1, [pc, #556] @ (8002cdc ) 8002aae: 400a ands r2, r1 8002ab0: 601a str r2, [r3, #0] if (hi2c->hdmatx != NULL) 8002ab2: 687b ldr r3, [r7, #4] 8002ab4: 6b9b ldr r3, [r3, #56] @ 0x38 8002ab6: 2b00 cmp r3, #0 8002ab8: d01f beq.n 8002afa { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); 8002aba: 687b ldr r3, [r7, #4] 8002abc: 6b9b ldr r3, [r3, #56] @ 0x38 8002abe: 681b ldr r3, [r3, #0] 8002ac0: 685b ldr r3, [r3, #4] 8002ac2: b29a uxth r2, r3 8002ac4: 687b ldr r3, [r7, #4] 8002ac6: 855a strh r2, [r3, #42] @ 0x2a 8002ac8: e017 b.n 8002afa } } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) 8002aca: 693a ldr r2, [r7, #16] 8002acc: 2380 movs r3, #128 @ 0x80 8002ace: 021b lsls r3, r3, #8 8002ad0: 4013 ands r3, r2 8002ad2: d012 beq.n 8002afa { /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8002ad4: 687b ldr r3, [r7, #4] 8002ad6: 681b ldr r3, [r3, #0] 8002ad8: 681a ldr r2, [r3, #0] 8002ada: 687b ldr r3, [r7, #4] 8002adc: 681b ldr r3, [r3, #0] 8002ade: 4980 ldr r1, [pc, #512] @ (8002ce0 ) 8002ae0: 400a ands r2, r1 8002ae2: 601a str r2, [r3, #0] if (hi2c->hdmarx != NULL) 8002ae4: 687b ldr r3, [r7, #4] 8002ae6: 6bdb ldr r3, [r3, #60] @ 0x3c 8002ae8: 2b00 cmp r3, #0 8002aea: d006 beq.n 8002afa { hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); 8002aec: 687b ldr r3, [r7, #4] 8002aee: 6bdb ldr r3, [r3, #60] @ 0x3c 8002af0: 681b ldr r3, [r3, #0] 8002af2: 685b ldr r3, [r3, #4] 8002af4: b29a uxth r2, r3 8002af6: 687b ldr r3, [r7, #4] 8002af8: 855a strh r2, [r3, #42] @ 0x2a { /* Do nothing */ } /* Store Last receive data if any */ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) 8002afa: 697b ldr r3, [r7, #20] 8002afc: 2204 movs r2, #4 8002afe: 4013 ands r3, r2 8002b00: d020 beq.n 8002b44 { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; 8002b02: 697b ldr r3, [r7, #20] 8002b04: 2204 movs r2, #4 8002b06: 4393 bics r3, r2 8002b08: 617b str r3, [r7, #20] /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8002b0a: 687b ldr r3, [r7, #4] 8002b0c: 681b ldr r3, [r3, #0] 8002b0e: 6a5a ldr r2, [r3, #36] @ 0x24 8002b10: 687b ldr r3, [r7, #4] 8002b12: 6a5b ldr r3, [r3, #36] @ 0x24 8002b14: b2d2 uxtb r2, r2 8002b16: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002b18: 687b ldr r3, [r7, #4] 8002b1a: 6a5b ldr r3, [r3, #36] @ 0x24 8002b1c: 1c5a adds r2, r3, #1 8002b1e: 687b ldr r3, [r7, #4] 8002b20: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 8002b22: 687b ldr r3, [r7, #4] 8002b24: 8d1b ldrh r3, [r3, #40] @ 0x28 8002b26: 2b00 cmp r3, #0 8002b28: d00c beq.n 8002b44 { hi2c->XferSize--; 8002b2a: 687b ldr r3, [r7, #4] 8002b2c: 8d1b ldrh r3, [r3, #40] @ 0x28 8002b2e: 3b01 subs r3, #1 8002b30: b29a uxth r2, r3 8002b32: 687b ldr r3, [r7, #4] 8002b34: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8002b36: 687b ldr r3, [r7, #4] 8002b38: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002b3a: b29b uxth r3, r3 8002b3c: 3b01 subs r3, #1 8002b3e: b29a uxth r2, r3 8002b40: 687b ldr r3, [r7, #4] 8002b42: 855a strh r2, [r3, #42] @ 0x2a } } /* All data are not transferred, so set error code accordingly */ if (hi2c->XferCount != 0U) 8002b44: 687b ldr r3, [r7, #4] 8002b46: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002b48: b29b uxth r3, r3 8002b4a: 2b00 cmp r3, #0 8002b4c: d005 beq.n 8002b5a { /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8002b4e: 687b ldr r3, [r7, #4] 8002b50: 6c5b ldr r3, [r3, #68] @ 0x44 8002b52: 2204 movs r2, #4 8002b54: 431a orrs r2, r3 8002b56: 687b ldr r3, [r7, #4] 8002b58: 645a str r2, [r3, #68] @ 0x44 } if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8002b5a: 697b ldr r3, [r7, #20] 8002b5c: 2210 movs r2, #16 8002b5e: 4013 ands r3, r2 8002b60: d04f beq.n 8002c02 (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) 8002b62: 693b ldr r3, [r7, #16] 8002b64: 2210 movs r2, #16 8002b66: 4013 ands r3, r2 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ 8002b68: d04b beq.n 8002c02 { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ /* Mean XferCount == 0*/ /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) 8002b6a: 687b ldr r3, [r7, #4] 8002b6c: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002b6e: b29b uxth r3, r3 8002b70: 2b00 cmp r3, #0 8002b72: d12d bne.n 8002bd0 { if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) 8002b74: 687b ldr r3, [r7, #4] 8002b76: 2241 movs r2, #65 @ 0x41 8002b78: 5c9b ldrb r3, [r3, r2] 8002b7a: b2db uxtb r3, r3 8002b7c: 2b28 cmp r3, #40 @ 0x28 8002b7e: d10b bne.n 8002b98 8002b80: 68fa ldr r2, [r7, #12] 8002b82: 2380 movs r3, #128 @ 0x80 8002b84: 049b lsls r3, r3, #18 8002b86: 429a cmp r2, r3 8002b88: d106 bne.n 8002b98 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8002b8a: 697a ldr r2, [r7, #20] 8002b8c: 687b ldr r3, [r7, #4] 8002b8e: 0011 movs r1, r2 8002b90: 0018 movs r0, r3 8002b92: f000 f8a9 bl 8002ce8 8002b96: e034 b.n 8002c02 } else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) 8002b98: 687b ldr r3, [r7, #4] 8002b9a: 2241 movs r2, #65 @ 0x41 8002b9c: 5c9b ldrb r3, [r3, r2] 8002b9e: b2db uxtb r3, r3 8002ba0: 2b29 cmp r3, #41 @ 0x29 8002ba2: d110 bne.n 8002bc6 8002ba4: 68fb ldr r3, [r7, #12] 8002ba6: 4a4f ldr r2, [pc, #316] @ (8002ce4 ) 8002ba8: 4293 cmp r3, r2 8002baa: d00c beq.n 8002bc6 { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002bac: 687b ldr r3, [r7, #4] 8002bae: 681b ldr r3, [r3, #0] 8002bb0: 2210 movs r2, #16 8002bb2: 61da str r2, [r3, #28] /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8002bb4: 687b ldr r3, [r7, #4] 8002bb6: 0018 movs r0, r3 8002bb8: f000 fa19 bl 8002fee /* Last Byte is Transmitted */ /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSeqCplt(hi2c); 8002bbc: 687b ldr r3, [r7, #4] 8002bbe: 0018 movs r0, r3 8002bc0: f7ff fdd8 bl 8002774 8002bc4: e01d b.n 8002c02 } else { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002bc6: 687b ldr r3, [r7, #4] 8002bc8: 681b ldr r3, [r3, #0] 8002bca: 2210 movs r2, #16 8002bcc: 61da str r2, [r3, #28] 8002bce: e018 b.n 8002c02 } else { /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002bd0: 687b ldr r3, [r7, #4] 8002bd2: 681b ldr r3, [r3, #0] 8002bd4: 2210 movs r2, #16 8002bd6: 61da str r2, [r3, #28] /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8002bd8: 687b ldr r3, [r7, #4] 8002bda: 6c5b ldr r3, [r3, #68] @ 0x44 8002bdc: 2204 movs r2, #4 8002bde: 431a orrs r2, r3 8002be0: 687b ldr r3, [r7, #4] 8002be2: 645a str r2, [r3, #68] @ 0x44 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) 8002be4: 68fb ldr r3, [r7, #12] 8002be6: 2b00 cmp r3, #0 8002be8: d004 beq.n 8002bf4 8002bea: 68fa ldr r2, [r7, #12] 8002bec: 2380 movs r3, #128 @ 0x80 8002bee: 045b lsls r3, r3, #17 8002bf0: 429a cmp r2, r3 8002bf2: d106 bne.n 8002c02 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002bf4: 687b ldr r3, [r7, #4] 8002bf6: 6c5a ldr r2, [r3, #68] @ 0x44 8002bf8: 687b ldr r3, [r7, #4] 8002bfa: 0011 movs r1, r2 8002bfc: 0018 movs r0, r3 8002bfe: f000 f8cb bl 8002d98 } } } hi2c->Mode = HAL_I2C_MODE_NONE; 8002c02: 687b ldr r3, [r7, #4] 8002c04: 2242 movs r2, #66 @ 0x42 8002c06: 2100 movs r1, #0 8002c08: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 8002c0a: 687b ldr r3, [r7, #4] 8002c0c: 2200 movs r2, #0 8002c0e: 635a str r2, [r3, #52] @ 0x34 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 8002c10: 687b ldr r3, [r7, #4] 8002c12: 6c5b ldr r3, [r3, #68] @ 0x44 8002c14: 2b00 cmp r3, #0 8002c16: d013 beq.n 8002c40 { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); 8002c18: 687b ldr r3, [r7, #4] 8002c1a: 6c5a ldr r2, [r3, #68] @ 0x44 8002c1c: 687b ldr r3, [r7, #4] 8002c1e: 0011 movs r1, r2 8002c20: 0018 movs r0, r3 8002c22: f000 f8b9 bl 8002d98 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ if (hi2c->State == HAL_I2C_STATE_LISTEN) 8002c26: 687b ldr r3, [r7, #4] 8002c28: 2241 movs r2, #65 @ 0x41 8002c2a: 5c9b ldrb r3, [r3, r2] 8002c2c: b2db uxtb r3, r3 8002c2e: 2b28 cmp r3, #40 @ 0x28 8002c30: d147 bne.n 8002cc2 { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); 8002c32: 697a ldr r2, [r7, #20] 8002c34: 687b ldr r3, [r7, #4] 8002c36: 0011 movs r1, r2 8002c38: 0018 movs r0, r3 8002c3a: f000 f855 bl 8002ce8 hi2c->SlaveTxCpltCallback(hi2c); #else HAL_I2C_SlaveTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8002c3e: e040 b.n 8002cc2 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) 8002c40: 687b ldr r3, [r7, #4] 8002c42: 6adb ldr r3, [r3, #44] @ 0x2c 8002c44: 4a27 ldr r2, [pc, #156] @ (8002ce4 ) 8002c46: 4293 cmp r3, r2 8002c48: d016 beq.n 8002c78 I2C_ITSlaveSeqCplt(hi2c); 8002c4a: 687b ldr r3, [r7, #4] 8002c4c: 0018 movs r0, r3 8002c4e: f7ff fd91 bl 8002774 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002c52: 687b ldr r3, [r7, #4] 8002c54: 4a23 ldr r2, [pc, #140] @ (8002ce4 ) 8002c56: 62da str r2, [r3, #44] @ 0x2c hi2c->State = HAL_I2C_STATE_READY; 8002c58: 687b ldr r3, [r7, #4] 8002c5a: 2241 movs r2, #65 @ 0x41 8002c5c: 2120 movs r1, #32 8002c5e: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002c60: 687b ldr r3, [r7, #4] 8002c62: 2200 movs r2, #0 8002c64: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8002c66: 687b ldr r3, [r7, #4] 8002c68: 2240 movs r2, #64 @ 0x40 8002c6a: 2100 movs r1, #0 8002c6c: 5499 strb r1, [r3, r2] HAL_I2C_ListenCpltCallback(hi2c); 8002c6e: 687b ldr r3, [r7, #4] 8002c70: 0018 movs r0, r3 8002c72: f7fd fd69 bl 8000748 } 8002c76: e024 b.n 8002cc2 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 8002c78: 687b ldr r3, [r7, #4] 8002c7a: 2241 movs r2, #65 @ 0x41 8002c7c: 5c9b ldrb r3, [r3, r2] 8002c7e: b2db uxtb r3, r3 8002c80: 2b22 cmp r3, #34 @ 0x22 8002c82: d10f bne.n 8002ca4 hi2c->State = HAL_I2C_STATE_READY; 8002c84: 687b ldr r3, [r7, #4] 8002c86: 2241 movs r2, #65 @ 0x41 8002c88: 2120 movs r1, #32 8002c8a: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002c8c: 687b ldr r3, [r7, #4] 8002c8e: 2200 movs r2, #0 8002c90: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8002c92: 687b ldr r3, [r7, #4] 8002c94: 2240 movs r2, #64 @ 0x40 8002c96: 2100 movs r1, #0 8002c98: 5499 strb r1, [r3, r2] HAL_I2C_SlaveRxCpltCallback(hi2c); 8002c9a: 687b ldr r3, [r7, #4] 8002c9c: 0018 movs r0, r3 8002c9e: f7fd fe4f bl 8000940 } 8002ca2: e00e b.n 8002cc2 hi2c->State = HAL_I2C_STATE_READY; 8002ca4: 687b ldr r3, [r7, #4] 8002ca6: 2241 movs r2, #65 @ 0x41 8002ca8: 2120 movs r1, #32 8002caa: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002cac: 687b ldr r3, [r7, #4] 8002cae: 2200 movs r2, #0 8002cb0: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8002cb2: 687b ldr r3, [r7, #4] 8002cb4: 2240 movs r2, #64 @ 0x40 8002cb6: 2100 movs r1, #0 8002cb8: 5499 strb r1, [r3, r2] HAL_I2C_SlaveTxCpltCallback(hi2c); 8002cba: 687b ldr r3, [r7, #4] 8002cbc: 0018 movs r0, r3 8002cbe: f7fd fe8f bl 80009e0 } 8002cc2: 46c0 nop @ (mov r8, r8) 8002cc4: 46bd mov sp, r7 8002cc6: b006 add sp, #24 8002cc8: bd80 pop {r7, pc} 8002cca: 46c0 nop @ (mov r8, r8) 8002ccc: 00008001 .word 0x00008001 8002cd0: 00008002 .word 0x00008002 8002cd4: 00008003 .word 0x00008003 8002cd8: fe00e800 .word 0xfe00e800 8002cdc: ffffbfff .word 0xffffbfff 8002ce0: ffff7fff .word 0xffff7fff 8002ce4: ffff0000 .word 0xffff0000 08002ce8 : * @param hi2c I2C handle. * @param ITFlags Interrupt flags to handle. * @retval None */ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { 8002ce8: b580 push {r7, lr} 8002cea: b082 sub sp, #8 8002cec: af00 add r7, sp, #0 8002cee: 6078 str r0, [r7, #4] 8002cf0: 6039 str r1, [r7, #0] /* Reset handle parameters */ hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002cf2: 687b ldr r3, [r7, #4] 8002cf4: 4a26 ldr r2, [pc, #152] @ (8002d90 ) 8002cf6: 62da str r2, [r3, #44] @ 0x2c hi2c->PreviousState = I2C_STATE_NONE; 8002cf8: 687b ldr r3, [r7, #4] 8002cfa: 2200 movs r2, #0 8002cfc: 631a str r2, [r3, #48] @ 0x30 hi2c->State = HAL_I2C_STATE_READY; 8002cfe: 687b ldr r3, [r7, #4] 8002d00: 2241 movs r2, #65 @ 0x41 8002d02: 2120 movs r1, #32 8002d04: 5499 strb r1, [r3, r2] hi2c->Mode = HAL_I2C_MODE_NONE; 8002d06: 687b ldr r3, [r7, #4] 8002d08: 2242 movs r2, #66 @ 0x42 8002d0a: 2100 movs r1, #0 8002d0c: 5499 strb r1, [r3, r2] hi2c->XferISR = NULL; 8002d0e: 687b ldr r3, [r7, #4] 8002d10: 2200 movs r2, #0 8002d12: 635a str r2, [r3, #52] @ 0x34 /* Store Last receive data if any */ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) 8002d14: 683b ldr r3, [r7, #0] 8002d16: 2204 movs r2, #4 8002d18: 4013 ands r3, r2 8002d1a: d022 beq.n 8002d62 { /* Read data from RXDR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; 8002d1c: 687b ldr r3, [r7, #4] 8002d1e: 681b ldr r3, [r3, #0] 8002d20: 6a5a ldr r2, [r3, #36] @ 0x24 8002d22: 687b ldr r3, [r7, #4] 8002d24: 6a5b ldr r3, [r3, #36] @ 0x24 8002d26: b2d2 uxtb r2, r2 8002d28: 701a strb r2, [r3, #0] /* Increment Buffer pointer */ hi2c->pBuffPtr++; 8002d2a: 687b ldr r3, [r7, #4] 8002d2c: 6a5b ldr r3, [r3, #36] @ 0x24 8002d2e: 1c5a adds r2, r3, #1 8002d30: 687b ldr r3, [r7, #4] 8002d32: 625a str r2, [r3, #36] @ 0x24 if ((hi2c->XferSize > 0U)) 8002d34: 687b ldr r3, [r7, #4] 8002d36: 8d1b ldrh r3, [r3, #40] @ 0x28 8002d38: 2b00 cmp r3, #0 8002d3a: d012 beq.n 8002d62 { hi2c->XferSize--; 8002d3c: 687b ldr r3, [r7, #4] 8002d3e: 8d1b ldrh r3, [r3, #40] @ 0x28 8002d40: 3b01 subs r3, #1 8002d42: b29a uxth r2, r3 8002d44: 687b ldr r3, [r7, #4] 8002d46: 851a strh r2, [r3, #40] @ 0x28 hi2c->XferCount--; 8002d48: 687b ldr r3, [r7, #4] 8002d4a: 8d5b ldrh r3, [r3, #42] @ 0x2a 8002d4c: b29b uxth r3, r3 8002d4e: 3b01 subs r3, #1 8002d50: b29a uxth r2, r3 8002d52: 687b ldr r3, [r7, #4] 8002d54: 855a strh r2, [r3, #42] @ 0x2a /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8002d56: 687b ldr r3, [r7, #4] 8002d58: 6c5b ldr r3, [r3, #68] @ 0x44 8002d5a: 2204 movs r2, #4 8002d5c: 431a orrs r2, r3 8002d5e: 687b ldr r3, [r7, #4] 8002d60: 645a str r2, [r3, #68] @ 0x44 } } /* Disable all Interrupts*/ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8002d62: 4a0c ldr r2, [pc, #48] @ (8002d94 ) 8002d64: 687b ldr r3, [r7, #4] 8002d66: 0011 movs r1, r2 8002d68: 0018 movs r0, r3 8002d6a: f000 fa45 bl 80031f8 /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002d6e: 687b ldr r3, [r7, #4] 8002d70: 681b ldr r3, [r3, #0] 8002d72: 2210 movs r2, #16 8002d74: 61da str r2, [r3, #28] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002d76: 687b ldr r3, [r7, #4] 8002d78: 2240 movs r2, #64 @ 0x40 8002d7a: 2100 movs r1, #0 8002d7c: 5499 strb r1, [r3, r2] /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->ListenCpltCallback(hi2c); #else HAL_I2C_ListenCpltCallback(hi2c); 8002d7e: 687b ldr r3, [r7, #4] 8002d80: 0018 movs r0, r3 8002d82: f7fd fce1 bl 8000748 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } 8002d86: 46c0 nop @ (mov r8, r8) 8002d88: 46bd mov sp, r7 8002d8a: b002 add sp, #8 8002d8c: bd80 pop {r7, pc} 8002d8e: 46c0 nop @ (mov r8, r8) 8002d90: ffff0000 .word 0xffff0000 8002d94: 00008003 .word 0x00008003 08002d98 : * @param hi2c I2C handle. * @param ErrorCode Error code to handle. * @retval None */ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { 8002d98: b580 push {r7, lr} 8002d9a: b084 sub sp, #16 8002d9c: af00 add r7, sp, #0 8002d9e: 6078 str r0, [r7, #4] 8002da0: 6039 str r1, [r7, #0] HAL_I2C_StateTypeDef tmpstate = hi2c->State; 8002da2: 200f movs r0, #15 8002da4: 183b adds r3, r7, r0 8002da6: 687a ldr r2, [r7, #4] 8002da8: 2141 movs r1, #65 @ 0x41 8002daa: 5c52 ldrb r2, [r2, r1] 8002dac: 701a strb r2, [r3, #0] uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; 8002dae: 687b ldr r3, [r7, #4] 8002db0: 2242 movs r2, #66 @ 0x42 8002db2: 2100 movs r1, #0 8002db4: 5499 strb r1, [r3, r2] hi2c->XferOptions = I2C_NO_OPTION_FRAME; 8002db6: 687b ldr r3, [r7, #4] 8002db8: 4a72 ldr r2, [pc, #456] @ (8002f84 ) 8002dba: 62da str r2, [r3, #44] @ 0x2c hi2c->XferCount = 0U; 8002dbc: 687b ldr r3, [r7, #4] 8002dbe: 2200 movs r2, #0 8002dc0: 855a strh r2, [r3, #42] @ 0x2a /* Set new error code */ hi2c->ErrorCode |= ErrorCode; 8002dc2: 687b ldr r3, [r7, #4] 8002dc4: 6c5a ldr r2, [r3, #68] @ 0x44 8002dc6: 683b ldr r3, [r7, #0] 8002dc8: 431a orrs r2, r3 8002dca: 687b ldr r3, [r7, #4] 8002dcc: 645a str r2, [r3, #68] @ 0x44 /* Disable Interrupts */ if ((tmpstate == HAL_I2C_STATE_LISTEN) || 8002dce: 183b adds r3, r7, r0 8002dd0: 781b ldrb r3, [r3, #0] 8002dd2: 2b28 cmp r3, #40 @ 0x28 8002dd4: d007 beq.n 8002de6 8002dd6: 183b adds r3, r7, r0 8002dd8: 781b ldrb r3, [r3, #0] 8002dda: 2b29 cmp r3, #41 @ 0x29 8002ddc: d003 beq.n 8002de6 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || 8002dde: 183b adds r3, r7, r0 8002de0: 781b ldrb r3, [r3, #0] 8002de2: 2b2a cmp r3, #42 @ 0x2a 8002de4: d10c bne.n 8002e00 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) { /* Disable all interrupts, except interrupts related to LISTEN state */ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8002de6: 687b ldr r3, [r7, #4] 8002de8: 2103 movs r1, #3 8002dea: 0018 movs r0, r3 8002dec: f000 fa04 bl 80031f8 /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; 8002df0: 687b ldr r3, [r7, #4] 8002df2: 2241 movs r2, #65 @ 0x41 8002df4: 2128 movs r1, #40 @ 0x28 8002df6: 5499 strb r1, [r3, r2] hi2c->XferISR = I2C_Slave_ISR_IT; 8002df8: 687b ldr r3, [r7, #4] 8002dfa: 4a63 ldr r2, [pc, #396] @ (8002f88 ) 8002dfc: 635a str r2, [r3, #52] @ 0x34 8002dfe: e032 b.n 8002e66 } else { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); 8002e00: 4a62 ldr r2, [pc, #392] @ (8002f8c ) 8002e02: 687b ldr r3, [r7, #4] 8002e04: 0011 movs r1, r2 8002e06: 0018 movs r0, r3 8002e08: f000 f9f6 bl 80031f8 /* Flush TX register */ I2C_Flush_TXDR(hi2c); 8002e0c: 687b ldr r3, [r7, #4] 8002e0e: 0018 movs r0, r3 8002e10: f000 f8ed bl 8002fee /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) 8002e14: 687b ldr r3, [r7, #4] 8002e16: 2241 movs r2, #65 @ 0x41 8002e18: 5c9b ldrb r3, [r3, r2] 8002e1a: b2db uxtb r3, r3 8002e1c: 2b60 cmp r3, #96 @ 0x60 8002e1e: d01f beq.n 8002e60 { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; 8002e20: 687b ldr r3, [r7, #4] 8002e22: 2241 movs r2, #65 @ 0x41 8002e24: 2120 movs r1, #32 8002e26: 5499 strb r1, [r3, r2] /* Check if a STOPF is detected */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 8002e28: 687b ldr r3, [r7, #4] 8002e2a: 681b ldr r3, [r3, #0] 8002e2c: 699b ldr r3, [r3, #24] 8002e2e: 2220 movs r2, #32 8002e30: 4013 ands r3, r2 8002e32: 2b20 cmp r3, #32 8002e34: d114 bne.n 8002e60 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 8002e36: 687b ldr r3, [r7, #4] 8002e38: 681b ldr r3, [r3, #0] 8002e3a: 699b ldr r3, [r3, #24] 8002e3c: 2210 movs r2, #16 8002e3e: 4013 ands r3, r2 8002e40: 2b10 cmp r3, #16 8002e42: d109 bne.n 8002e58 { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 8002e44: 687b ldr r3, [r7, #4] 8002e46: 681b ldr r3, [r3, #0] 8002e48: 2210 movs r2, #16 8002e4a: 61da str r2, [r3, #28] hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 8002e4c: 687b ldr r3, [r7, #4] 8002e4e: 6c5b ldr r3, [r3, #68] @ 0x44 8002e50: 2204 movs r2, #4 8002e52: 431a orrs r2, r3 8002e54: 687b ldr r3, [r7, #4] 8002e56: 645a str r2, [r3, #68] @ 0x44 } /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 8002e58: 687b ldr r3, [r7, #4] 8002e5a: 681b ldr r3, [r3, #0] 8002e5c: 2220 movs r2, #32 8002e5e: 61da str r2, [r3, #28] } } hi2c->XferISR = NULL; 8002e60: 687b ldr r3, [r7, #4] 8002e62: 2200 movs r2, #0 8002e64: 635a str r2, [r3, #52] @ 0x34 } /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; 8002e66: 687b ldr r3, [r7, #4] 8002e68: 6b1b ldr r3, [r3, #48] @ 0x30 8002e6a: 60bb str r3, [r7, #8] if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ 8002e6c: 687b ldr r3, [r7, #4] 8002e6e: 6b9b ldr r3, [r3, #56] @ 0x38 8002e70: 2b00 cmp r3, #0 8002e72: d03b beq.n 8002eec 8002e74: 68bb ldr r3, [r7, #8] 8002e76: 2b11 cmp r3, #17 8002e78: d002 beq.n 8002e80 8002e7a: 68bb ldr r3, [r7, #8] 8002e7c: 2b21 cmp r3, #33 @ 0x21 8002e7e: d135 bne.n 8002eec (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) 8002e80: 687b ldr r3, [r7, #4] 8002e82: 681b ldr r3, [r3, #0] 8002e84: 681a ldr r2, [r3, #0] 8002e86: 2380 movs r3, #128 @ 0x80 8002e88: 01db lsls r3, r3, #7 8002e8a: 401a ands r2, r3 8002e8c: 2380 movs r3, #128 @ 0x80 8002e8e: 01db lsls r3, r3, #7 8002e90: 429a cmp r2, r3 8002e92: d107 bne.n 8002ea4 { hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; 8002e94: 687b ldr r3, [r7, #4] 8002e96: 681b ldr r3, [r3, #0] 8002e98: 681a ldr r2, [r3, #0] 8002e9a: 687b ldr r3, [r7, #4] 8002e9c: 681b ldr r3, [r3, #0] 8002e9e: 493c ldr r1, [pc, #240] @ (8002f90 ) 8002ea0: 400a ands r2, r1 8002ea2: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002ea4: 687b ldr r3, [r7, #4] 8002ea6: 6b9b ldr r3, [r3, #56] @ 0x38 8002ea8: 0018 movs r0, r3 8002eaa: f7fe fad5 bl 8001458 8002eae: 0003 movs r3, r0 8002eb0: 2b01 cmp r3, #1 8002eb2: d016 beq.n 8002ee2 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 8002eb4: 687b ldr r3, [r7, #4] 8002eb6: 6b9b ldr r3, [r3, #56] @ 0x38 8002eb8: 4a36 ldr r2, [pc, #216] @ (8002f94 ) 8002eba: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002ebc: 687b ldr r3, [r7, #4] 8002ebe: 2240 movs r2, #64 @ 0x40 8002ec0: 2100 movs r1, #0 8002ec2: 5499 strb r1, [r3, r2] /* Abort DMA TX */ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 8002ec4: 687b ldr r3, [r7, #4] 8002ec6: 6b9b ldr r3, [r3, #56] @ 0x38 8002ec8: 0018 movs r0, r3 8002eca: f7fe fa5b bl 8001384 8002ece: 1e03 subs r3, r0, #0 8002ed0: d051 beq.n 8002f76 { /* Call Directly XferAbortCallback function in case of error */ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 8002ed2: 687b ldr r3, [r7, #4] 8002ed4: 6b9b ldr r3, [r3, #56] @ 0x38 8002ed6: 6b9a ldr r2, [r3, #56] @ 0x38 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 6b9b ldr r3, [r3, #56] @ 0x38 8002edc: 0018 movs r0, r3 8002ede: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002ee0: e049 b.n 8002f76 } } else { I2C_TreatErrorCallback(hi2c); 8002ee2: 687b ldr r3, [r7, #4] 8002ee4: 0018 movs r0, r3 8002ee6: f000 f859 bl 8002f9c if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002eea: e044 b.n 8002f76 } } /* Abort DMA RX transfer if any */ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ 8002eec: 687b ldr r3, [r7, #4] 8002eee: 6bdb ldr r3, [r3, #60] @ 0x3c 8002ef0: 2b00 cmp r3, #0 8002ef2: d03b beq.n 8002f6c 8002ef4: 68bb ldr r3, [r7, #8] 8002ef6: 2b12 cmp r3, #18 8002ef8: d002 beq.n 8002f00 8002efa: 68bb ldr r3, [r7, #8] 8002efc: 2b22 cmp r3, #34 @ 0x22 8002efe: d135 bne.n 8002f6c (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) 8002f00: 687b ldr r3, [r7, #4] 8002f02: 681b ldr r3, [r3, #0] 8002f04: 681a ldr r2, [r3, #0] 8002f06: 2380 movs r3, #128 @ 0x80 8002f08: 021b lsls r3, r3, #8 8002f0a: 401a ands r2, r3 8002f0c: 2380 movs r3, #128 @ 0x80 8002f0e: 021b lsls r3, r3, #8 8002f10: 429a cmp r2, r3 8002f12: d107 bne.n 8002f24 { hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; 8002f14: 687b ldr r3, [r7, #4] 8002f16: 681b ldr r3, [r3, #0] 8002f18: 681a ldr r2, [r3, #0] 8002f1a: 687b ldr r3, [r7, #4] 8002f1c: 681b ldr r3, [r3, #0] 8002f1e: 491e ldr r1, [pc, #120] @ (8002f98 ) 8002f20: 400a ands r2, r1 8002f22: 601a str r2, [r3, #0] } if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8002f24: 687b ldr r3, [r7, #4] 8002f26: 6bdb ldr r3, [r3, #60] @ 0x3c 8002f28: 0018 movs r0, r3 8002f2a: f7fe fa95 bl 8001458 8002f2e: 0003 movs r3, r0 8002f30: 2b01 cmp r3, #1 8002f32: d016 beq.n 8002f62 { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 8002f34: 687b ldr r3, [r7, #4] 8002f36: 6bdb ldr r3, [r3, #60] @ 0x3c 8002f38: 4a16 ldr r2, [pc, #88] @ (8002f94 ) 8002f3a: 639a str r2, [r3, #56] @ 0x38 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002f3c: 687b ldr r3, [r7, #4] 8002f3e: 2240 movs r2, #64 @ 0x40 8002f40: 2100 movs r1, #0 8002f42: 5499 strb r1, [r3, r2] /* Abort DMA RX */ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 8002f44: 687b ldr r3, [r7, #4] 8002f46: 6bdb ldr r3, [r3, #60] @ 0x3c 8002f48: 0018 movs r0, r3 8002f4a: f7fe fa1b bl 8001384 8002f4e: 1e03 subs r3, r0, #0 8002f50: d013 beq.n 8002f7a { /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 8002f52: 687b ldr r3, [r7, #4] 8002f54: 6bdb ldr r3, [r3, #60] @ 0x3c 8002f56: 6b9a ldr r2, [r3, #56] @ 0x38 8002f58: 687b ldr r3, [r7, #4] 8002f5a: 6bdb ldr r3, [r3, #60] @ 0x3c 8002f5c: 0018 movs r0, r3 8002f5e: 4790 blx r2 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8002f60: e00b b.n 8002f7a } } else { I2C_TreatErrorCallback(hi2c); 8002f62: 687b ldr r3, [r7, #4] 8002f64: 0018 movs r0, r3 8002f66: f000 f819 bl 8002f9c if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8002f6a: e006 b.n 8002f7a } } else { I2C_TreatErrorCallback(hi2c); 8002f6c: 687b ldr r3, [r7, #4] 8002f6e: 0018 movs r0, r3 8002f70: f000 f814 bl 8002f9c } } 8002f74: e002 b.n 8002f7c if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 8002f76: 46c0 nop @ (mov r8, r8) 8002f78: e000 b.n 8002f7c if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 8002f7a: 46c0 nop @ (mov r8, r8) } 8002f7c: 46c0 nop @ (mov r8, r8) 8002f7e: 46bd mov sp, r7 8002f80: b004 add sp, #16 8002f82: bd80 pop {r7, pc} 8002f84: ffff0000 .word 0xffff0000 8002f88: 08001d89 .word 0x08001d89 8002f8c: 00008003 .word 0x00008003 8002f90: ffffbfff .word 0xffffbfff 8002f94: 08003033 .word 0x08003033 8002f98: ffff7fff .word 0xffff7fff 08002f9c : * @brief I2C Error callback treatment. * @param hi2c I2C handle. * @retval None */ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) { 8002f9c: b580 push {r7, lr} 8002f9e: b082 sub sp, #8 8002fa0: af00 add r7, sp, #0 8002fa2: 6078 str r0, [r7, #4] if (hi2c->State == HAL_I2C_STATE_ABORT) 8002fa4: 687b ldr r3, [r7, #4] 8002fa6: 2241 movs r2, #65 @ 0x41 8002fa8: 5c9b ldrb r3, [r3, r2] 8002faa: b2db uxtb r3, r3 8002fac: 2b60 cmp r3, #96 @ 0x60 8002fae: d10f bne.n 8002fd0 { hi2c->State = HAL_I2C_STATE_READY; 8002fb0: 687b ldr r3, [r7, #4] 8002fb2: 2241 movs r2, #65 @ 0x41 8002fb4: 2120 movs r1, #32 8002fb6: 5499 strb r1, [r3, r2] hi2c->PreviousState = I2C_STATE_NONE; 8002fb8: 687b ldr r3, [r7, #4] 8002fba: 2200 movs r2, #0 8002fbc: 631a str r2, [r3, #48] @ 0x30 /* Process Unlocked */ __HAL_UNLOCK(hi2c); 8002fbe: 687b ldr r3, [r7, #4] 8002fc0: 2240 movs r2, #64 @ 0x40 8002fc2: 2100 movs r1, #0 8002fc4: 5499 strb r1, [r3, r2] /* Call the corresponding callback to inform upper layer of End of Transfer */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->AbortCpltCallback(hi2c); #else HAL_I2C_AbortCpltCallback(hi2c); 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 0018 movs r0, r3 8002fca: f7fe fed4 bl 8001d76 hi2c->ErrorCallback(hi2c); #else HAL_I2C_ErrorCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } } 8002fce: e00a b.n 8002fe6 hi2c->PreviousState = I2C_STATE_NONE; 8002fd0: 687b ldr r3, [r7, #4] 8002fd2: 2200 movs r2, #0 8002fd4: 631a str r2, [r3, #48] @ 0x30 __HAL_UNLOCK(hi2c); 8002fd6: 687b ldr r3, [r7, #4] 8002fd8: 2240 movs r2, #64 @ 0x40 8002fda: 2100 movs r1, #0 8002fdc: 5499 strb r1, [r3, r2] HAL_I2C_ErrorCallback(hi2c); 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 0018 movs r0, r3 8002fe2: f7fe fec0 bl 8001d66 } 8002fe6: 46c0 nop @ (mov r8, r8) 8002fe8: 46bd mov sp, r7 8002fea: b002 add sp, #8 8002fec: bd80 pop {r7, pc} 08002fee : * @brief I2C Tx data register flush process. * @param hi2c I2C handle. * @retval None */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) { 8002fee: b580 push {r7, lr} 8002ff0: b082 sub sp, #8 8002ff2: af00 add r7, sp, #0 8002ff4: 6078 str r0, [r7, #4] /* If a pending TXIS flag is set */ /* Write a dummy data in TXDR to clear it */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) 8002ff6: 687b ldr r3, [r7, #4] 8002ff8: 681b ldr r3, [r3, #0] 8002ffa: 699b ldr r3, [r3, #24] 8002ffc: 2202 movs r2, #2 8002ffe: 4013 ands r3, r2 8003000: 2b02 cmp r3, #2 8003002: d103 bne.n 800300c { hi2c->Instance->TXDR = 0x00U; 8003004: 687b ldr r3, [r7, #4] 8003006: 681b ldr r3, [r3, #0] 8003008: 2200 movs r2, #0 800300a: 629a str r2, [r3, #40] @ 0x28 } /* Flush TX register if not empty */ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 800300c: 687b ldr r3, [r7, #4] 800300e: 681b ldr r3, [r3, #0] 8003010: 699b ldr r3, [r3, #24] 8003012: 2201 movs r2, #1 8003014: 4013 ands r3, r2 8003016: 2b01 cmp r3, #1 8003018: d007 beq.n 800302a { __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); 800301a: 687b ldr r3, [r7, #4] 800301c: 681b ldr r3, [r3, #0] 800301e: 699a ldr r2, [r3, #24] 8003020: 687b ldr r3, [r7, #4] 8003022: 681b ldr r3, [r3, #0] 8003024: 2101 movs r1, #1 8003026: 430a orrs r2, r1 8003028: 619a str r2, [r3, #24] } } 800302a: 46c0 nop @ (mov r8, r8) 800302c: 46bd mov sp, r7 800302e: b002 add sp, #8 8003030: bd80 pop {r7, pc} 08003032 : * (To be called at end of DMA Abort procedure). * @param hdma DMA handle. * @retval None */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { 8003032: b580 push {r7, lr} 8003034: b084 sub sp, #16 8003036: af00 add r7, sp, #0 8003038: 6078 str r0, [r7, #4] /* Derogation MISRAC2012-Rule-11.5 */ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); 800303a: 687b ldr r3, [r7, #4] 800303c: 6a9b ldr r3, [r3, #40] @ 0x28 800303e: 60fb str r3, [r7, #12] /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) 8003040: 68fb ldr r3, [r7, #12] 8003042: 6b9b ldr r3, [r3, #56] @ 0x38 8003044: 2b00 cmp r3, #0 8003046: d003 beq.n 8003050 { hi2c->hdmatx->XferAbortCallback = NULL; 8003048: 68fb ldr r3, [r7, #12] 800304a: 6b9b ldr r3, [r3, #56] @ 0x38 800304c: 2200 movs r2, #0 800304e: 639a str r2, [r3, #56] @ 0x38 } if (hi2c->hdmarx != NULL) 8003050: 68fb ldr r3, [r7, #12] 8003052: 6bdb ldr r3, [r3, #60] @ 0x3c 8003054: 2b00 cmp r3, #0 8003056: d003 beq.n 8003060 { hi2c->hdmarx->XferAbortCallback = NULL; 8003058: 68fb ldr r3, [r7, #12] 800305a: 6bdb ldr r3, [r3, #60] @ 0x3c 800305c: 2200 movs r2, #0 800305e: 639a str r2, [r3, #56] @ 0x38 } I2C_TreatErrorCallback(hi2c); 8003060: 68fb ldr r3, [r7, #12] 8003062: 0018 movs r0, r3 8003064: f7ff ff9a bl 8002f9c } 8003068: 46c0 nop @ (mov r8, r8) 800306a: 46bd mov sp, r7 800306c: b004 add sp, #16 800306e: bd80 pop {r7, pc} 08003070 : * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { 8003070: b590 push {r4, r7, lr} 8003072: b087 sub sp, #28 8003074: af00 add r7, sp, #0 8003076: 60f8 str r0, [r7, #12] 8003078: 0008 movs r0, r1 800307a: 0011 movs r1, r2 800307c: 607b str r3, [r7, #4] 800307e: 240a movs r4, #10 8003080: 193b adds r3, r7, r4 8003082: 1c02 adds r2, r0, #0 8003084: 801a strh r2, [r3, #0] 8003086: 2009 movs r0, #9 8003088: 183b adds r3, r7, r0 800308a: 1c0a adds r2, r1, #0 800308c: 701a strb r2, [r3, #0] assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 800308e: 193b adds r3, r7, r4 8003090: 881b ldrh r3, [r3, #0] 8003092: 059b lsls r3, r3, #22 8003094: 0d9a lsrs r2, r3, #22 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 8003096: 183b adds r3, r7, r0 8003098: 781b ldrb r3, [r3, #0] 800309a: 0419 lsls r1, r3, #16 800309c: 23ff movs r3, #255 @ 0xff 800309e: 041b lsls r3, r3, #16 80030a0: 400b ands r3, r1 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 80030a2: 431a orrs r2, r3 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 80030a4: 687b ldr r3, [r7, #4] 80030a6: 431a orrs r2, r3 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ 80030a8: 6abb ldr r3, [r7, #40] @ 0x28 80030aa: 4313 orrs r3, r2 80030ac: 005b lsls r3, r3, #1 80030ae: 085b lsrs r3, r3, #1 80030b0: 617b str r3, [r7, #20] (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ 80030b2: 68fb ldr r3, [r7, #12] 80030b4: 681b ldr r3, [r3, #0] 80030b6: 685b ldr r3, [r3, #4] 80030b8: 6aba ldr r2, [r7, #40] @ 0x28 80030ba: 0d51 lsrs r1, r2, #21 80030bc: 2280 movs r2, #128 @ 0x80 80030be: 00d2 lsls r2, r2, #3 80030c0: 400a ands r2, r1 80030c2: 4907 ldr r1, [pc, #28] @ (80030e0 ) 80030c4: 430a orrs r2, r1 80030c6: 43d2 mvns r2, r2 80030c8: 401a ands r2, r3 80030ca: 0011 movs r1, r2 80030cc: 68fb ldr r3, [r7, #12] 80030ce: 681b ldr r3, [r3, #0] 80030d0: 697a ldr r2, [r7, #20] 80030d2: 430a orrs r2, r1 80030d4: 605a str r2, [r3, #4] ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ I2C_CR2_START | I2C_CR2_STOP)), tmp); } 80030d6: 46c0 nop @ (mov r8, r8) 80030d8: 46bd mov sp, r7 80030da: b007 add sp, #28 80030dc: bd90 pop {r4, r7, pc} 80030de: 46c0 nop @ (mov r8, r8) 80030e0: 03ff63ff .word 0x03ff63ff 080030e4 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80030e4: b580 push {r7, lr} 80030e6: b084 sub sp, #16 80030e8: af00 add r7, sp, #0 80030ea: 6078 str r0, [r7, #4] 80030ec: 000a movs r2, r1 80030ee: 1cbb adds r3, r7, #2 80030f0: 801a strh r2, [r3, #0] uint32_t tmpisr = 0U; 80030f2: 2300 movs r3, #0 80030f4: 60fb str r3, [r7, #12] if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 80030f6: 687b ldr r3, [r7, #4] 80030f8: 6b5a ldr r2, [r3, #52] @ 0x34 80030fa: 4b3c ldr r3, [pc, #240] @ (80031ec ) 80030fc: 429a cmp r2, r3 80030fe: d035 beq.n 800316c (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 8003100: 687b ldr r3, [r7, #4] 8003102: 6b5a ldr r2, [r3, #52] @ 0x34 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ 8003104: 4b3a ldr r3, [pc, #232] @ (80031f0 ) 8003106: 429a cmp r2, r3 8003108: d030 beq.n 800316c (hi2c->XferISR != I2C_Mem_ISR_DMA)) 800310a: 687b ldr r3, [r7, #4] 800310c: 6b5a ldr r2, [r3, #52] @ 0x34 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ 800310e: 4b39 ldr r3, [pc, #228] @ (80031f4 ) 8003110: 429a cmp r2, r3 8003112: d02b beq.n 800316c { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8003114: 1cbb adds r3, r7, #2 8003116: 2200 movs r2, #0 8003118: 5e9b ldrsh r3, [r3, r2] 800311a: 2b00 cmp r3, #0 800311c: da03 bge.n 8003126 { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 800311e: 68fb ldr r3, [r7, #12] 8003120: 22b8 movs r2, #184 @ 0xb8 8003122: 4313 orrs r3, r2 8003124: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 8003126: 1cbb adds r3, r7, #2 8003128: 881b ldrh r3, [r3, #0] 800312a: 2201 movs r2, #1 800312c: 4013 ands r3, r2 800312e: d003 beq.n 8003138 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8003130: 68fb ldr r3, [r7, #12] 8003132: 22f2 movs r2, #242 @ 0xf2 8003134: 4313 orrs r3, r2 8003136: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8003138: 1cbb adds r3, r7, #2 800313a: 881b ldrh r3, [r3, #0] 800313c: 2202 movs r2, #2 800313e: 4013 ands r3, r2 8003140: d003 beq.n 800314a { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 8003142: 68fb ldr r3, [r7, #12] 8003144: 22f4 movs r2, #244 @ 0xf4 8003146: 4313 orrs r3, r2 8003148: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 800314a: 1cbb adds r3, r7, #2 800314c: 881b ldrh r3, [r3, #0] 800314e: 2b10 cmp r3, #16 8003150: d103 bne.n 800315a { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 8003152: 68fb ldr r3, [r7, #12] 8003154: 2290 movs r2, #144 @ 0x90 8003156: 4313 orrs r3, r2 8003158: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 800315a: 1cbb adds r3, r7, #2 800315c: 881b ldrh r3, [r3, #0] 800315e: 2b20 cmp r3, #32 8003160: d137 bne.n 80031d2 { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 8003162: 68fb ldr r3, [r7, #12] 8003164: 2220 movs r2, #32 8003166: 4313 orrs r3, r2 8003168: 60fb str r3, [r7, #12] if (InterruptRequest == I2C_XFER_CPLT_IT) 800316a: e032 b.n 80031d2 } } else { if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 800316c: 1cbb adds r3, r7, #2 800316e: 2200 movs r2, #0 8003170: 5e9b ldrsh r3, [r3, r2] 8003172: 2b00 cmp r3, #0 8003174: da03 bge.n 800317e { /* Enable ERR, STOP, NACK and ADDR interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 8003176: 68fb ldr r3, [r7, #12] 8003178: 22b8 movs r2, #184 @ 0xb8 800317a: 4313 orrs r3, r2 800317c: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 800317e: 1cbb adds r3, r7, #2 8003180: 881b ldrh r3, [r3, #0] 8003182: 2201 movs r2, #1 8003184: 4013 ands r3, r2 8003186: d003 beq.n 8003190 { /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; 8003188: 68fb ldr r3, [r7, #12] 800318a: 22f2 movs r2, #242 @ 0xf2 800318c: 4313 orrs r3, r2 800318e: 60fb str r3, [r7, #12] } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8003190: 1cbb adds r3, r7, #2 8003192: 881b ldrh r3, [r3, #0] 8003194: 2202 movs r2, #2 8003196: 4013 ands r3, r2 8003198: d003 beq.n 80031a2 { /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; 800319a: 68fb ldr r3, [r7, #12] 800319c: 22f4 movs r2, #244 @ 0xf4 800319e: 4313 orrs r3, r2 80031a0: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 80031a2: 1cbb adds r3, r7, #2 80031a4: 881b ldrh r3, [r3, #0] 80031a6: 2b10 cmp r3, #16 80031a8: d103 bne.n 80031b2 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 80031aa: 68fb ldr r3, [r7, #12] 80031ac: 2290 movs r2, #144 @ 0x90 80031ae: 4313 orrs r3, r2 80031b0: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 80031b2: 1cbb adds r3, r7, #2 80031b4: 881b ldrh r3, [r3, #0] 80031b6: 2b20 cmp r3, #32 80031b8: d103 bne.n 80031c2 { /* Enable STOP interrupts */ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); 80031ba: 68fb ldr r3, [r7, #12] 80031bc: 2260 movs r2, #96 @ 0x60 80031be: 4313 orrs r3, r2 80031c0: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 80031c2: 1cbb adds r3, r7, #2 80031c4: 881b ldrh r3, [r3, #0] 80031c6: 2b40 cmp r3, #64 @ 0x40 80031c8: d103 bne.n 80031d2 { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 80031ca: 68fb ldr r3, [r7, #12] 80031cc: 2240 movs r2, #64 @ 0x40 80031ce: 4313 orrs r3, r2 80031d0: 60fb str r3, [r7, #12] } /* Enable interrupts only at the end */ /* to avoid the risk of I2C interrupt handle execution before */ /* all interrupts requested done */ __HAL_I2C_ENABLE_IT(hi2c, tmpisr); 80031d2: 687b ldr r3, [r7, #4] 80031d4: 681b ldr r3, [r3, #0] 80031d6: 6819 ldr r1, [r3, #0] 80031d8: 687b ldr r3, [r7, #4] 80031da: 681b ldr r3, [r3, #0] 80031dc: 68fa ldr r2, [r7, #12] 80031de: 430a orrs r2, r1 80031e0: 601a str r2, [r3, #0] } 80031e2: 46c0 nop @ (mov r8, r8) 80031e4: 46bd mov sp, r7 80031e6: b004 add sp, #16 80031e8: bd80 pop {r7, pc} 80031ea: 46c0 nop @ (mov r8, r8) 80031ec: 08001f89 .word 0x08001f89 80031f0: 080023d9 .word 0x080023d9 80031f4: 08002181 .word 0x08002181 080031f8 : * the configuration information for the specified I2C. * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. * @retval None */ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) { 80031f8: b580 push {r7, lr} 80031fa: b084 sub sp, #16 80031fc: af00 add r7, sp, #0 80031fe: 6078 str r0, [r7, #4] 8003200: 000a movs r2, r1 8003202: 1cbb adds r3, r7, #2 8003204: 801a strh r2, [r3, #0] uint32_t tmpisr = 0U; 8003206: 2300 movs r3, #0 8003208: 60fb str r3, [r7, #12] if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) 800320a: 1cbb adds r3, r7, #2 800320c: 881b ldrh r3, [r3, #0] 800320e: 2201 movs r2, #1 8003210: 4013 ands r3, r2 8003212: d010 beq.n 8003236 { /* Disable TC and TXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_TXI; 8003214: 68fb ldr r3, [r7, #12] 8003216: 2242 movs r2, #66 @ 0x42 8003218: 4313 orrs r3, r2 800321a: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 800321c: 687b ldr r3, [r7, #4] 800321e: 2241 movs r2, #65 @ 0x41 8003220: 5c9b ldrb r3, [r3, r2] 8003222: b2db uxtb r3, r3 8003224: 001a movs r2, r3 8003226: 2328 movs r3, #40 @ 0x28 8003228: 4013 ands r3, r2 800322a: 2b28 cmp r3, #40 @ 0x28 800322c: d003 beq.n 8003236 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 800322e: 68fb ldr r3, [r7, #12] 8003230: 22b0 movs r2, #176 @ 0xb0 8003232: 4313 orrs r3, r2 8003234: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) 8003236: 1cbb adds r3, r7, #2 8003238: 881b ldrh r3, [r3, #0] 800323a: 2202 movs r2, #2 800323c: 4013 ands r3, r2 800323e: d010 beq.n 8003262 { /* Disable TC and RXI interrupts */ tmpisr |= I2C_IT_TCI | I2C_IT_RXI; 8003240: 68fb ldr r3, [r7, #12] 8003242: 2244 movs r2, #68 @ 0x44 8003244: 4313 orrs r3, r2 8003246: 60fb str r3, [r7, #12] if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) 8003248: 687b ldr r3, [r7, #4] 800324a: 2241 movs r2, #65 @ 0x41 800324c: 5c9b ldrb r3, [r3, r2] 800324e: b2db uxtb r3, r3 8003250: 001a movs r2, r3 8003252: 2328 movs r3, #40 @ 0x28 8003254: 4013 ands r3, r2 8003256: 2b28 cmp r3, #40 @ 0x28 8003258: d003 beq.n 8003262 { /* Disable NACK and STOP interrupts */ tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 800325a: 68fb ldr r3, [r7, #12] 800325c: 22b0 movs r2, #176 @ 0xb0 800325e: 4313 orrs r3, r2 8003260: 60fb str r3, [r7, #12] } } if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) 8003262: 1cbb adds r3, r7, #2 8003264: 2200 movs r2, #0 8003266: 5e9b ldrsh r3, [r3, r2] 8003268: 2b00 cmp r3, #0 800326a: da03 bge.n 8003274 { /* Disable ADDR, NACK and STOP interrupts */ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; 800326c: 68fb ldr r3, [r7, #12] 800326e: 22b8 movs r2, #184 @ 0xb8 8003270: 4313 orrs r3, r2 8003272: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_ERROR_IT) 8003274: 1cbb adds r3, r7, #2 8003276: 881b ldrh r3, [r3, #0] 8003278: 2b10 cmp r3, #16 800327a: d103 bne.n 8003284 { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; 800327c: 68fb ldr r3, [r7, #12] 800327e: 2290 movs r2, #144 @ 0x90 8003280: 4313 orrs r3, r2 8003282: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_CPLT_IT) 8003284: 1cbb adds r3, r7, #2 8003286: 881b ldrh r3, [r3, #0] 8003288: 2b20 cmp r3, #32 800328a: d103 bne.n 8003294 { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; 800328c: 68fb ldr r3, [r7, #12] 800328e: 2220 movs r2, #32 8003290: 4313 orrs r3, r2 8003292: 60fb str r3, [r7, #12] } if (InterruptRequest == I2C_XFER_RELOAD_IT) 8003294: 1cbb adds r3, r7, #2 8003296: 881b ldrh r3, [r3, #0] 8003298: 2b40 cmp r3, #64 @ 0x40 800329a: d103 bne.n 80032a4 { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; 800329c: 68fb ldr r3, [r7, #12] 800329e: 2240 movs r2, #64 @ 0x40 80032a0: 4313 orrs r3, r2 80032a2: 60fb str r3, [r7, #12] } /* Disable interrupts only at the end */ /* to avoid a breaking situation like at "t" time */ /* all disable interrupts request are not done */ __HAL_I2C_DISABLE_IT(hi2c, tmpisr); 80032a4: 687b ldr r3, [r7, #4] 80032a6: 681b ldr r3, [r3, #0] 80032a8: 681a ldr r2, [r3, #0] 80032aa: 68fb ldr r3, [r7, #12] 80032ac: 43d9 mvns r1, r3 80032ae: 687b ldr r3, [r7, #4] 80032b0: 681b ldr r3, [r3, #0] 80032b2: 400a ands r2, r1 80032b4: 601a str r2, [r3, #0] } 80032b6: 46c0 nop @ (mov r8, r8) 80032b8: 46bd mov sp, r7 80032ba: b004 add sp, #16 80032bc: bd80 pop {r7, pc} ... 080032c0 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter New state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 80032c0: b580 push {r7, lr} 80032c2: b082 sub sp, #8 80032c4: af00 add r7, sp, #0 80032c6: 6078 str r0, [r7, #4] 80032c8: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 80032ca: 687b ldr r3, [r7, #4] 80032cc: 2241 movs r2, #65 @ 0x41 80032ce: 5c9b ldrb r3, [r3, r2] 80032d0: b2db uxtb r3, r3 80032d2: 2b20 cmp r3, #32 80032d4: d138 bne.n 8003348 { /* Process Locked */ __HAL_LOCK(hi2c); 80032d6: 687b ldr r3, [r7, #4] 80032d8: 2240 movs r2, #64 @ 0x40 80032da: 5c9b ldrb r3, [r3, r2] 80032dc: 2b01 cmp r3, #1 80032de: d101 bne.n 80032e4 80032e0: 2302 movs r3, #2 80032e2: e032 b.n 800334a 80032e4: 687b ldr r3, [r7, #4] 80032e6: 2240 movs r2, #64 @ 0x40 80032e8: 2101 movs r1, #1 80032ea: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 80032ec: 687b ldr r3, [r7, #4] 80032ee: 2241 movs r2, #65 @ 0x41 80032f0: 2124 movs r1, #36 @ 0x24 80032f2: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 80032f4: 687b ldr r3, [r7, #4] 80032f6: 681b ldr r3, [r3, #0] 80032f8: 681a ldr r2, [r3, #0] 80032fa: 687b ldr r3, [r7, #4] 80032fc: 681b ldr r3, [r3, #0] 80032fe: 2101 movs r1, #1 8003300: 438a bics r2, r1 8003302: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 8003304: 687b ldr r3, [r7, #4] 8003306: 681b ldr r3, [r3, #0] 8003308: 681a ldr r2, [r3, #0] 800330a: 687b ldr r3, [r7, #4] 800330c: 681b ldr r3, [r3, #0] 800330e: 4911 ldr r1, [pc, #68] @ (8003354 ) 8003310: 400a ands r2, r1 8003312: 601a str r2, [r3, #0] /* Set analog filter bit*/ hi2c->Instance->CR1 |= AnalogFilter; 8003314: 687b ldr r3, [r7, #4] 8003316: 681b ldr r3, [r3, #0] 8003318: 6819 ldr r1, [r3, #0] 800331a: 687b ldr r3, [r7, #4] 800331c: 681b ldr r3, [r3, #0] 800331e: 683a ldr r2, [r7, #0] 8003320: 430a orrs r2, r1 8003322: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 8003324: 687b ldr r3, [r7, #4] 8003326: 681b ldr r3, [r3, #0] 8003328: 681a ldr r2, [r3, #0] 800332a: 687b ldr r3, [r7, #4] 800332c: 681b ldr r3, [r3, #0] 800332e: 2101 movs r1, #1 8003330: 430a orrs r2, r1 8003332: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003334: 687b ldr r3, [r7, #4] 8003336: 2241 movs r2, #65 @ 0x41 8003338: 2120 movs r1, #32 800333a: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 800333c: 687b ldr r3, [r7, #4] 800333e: 2240 movs r2, #64 @ 0x40 8003340: 2100 movs r1, #0 8003342: 5499 strb r1, [r3, r2] return HAL_OK; 8003344: 2300 movs r3, #0 8003346: e000 b.n 800334a } else { return HAL_BUSY; 8003348: 2302 movs r3, #2 } } 800334a: 0018 movs r0, r3 800334c: 46bd mov sp, r7 800334e: b002 add sp, #8 8003350: bd80 pop {r7, pc} 8003352: 46c0 nop @ (mov r8, r8) 8003354: ffffefff .word 0xffffefff 08003358 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8003358: b580 push {r7, lr} 800335a: b084 sub sp, #16 800335c: af00 add r7, sp, #0 800335e: 6078 str r0, [r7, #4] 8003360: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8003362: 687b ldr r3, [r7, #4] 8003364: 2241 movs r2, #65 @ 0x41 8003366: 5c9b ldrb r3, [r3, r2] 8003368: b2db uxtb r3, r3 800336a: 2b20 cmp r3, #32 800336c: d139 bne.n 80033e2 { /* Process Locked */ __HAL_LOCK(hi2c); 800336e: 687b ldr r3, [r7, #4] 8003370: 2240 movs r2, #64 @ 0x40 8003372: 5c9b ldrb r3, [r3, r2] 8003374: 2b01 cmp r3, #1 8003376: d101 bne.n 800337c 8003378: 2302 movs r3, #2 800337a: e033 b.n 80033e4 800337c: 687b ldr r3, [r7, #4] 800337e: 2240 movs r2, #64 @ 0x40 8003380: 2101 movs r1, #1 8003382: 5499 strb r1, [r3, r2] hi2c->State = HAL_I2C_STATE_BUSY; 8003384: 687b ldr r3, [r7, #4] 8003386: 2241 movs r2, #65 @ 0x41 8003388: 2124 movs r1, #36 @ 0x24 800338a: 5499 strb r1, [r3, r2] /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 800338c: 687b ldr r3, [r7, #4] 800338e: 681b ldr r3, [r3, #0] 8003390: 681a ldr r2, [r3, #0] 8003392: 687b ldr r3, [r7, #4] 8003394: 681b ldr r3, [r3, #0] 8003396: 2101 movs r1, #1 8003398: 438a bics r2, r1 800339a: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->CR1; 800339c: 687b ldr r3, [r7, #4] 800339e: 681b ldr r3, [r3, #0] 80033a0: 681b ldr r3, [r3, #0] 80033a2: 60fb str r3, [r7, #12] /* Reset I2Cx DNF bits [11:8] */ tmpreg &= ~(I2C_CR1_DNF); 80033a4: 68fb ldr r3, [r7, #12] 80033a6: 4a11 ldr r2, [pc, #68] @ (80033ec ) 80033a8: 4013 ands r3, r2 80033aa: 60fb str r3, [r7, #12] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter << 8U; 80033ac: 683b ldr r3, [r7, #0] 80033ae: 021b lsls r3, r3, #8 80033b0: 68fa ldr r2, [r7, #12] 80033b2: 4313 orrs r3, r2 80033b4: 60fb str r3, [r7, #12] /* Store the new register value */ hi2c->Instance->CR1 = tmpreg; 80033b6: 687b ldr r3, [r7, #4] 80033b8: 681b ldr r3, [r3, #0] 80033ba: 68fa ldr r2, [r7, #12] 80033bc: 601a str r2, [r3, #0] __HAL_I2C_ENABLE(hi2c); 80033be: 687b ldr r3, [r7, #4] 80033c0: 681b ldr r3, [r3, #0] 80033c2: 681a ldr r2, [r3, #0] 80033c4: 687b ldr r3, [r7, #4] 80033c6: 681b ldr r3, [r3, #0] 80033c8: 2101 movs r1, #1 80033ca: 430a orrs r2, r1 80033cc: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 80033ce: 687b ldr r3, [r7, #4] 80033d0: 2241 movs r2, #65 @ 0x41 80033d2: 2120 movs r1, #32 80033d4: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hi2c); 80033d6: 687b ldr r3, [r7, #4] 80033d8: 2240 movs r2, #64 @ 0x40 80033da: 2100 movs r1, #0 80033dc: 5499 strb r1, [r3, r2] return HAL_OK; 80033de: 2300 movs r3, #0 80033e0: e000 b.n 80033e4 } else { return HAL_BUSY; 80033e2: 2302 movs r3, #2 } } 80033e4: 0018 movs r0, r3 80033e6: 46bd mov sp, r7 80033e8: b004 add sp, #16 80033ea: bd80 pop {r7, pc} 80033ec: fffff0ff .word 0xfffff0ff 080033f0 : * cleared before returning the status. If the flag is not cleared within * 6 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 80033f0: b580 push {r7, lr} 80033f2: b084 sub sp, #16 80033f4: af00 add r7, sp, #0 80033f6: 6078 str r0, [r7, #4] uint32_t wait_loop_index; assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* Modify voltage scaling range */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 80033f8: 4b19 ldr r3, [pc, #100] @ (8003460 ) 80033fa: 681b ldr r3, [r3, #0] 80033fc: 4a19 ldr r2, [pc, #100] @ (8003464 ) 80033fe: 4013 ands r3, r2 8003400: 0019 movs r1, r3 8003402: 4b17 ldr r3, [pc, #92] @ (8003460 ) 8003404: 687a ldr r2, [r7, #4] 8003406: 430a orrs r2, r1 8003408: 601a str r2, [r3, #0] /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 800340a: 687a ldr r2, [r7, #4] 800340c: 2380 movs r3, #128 @ 0x80 800340e: 009b lsls r3, r3, #2 8003410: 429a cmp r2, r3 8003412: d11f bne.n 8003454 { /* Set timeout value */ wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; 8003414: 4b14 ldr r3, [pc, #80] @ (8003468 ) 8003416: 681a ldr r2, [r3, #0] 8003418: 0013 movs r3, r2 800341a: 005b lsls r3, r3, #1 800341c: 189b adds r3, r3, r2 800341e: 005b lsls r3, r3, #1 8003420: 4912 ldr r1, [pc, #72] @ (800346c ) 8003422: 0018 movs r0, r3 8003424: f7fc fe6c bl 8000100 <__udivsi3> 8003428: 0003 movs r3, r0 800342a: 3301 adds r3, #1 800342c: 60fb str r3, [r7, #12] /* Wait until VOSF is reset */ while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 800342e: e008 b.n 8003442 { if (wait_loop_index != 0U) 8003430: 68fb ldr r3, [r7, #12] 8003432: 2b00 cmp r3, #0 8003434: d003 beq.n 800343e { wait_loop_index--; 8003436: 68fb ldr r3, [r7, #12] 8003438: 3b01 subs r3, #1 800343a: 60fb str r3, [r7, #12] 800343c: e001 b.n 8003442 } else { return HAL_TIMEOUT; 800343e: 2303 movs r3, #3 8003440: e009 b.n 8003456 while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 8003442: 4b07 ldr r3, [pc, #28] @ (8003460 ) 8003444: 695a ldr r2, [r3, #20] 8003446: 2380 movs r3, #128 @ 0x80 8003448: 00db lsls r3, r3, #3 800344a: 401a ands r2, r3 800344c: 2380 movs r3, #128 @ 0x80 800344e: 00db lsls r3, r3, #3 8003450: 429a cmp r2, r3 8003452: d0ed beq.n 8003430 } } } return HAL_OK; 8003454: 2300 movs r3, #0 } 8003456: 0018 movs r0, r3 8003458: 46bd mov sp, r7 800345a: b004 add sp, #16 800345c: bd80 pop {r7, pc} 800345e: 46c0 nop @ (mov r8, r8) 8003460: 40007000 .word 0x40007000 8003464: fffff9ff .word 0xfffff9ff 8003468: 20000004 .word 0x20000004 800346c: 000f4240 .word 0x000f4240 08003470 : * @arg @ref LL_RCC_APB1_DIV_4 * @arg @ref LL_RCC_APB1_DIV_8 * @arg @ref LL_RCC_APB1_DIV_16 */ __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) { 8003470: b580 push {r7, lr} 8003472: af00 add r7, sp, #0 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); 8003474: 4b03 ldr r3, [pc, #12] @ (8003484 ) 8003476: 689a ldr r2, [r3, #8] 8003478: 23e0 movs r3, #224 @ 0xe0 800347a: 01db lsls r3, r3, #7 800347c: 4013 ands r3, r2 } 800347e: 0018 movs r0, r3 8003480: 46bd mov sp, r7 8003482: bd80 pop {r7, pc} 8003484: 40021000 .word 0x40021000 08003488 : * supported by this function. User should request a transition to LSE Off * first and then to LSE On or LSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 8003488: b580 push {r7, lr} 800348a: b088 sub sp, #32 800348c: af00 add r7, sp, #0 800348e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; uint32_t temp_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8003490: 687b ldr r3, [r7, #4] 8003492: 2b00 cmp r3, #0 8003494: d101 bne.n 800349a { return HAL_ERROR; 8003496: 2301 movs r3, #1 8003498: e2f3 b.n 8003a82 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800349a: 687b ldr r3, [r7, #4] 800349c: 681b ldr r3, [r3, #0] 800349e: 2201 movs r2, #1 80034a0: 4013 ands r3, r2 80034a2: d100 bne.n 80034a6 80034a4: e07c b.n 80035a0 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80034a6: 4bc3 ldr r3, [pc, #780] @ (80037b4 ) 80034a8: 689b ldr r3, [r3, #8] 80034aa: 2238 movs r2, #56 @ 0x38 80034ac: 4013 ands r3, r2 80034ae: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80034b0: 4bc0 ldr r3, [pc, #768] @ (80037b4 ) 80034b2: 68db ldr r3, [r3, #12] 80034b4: 2203 movs r2, #3 80034b6: 4013 ands r3, r2 80034b8: 617b str r3, [r7, #20] /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) 80034ba: 69bb ldr r3, [r7, #24] 80034bc: 2b10 cmp r3, #16 80034be: d102 bne.n 80034c6 80034c0: 697b ldr r3, [r7, #20] 80034c2: 2b03 cmp r3, #3 80034c4: d002 beq.n 80034cc || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) 80034c6: 69bb ldr r3, [r7, #24] 80034c8: 2b08 cmp r3, #8 80034ca: d10b bne.n 80034e4 { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80034cc: 4bb9 ldr r3, [pc, #740] @ (80037b4 ) 80034ce: 681a ldr r2, [r3, #0] 80034d0: 2380 movs r3, #128 @ 0x80 80034d2: 029b lsls r3, r3, #10 80034d4: 4013 ands r3, r2 80034d6: d062 beq.n 800359e 80034d8: 687b ldr r3, [r7, #4] 80034da: 685b ldr r3, [r3, #4] 80034dc: 2b00 cmp r3, #0 80034de: d15e bne.n 800359e { return HAL_ERROR; 80034e0: 2301 movs r3, #1 80034e2: e2ce b.n 8003a82 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80034e4: 687b ldr r3, [r7, #4] 80034e6: 685a ldr r2, [r3, #4] 80034e8: 2380 movs r3, #128 @ 0x80 80034ea: 025b lsls r3, r3, #9 80034ec: 429a cmp r2, r3 80034ee: d107 bne.n 8003500 80034f0: 4bb0 ldr r3, [pc, #704] @ (80037b4 ) 80034f2: 681a ldr r2, [r3, #0] 80034f4: 4baf ldr r3, [pc, #700] @ (80037b4 ) 80034f6: 2180 movs r1, #128 @ 0x80 80034f8: 0249 lsls r1, r1, #9 80034fa: 430a orrs r2, r1 80034fc: 601a str r2, [r3, #0] 80034fe: e020 b.n 8003542 8003500: 687b ldr r3, [r7, #4] 8003502: 685a ldr r2, [r3, #4] 8003504: 23a0 movs r3, #160 @ 0xa0 8003506: 02db lsls r3, r3, #11 8003508: 429a cmp r2, r3 800350a: d10e bne.n 800352a 800350c: 4ba9 ldr r3, [pc, #676] @ (80037b4 ) 800350e: 681a ldr r2, [r3, #0] 8003510: 4ba8 ldr r3, [pc, #672] @ (80037b4 ) 8003512: 2180 movs r1, #128 @ 0x80 8003514: 02c9 lsls r1, r1, #11 8003516: 430a orrs r2, r1 8003518: 601a str r2, [r3, #0] 800351a: 4ba6 ldr r3, [pc, #664] @ (80037b4 ) 800351c: 681a ldr r2, [r3, #0] 800351e: 4ba5 ldr r3, [pc, #660] @ (80037b4 ) 8003520: 2180 movs r1, #128 @ 0x80 8003522: 0249 lsls r1, r1, #9 8003524: 430a orrs r2, r1 8003526: 601a str r2, [r3, #0] 8003528: e00b b.n 8003542 800352a: 4ba2 ldr r3, [pc, #648] @ (80037b4 ) 800352c: 681a ldr r2, [r3, #0] 800352e: 4ba1 ldr r3, [pc, #644] @ (80037b4 ) 8003530: 49a1 ldr r1, [pc, #644] @ (80037b8 ) 8003532: 400a ands r2, r1 8003534: 601a str r2, [r3, #0] 8003536: 4b9f ldr r3, [pc, #636] @ (80037b4 ) 8003538: 681a ldr r2, [r3, #0] 800353a: 4b9e ldr r3, [pc, #632] @ (80037b4 ) 800353c: 499f ldr r1, [pc, #636] @ (80037bc ) 800353e: 400a ands r2, r1 8003540: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8003542: 687b ldr r3, [r7, #4] 8003544: 685b ldr r3, [r3, #4] 8003546: 2b00 cmp r3, #0 8003548: d014 beq.n 8003574 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800354a: f7fd fe1d bl 8001188 800354e: 0003 movs r3, r0 8003550: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003552: e008 b.n 8003566 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8003554: f7fd fe18 bl 8001188 8003558: 0002 movs r2, r0 800355a: 693b ldr r3, [r7, #16] 800355c: 1ad3 subs r3, r2, r3 800355e: 2b64 cmp r3, #100 @ 0x64 8003560: d901 bls.n 8003566 { return HAL_TIMEOUT; 8003562: 2303 movs r3, #3 8003564: e28d b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003566: 4b93 ldr r3, [pc, #588] @ (80037b4 ) 8003568: 681a ldr r2, [r3, #0] 800356a: 2380 movs r3, #128 @ 0x80 800356c: 029b lsls r3, r3, #10 800356e: 4013 ands r3, r2 8003570: d0f0 beq.n 8003554 8003572: e015 b.n 80035a0 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003574: f7fd fe08 bl 8001188 8003578: 0003 movs r3, r0 800357a: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 800357c: e008 b.n 8003590 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800357e: f7fd fe03 bl 8001188 8003582: 0002 movs r2, r0 8003584: 693b ldr r3, [r7, #16] 8003586: 1ad3 subs r3, r2, r3 8003588: 2b64 cmp r3, #100 @ 0x64 800358a: d901 bls.n 8003590 { return HAL_TIMEOUT; 800358c: 2303 movs r3, #3 800358e: e278 b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8003590: 4b88 ldr r3, [pc, #544] @ (80037b4 ) 8003592: 681a ldr r2, [r3, #0] 8003594: 2380 movs r3, #128 @ 0x80 8003596: 029b lsls r3, r3, #10 8003598: 4013 ands r3, r2 800359a: d1f0 bne.n 800357e 800359c: e000 b.n 80035a0 if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800359e: 46c0 nop @ (mov r8, r8) } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 80035a0: 687b ldr r3, [r7, #4] 80035a2: 681b ldr r3, [r3, #0] 80035a4: 2202 movs r2, #2 80035a6: 4013 ands r3, r2 80035a8: d100 bne.n 80035ac 80035aa: e099 b.n 80036e0 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80035ac: 4b81 ldr r3, [pc, #516] @ (80037b4 ) 80035ae: 689b ldr r3, [r3, #8] 80035b0: 2238 movs r2, #56 @ 0x38 80035b2: 4013 ands r3, r2 80035b4: 61bb str r3, [r7, #24] temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); 80035b6: 4b7f ldr r3, [pc, #508] @ (80037b4 ) 80035b8: 68db ldr r3, [r3, #12] 80035ba: 2203 movs r2, #3 80035bc: 4013 ands r3, r2 80035be: 617b str r3, [r7, #20] if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) 80035c0: 69bb ldr r3, [r7, #24] 80035c2: 2b10 cmp r3, #16 80035c4: d102 bne.n 80035cc 80035c6: 697b ldr r3, [r7, #20] 80035c8: 2b02 cmp r3, #2 80035ca: d002 beq.n 80035d2 || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) 80035cc: 69bb ldr r3, [r7, #24] 80035ce: 2b00 cmp r3, #0 80035d0: d135 bne.n 800363e { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80035d2: 4b78 ldr r3, [pc, #480] @ (80037b4 ) 80035d4: 681a ldr r2, [r3, #0] 80035d6: 2380 movs r3, #128 @ 0x80 80035d8: 00db lsls r3, r3, #3 80035da: 4013 ands r3, r2 80035dc: d005 beq.n 80035ea 80035de: 687b ldr r3, [r7, #4] 80035e0: 68db ldr r3, [r3, #12] 80035e2: 2b00 cmp r3, #0 80035e4: d101 bne.n 80035ea { return HAL_ERROR; 80035e6: 2301 movs r3, #1 80035e8: e24b b.n 8003a82 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80035ea: 4b72 ldr r3, [pc, #456] @ (80037b4 ) 80035ec: 685b ldr r3, [r3, #4] 80035ee: 4a74 ldr r2, [pc, #464] @ (80037c0 ) 80035f0: 4013 ands r3, r2 80035f2: 0019 movs r1, r3 80035f4: 687b ldr r3, [r7, #4] 80035f6: 695b ldr r3, [r3, #20] 80035f8: 021a lsls r2, r3, #8 80035fa: 4b6e ldr r3, [pc, #440] @ (80037b4 ) 80035fc: 430a orrs r2, r1 80035fe: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) 8003600: 69bb ldr r3, [r7, #24] 8003602: 2b00 cmp r3, #0 8003604: d112 bne.n 800362c { /* Adjust the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003606: 4b6b ldr r3, [pc, #428] @ (80037b4 ) 8003608: 681b ldr r3, [r3, #0] 800360a: 4a6e ldr r2, [pc, #440] @ (80037c4 ) 800360c: 4013 ands r3, r2 800360e: 0019 movs r1, r3 8003610: 687b ldr r3, [r7, #4] 8003612: 691a ldr r2, [r3, #16] 8003614: 4b67 ldr r3, [pc, #412] @ (80037b4 ) 8003616: 430a orrs r2, r1 8003618: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 800361a: 4b66 ldr r3, [pc, #408] @ (80037b4 ) 800361c: 681b ldr r3, [r3, #0] 800361e: 0adb lsrs r3, r3, #11 8003620: 2207 movs r2, #7 8003622: 4013 ands r3, r2 8003624: 4a68 ldr r2, [pc, #416] @ (80037c8 ) 8003626: 40da lsrs r2, r3 8003628: 4b68 ldr r3, [pc, #416] @ (80037cc ) 800362a: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 800362c: 4b68 ldr r3, [pc, #416] @ (80037d0 ) 800362e: 681b ldr r3, [r3, #0] 8003630: 0018 movs r0, r3 8003632: f7fd fd4d bl 80010d0 8003636: 1e03 subs r3, r0, #0 8003638: d051 beq.n 80036de { return HAL_ERROR; 800363a: 2301 movs r3, #1 800363c: e221 b.n 8003a82 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 800363e: 687b ldr r3, [r7, #4] 8003640: 68db ldr r3, [r3, #12] 8003642: 2b00 cmp r3, #0 8003644: d030 beq.n 80036a8 { /* Configure the HSI16 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8003646: 4b5b ldr r3, [pc, #364] @ (80037b4 ) 8003648: 681b ldr r3, [r3, #0] 800364a: 4a5e ldr r2, [pc, #376] @ (80037c4 ) 800364c: 4013 ands r3, r2 800364e: 0019 movs r1, r3 8003650: 687b ldr r3, [r7, #4] 8003652: 691a ldr r2, [r3, #16] 8003654: 4b57 ldr r3, [pc, #348] @ (80037b4 ) 8003656: 430a orrs r2, r1 8003658: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_ENABLE(); 800365a: 4b56 ldr r3, [pc, #344] @ (80037b4 ) 800365c: 681a ldr r2, [r3, #0] 800365e: 4b55 ldr r3, [pc, #340] @ (80037b4 ) 8003660: 2180 movs r1, #128 @ 0x80 8003662: 0049 lsls r1, r1, #1 8003664: 430a orrs r2, r1 8003666: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003668: f7fd fd8e bl 8001188 800366c: 0003 movs r3, r0 800366e: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003670: e008 b.n 8003684 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8003672: f7fd fd89 bl 8001188 8003676: 0002 movs r2, r0 8003678: 693b ldr r3, [r7, #16] 800367a: 1ad3 subs r3, r2, r3 800367c: 2b02 cmp r3, #2 800367e: d901 bls.n 8003684 { return HAL_TIMEOUT; 8003680: 2303 movs r3, #3 8003682: e1fe b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003684: 4b4b ldr r3, [pc, #300] @ (80037b4 ) 8003686: 681a ldr r2, [r3, #0] 8003688: 2380 movs r3, #128 @ 0x80 800368a: 00db lsls r3, r3, #3 800368c: 4013 ands r3, r2 800368e: d0f0 beq.n 8003672 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8003690: 4b48 ldr r3, [pc, #288] @ (80037b4 ) 8003692: 685b ldr r3, [r3, #4] 8003694: 4a4a ldr r2, [pc, #296] @ (80037c0 ) 8003696: 4013 ands r3, r2 8003698: 0019 movs r1, r3 800369a: 687b ldr r3, [r7, #4] 800369c: 695b ldr r3, [r3, #20] 800369e: 021a lsls r2, r3, #8 80036a0: 4b44 ldr r3, [pc, #272] @ (80037b4 ) 80036a2: 430a orrs r2, r1 80036a4: 605a str r2, [r3, #4] 80036a6: e01b b.n 80036e0 } else { /* Disable the Internal High Speed oscillator (HSI16). */ __HAL_RCC_HSI_DISABLE(); 80036a8: 4b42 ldr r3, [pc, #264] @ (80037b4 ) 80036aa: 681a ldr r2, [r3, #0] 80036ac: 4b41 ldr r3, [pc, #260] @ (80037b4 ) 80036ae: 4949 ldr r1, [pc, #292] @ (80037d4 ) 80036b0: 400a ands r2, r1 80036b2: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80036b4: f7fd fd68 bl 8001188 80036b8: 0003 movs r3, r0 80036ba: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80036bc: e008 b.n 80036d0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80036be: f7fd fd63 bl 8001188 80036c2: 0002 movs r2, r0 80036c4: 693b ldr r3, [r7, #16] 80036c6: 1ad3 subs r3, r2, r3 80036c8: 2b02 cmp r3, #2 80036ca: d901 bls.n 80036d0 { return HAL_TIMEOUT; 80036cc: 2303 movs r3, #3 80036ce: e1d8 b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 80036d0: 4b38 ldr r3, [pc, #224] @ (80037b4 ) 80036d2: 681a ldr r2, [r3, #0] 80036d4: 2380 movs r3, #128 @ 0x80 80036d6: 00db lsls r3, r3, #3 80036d8: 4013 ands r3, r2 80036da: d1f0 bne.n 80036be 80036dc: e000 b.n 80036e0 if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80036de: 46c0 nop @ (mov r8, r8) } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80036e0: 687b ldr r3, [r7, #4] 80036e2: 681b ldr r3, [r3, #0] 80036e4: 2208 movs r2, #8 80036e6: 4013 ands r3, r2 80036e8: d047 beq.n 800377a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 80036ea: 4b32 ldr r3, [pc, #200] @ (80037b4 ) 80036ec: 689b ldr r3, [r3, #8] 80036ee: 2238 movs r2, #56 @ 0x38 80036f0: 4013 ands r3, r2 80036f2: 2b18 cmp r3, #24 80036f4: d10a bne.n 800370c { /* When LSI is used as system clock it will not be disabled */ if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) 80036f6: 4b2f ldr r3, [pc, #188] @ (80037b4 ) 80036f8: 6e1b ldr r3, [r3, #96] @ 0x60 80036fa: 2202 movs r2, #2 80036fc: 4013 ands r3, r2 80036fe: d03c beq.n 800377a 8003700: 687b ldr r3, [r7, #4] 8003702: 699b ldr r3, [r3, #24] 8003704: 2b00 cmp r3, #0 8003706: d138 bne.n 800377a { return HAL_ERROR; 8003708: 2301 movs r3, #1 800370a: e1ba b.n 8003a82 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 800370c: 687b ldr r3, [r7, #4] 800370e: 699b ldr r3, [r3, #24] 8003710: 2b00 cmp r3, #0 8003712: d019 beq.n 8003748 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8003714: 4b27 ldr r3, [pc, #156] @ (80037b4 ) 8003716: 6e1a ldr r2, [r3, #96] @ 0x60 8003718: 4b26 ldr r3, [pc, #152] @ (80037b4 ) 800371a: 2101 movs r1, #1 800371c: 430a orrs r2, r1 800371e: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003720: f7fd fd32 bl 8001188 8003724: 0003 movs r3, r0 8003726: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003728: e008 b.n 800373c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800372a: f7fd fd2d bl 8001188 800372e: 0002 movs r2, r0 8003730: 693b ldr r3, [r7, #16] 8003732: 1ad3 subs r3, r2, r3 8003734: 2b02 cmp r3, #2 8003736: d901 bls.n 800373c { return HAL_TIMEOUT; 8003738: 2303 movs r3, #3 800373a: e1a2 b.n 8003a82 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 800373c: 4b1d ldr r3, [pc, #116] @ (80037b4 ) 800373e: 6e1b ldr r3, [r3, #96] @ 0x60 8003740: 2202 movs r2, #2 8003742: 4013 ands r3, r2 8003744: d0f1 beq.n 800372a 8003746: e018 b.n 800377a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8003748: 4b1a ldr r3, [pc, #104] @ (80037b4 ) 800374a: 6e1a ldr r2, [r3, #96] @ 0x60 800374c: 4b19 ldr r3, [pc, #100] @ (80037b4 ) 800374e: 2101 movs r1, #1 8003750: 438a bics r2, r1 8003752: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003754: f7fd fd18 bl 8001188 8003758: 0003 movs r3, r0 800375a: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 800375c: e008 b.n 8003770 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800375e: f7fd fd13 bl 8001188 8003762: 0002 movs r2, r0 8003764: 693b ldr r3, [r7, #16] 8003766: 1ad3 subs r3, r2, r3 8003768: 2b02 cmp r3, #2 800376a: d901 bls.n 8003770 { return HAL_TIMEOUT; 800376c: 2303 movs r3, #3 800376e: e188 b.n 8003a82 while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) 8003770: 4b10 ldr r3, [pc, #64] @ (80037b4 ) 8003772: 6e1b ldr r3, [r3, #96] @ 0x60 8003774: 2202 movs r2, #2 8003776: 4013 ands r3, r2 8003778: d1f1 bne.n 800375e } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800377a: 687b ldr r3, [r7, #4] 800377c: 681b ldr r3, [r3, #0] 800377e: 2204 movs r2, #4 8003780: 4013 ands r3, r2 8003782: d100 bne.n 8003786 8003784: e0c6 b.n 8003914 { FlagStatus pwrclkchanged = RESET; 8003786: 231f movs r3, #31 8003788: 18fb adds r3, r7, r3 800378a: 2200 movs r2, #0 800378c: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 800378e: 4b09 ldr r3, [pc, #36] @ (80037b4 ) 8003790: 689b ldr r3, [r3, #8] 8003792: 2238 movs r2, #56 @ 0x38 8003794: 4013 ands r3, r2 8003796: 2b20 cmp r3, #32 8003798: d11e bne.n 80037d8 { if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) 800379a: 4b06 ldr r3, [pc, #24] @ (80037b4 ) 800379c: 6ddb ldr r3, [r3, #92] @ 0x5c 800379e: 2202 movs r2, #2 80037a0: 4013 ands r3, r2 80037a2: d100 bne.n 80037a6 80037a4: e0b6 b.n 8003914 80037a6: 687b ldr r3, [r7, #4] 80037a8: 689b ldr r3, [r3, #8] 80037aa: 2b00 cmp r3, #0 80037ac: d000 beq.n 80037b0 80037ae: e0b1 b.n 8003914 { return HAL_ERROR; 80037b0: 2301 movs r3, #1 80037b2: e166 b.n 8003a82 80037b4: 40021000 .word 0x40021000 80037b8: fffeffff .word 0xfffeffff 80037bc: fffbffff .word 0xfffbffff 80037c0: ffff80ff .word 0xffff80ff 80037c4: ffffc7ff .word 0xffffc7ff 80037c8: 00f42400 .word 0x00f42400 80037cc: 20000004 .word 0x20000004 80037d0: 20000008 .word 0x20000008 80037d4: fffffeff .word 0xfffffeff } else { /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) 80037d8: 4bac ldr r3, [pc, #688] @ (8003a8c ) 80037da: 6bda ldr r2, [r3, #60] @ 0x3c 80037dc: 2380 movs r3, #128 @ 0x80 80037de: 055b lsls r3, r3, #21 80037e0: 4013 ands r3, r2 80037e2: d101 bne.n 80037e8 80037e4: 2301 movs r3, #1 80037e6: e000 b.n 80037ea 80037e8: 2300 movs r3, #0 80037ea: 2b00 cmp r3, #0 80037ec: d011 beq.n 8003812 { __HAL_RCC_PWR_CLK_ENABLE(); 80037ee: 4ba7 ldr r3, [pc, #668] @ (8003a8c ) 80037f0: 6bda ldr r2, [r3, #60] @ 0x3c 80037f2: 4ba6 ldr r3, [pc, #664] @ (8003a8c ) 80037f4: 2180 movs r1, #128 @ 0x80 80037f6: 0549 lsls r1, r1, #21 80037f8: 430a orrs r2, r1 80037fa: 63da str r2, [r3, #60] @ 0x3c 80037fc: 4ba3 ldr r3, [pc, #652] @ (8003a8c ) 80037fe: 6bda ldr r2, [r3, #60] @ 0x3c 8003800: 2380 movs r3, #128 @ 0x80 8003802: 055b lsls r3, r3, #21 8003804: 4013 ands r3, r2 8003806: 60fb str r3, [r7, #12] 8003808: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 800380a: 231f movs r3, #31 800380c: 18fb adds r3, r7, r3 800380e: 2201 movs r2, #1 8003810: 701a strb r2, [r3, #0] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003812: 4b9f ldr r3, [pc, #636] @ (8003a90 ) 8003814: 681a ldr r2, [r3, #0] 8003816: 2380 movs r3, #128 @ 0x80 8003818: 005b lsls r3, r3, #1 800381a: 4013 ands r3, r2 800381c: d11a bne.n 8003854 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800381e: 4b9c ldr r3, [pc, #624] @ (8003a90 ) 8003820: 681a ldr r2, [r3, #0] 8003822: 4b9b ldr r3, [pc, #620] @ (8003a90 ) 8003824: 2180 movs r1, #128 @ 0x80 8003826: 0049 lsls r1, r1, #1 8003828: 430a orrs r2, r1 800382a: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800382c: f7fd fcac bl 8001188 8003830: 0003 movs r3, r0 8003832: 613b str r3, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003834: e008 b.n 8003848 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003836: f7fd fca7 bl 8001188 800383a: 0002 movs r2, r0 800383c: 693b ldr r3, [r7, #16] 800383e: 1ad3 subs r3, r2, r3 8003840: 2b02 cmp r3, #2 8003842: d901 bls.n 8003848 { return HAL_TIMEOUT; 8003844: 2303 movs r3, #3 8003846: e11c b.n 8003a82 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8003848: 4b91 ldr r3, [pc, #580] @ (8003a90 ) 800384a: 681a ldr r2, [r3, #0] 800384c: 2380 movs r3, #128 @ 0x80 800384e: 005b lsls r3, r3, #1 8003850: 4013 ands r3, r2 8003852: d0f0 beq.n 8003836 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8003854: 687b ldr r3, [r7, #4] 8003856: 689b ldr r3, [r3, #8] 8003858: 2b01 cmp r3, #1 800385a: d106 bne.n 800386a 800385c: 4b8b ldr r3, [pc, #556] @ (8003a8c ) 800385e: 6dda ldr r2, [r3, #92] @ 0x5c 8003860: 4b8a ldr r3, [pc, #552] @ (8003a8c ) 8003862: 2101 movs r1, #1 8003864: 430a orrs r2, r1 8003866: 65da str r2, [r3, #92] @ 0x5c 8003868: e01c b.n 80038a4 800386a: 687b ldr r3, [r7, #4] 800386c: 689b ldr r3, [r3, #8] 800386e: 2b05 cmp r3, #5 8003870: d10c bne.n 800388c 8003872: 4b86 ldr r3, [pc, #536] @ (8003a8c ) 8003874: 6dda ldr r2, [r3, #92] @ 0x5c 8003876: 4b85 ldr r3, [pc, #532] @ (8003a8c ) 8003878: 2104 movs r1, #4 800387a: 430a orrs r2, r1 800387c: 65da str r2, [r3, #92] @ 0x5c 800387e: 4b83 ldr r3, [pc, #524] @ (8003a8c ) 8003880: 6dda ldr r2, [r3, #92] @ 0x5c 8003882: 4b82 ldr r3, [pc, #520] @ (8003a8c ) 8003884: 2101 movs r1, #1 8003886: 430a orrs r2, r1 8003888: 65da str r2, [r3, #92] @ 0x5c 800388a: e00b b.n 80038a4 800388c: 4b7f ldr r3, [pc, #508] @ (8003a8c ) 800388e: 6dda ldr r2, [r3, #92] @ 0x5c 8003890: 4b7e ldr r3, [pc, #504] @ (8003a8c ) 8003892: 2101 movs r1, #1 8003894: 438a bics r2, r1 8003896: 65da str r2, [r3, #92] @ 0x5c 8003898: 4b7c ldr r3, [pc, #496] @ (8003a8c ) 800389a: 6dda ldr r2, [r3, #92] @ 0x5c 800389c: 4b7b ldr r3, [pc, #492] @ (8003a8c ) 800389e: 2104 movs r1, #4 80038a0: 438a bics r2, r1 80038a2: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 80038a4: 687b ldr r3, [r7, #4] 80038a6: 689b ldr r3, [r3, #8] 80038a8: 2b00 cmp r3, #0 80038aa: d014 beq.n 80038d6 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80038ac: f7fd fc6c bl 8001188 80038b0: 0003 movs r3, r0 80038b2: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80038b4: e009 b.n 80038ca { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80038b6: f7fd fc67 bl 8001188 80038ba: 0002 movs r2, r0 80038bc: 693b ldr r3, [r7, #16] 80038be: 1ad3 subs r3, r2, r3 80038c0: 4a74 ldr r2, [pc, #464] @ (8003a94 ) 80038c2: 4293 cmp r3, r2 80038c4: d901 bls.n 80038ca { return HAL_TIMEOUT; 80038c6: 2303 movs r3, #3 80038c8: e0db b.n 8003a82 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 80038ca: 4b70 ldr r3, [pc, #448] @ (8003a8c ) 80038cc: 6ddb ldr r3, [r3, #92] @ 0x5c 80038ce: 2202 movs r2, #2 80038d0: 4013 ands r3, r2 80038d2: d0f0 beq.n 80038b6 80038d4: e013 b.n 80038fe } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80038d6: f7fd fc57 bl 8001188 80038da: 0003 movs r3, r0 80038dc: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80038de: e009 b.n 80038f4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80038e0: f7fd fc52 bl 8001188 80038e4: 0002 movs r2, r0 80038e6: 693b ldr r3, [r7, #16] 80038e8: 1ad3 subs r3, r2, r3 80038ea: 4a6a ldr r2, [pc, #424] @ (8003a94 ) 80038ec: 4293 cmp r3, r2 80038ee: d901 bls.n 80038f4 { return HAL_TIMEOUT; 80038f0: 2303 movs r3, #3 80038f2: e0c6 b.n 8003a82 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) 80038f4: 4b65 ldr r3, [pc, #404] @ (8003a8c ) 80038f6: 6ddb ldr r3, [r3, #92] @ 0x5c 80038f8: 2202 movs r2, #2 80038fa: 4013 ands r3, r2 80038fc: d1f0 bne.n 80038e0 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80038fe: 231f movs r3, #31 8003900: 18fb adds r3, r7, r3 8003902: 781b ldrb r3, [r3, #0] 8003904: 2b01 cmp r3, #1 8003906: d105 bne.n 8003914 { __HAL_RCC_PWR_CLK_DISABLE(); 8003908: 4b60 ldr r3, [pc, #384] @ (8003a8c ) 800390a: 6bda ldr r2, [r3, #60] @ 0x3c 800390c: 4b5f ldr r3, [pc, #380] @ (8003a8c ) 800390e: 4962 ldr r1, [pc, #392] @ (8003a98 ) 8003910: 400a ands r2, r1 8003912: 63da str r2, [r3, #60] @ 0x3c #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8003914: 687b ldr r3, [r7, #4] 8003916: 69db ldr r3, [r3, #28] 8003918: 2b00 cmp r3, #0 800391a: d100 bne.n 800391e 800391c: e0b0 b.n 8003a80 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) 800391e: 4b5b ldr r3, [pc, #364] @ (8003a8c ) 8003920: 689b ldr r3, [r3, #8] 8003922: 2238 movs r2, #56 @ 0x38 8003924: 4013 ands r3, r2 8003926: 2b10 cmp r3, #16 8003928: d100 bne.n 800392c 800392a: e078 b.n 8003a1e { if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 800392c: 687b ldr r3, [r7, #4] 800392e: 69db ldr r3, [r3, #28] 8003930: 2b02 cmp r3, #2 8003932: d153 bne.n 80039dc assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); #endif /* RCC_PLLQ_SUPPORT */ assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8003934: 4b55 ldr r3, [pc, #340] @ (8003a8c ) 8003936: 681a ldr r2, [r3, #0] 8003938: 4b54 ldr r3, [pc, #336] @ (8003a8c ) 800393a: 4958 ldr r1, [pc, #352] @ (8003a9c ) 800393c: 400a ands r2, r1 800393e: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003940: f7fd fc22 bl 8001188 8003944: 0003 movs r3, r0 8003946: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003948: e008 b.n 800395c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800394a: f7fd fc1d bl 8001188 800394e: 0002 movs r2, r0 8003950: 693b ldr r3, [r7, #16] 8003952: 1ad3 subs r3, r2, r3 8003954: 2b02 cmp r3, #2 8003956: d901 bls.n 800395c { return HAL_TIMEOUT; 8003958: 2303 movs r3, #3 800395a: e092 b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 800395c: 4b4b ldr r3, [pc, #300] @ (8003a8c ) 800395e: 681a ldr r2, [r3, #0] 8003960: 2380 movs r3, #128 @ 0x80 8003962: 049b lsls r3, r3, #18 8003964: 4013 ands r3, r2 8003966: d1f0 bne.n 800394a RCC_OscInitStruct->PLL.PLLN, RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); #else /* !RCC_PLLQ_SUPPORT */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8003968: 4b48 ldr r3, [pc, #288] @ (8003a8c ) 800396a: 68db ldr r3, [r3, #12] 800396c: 4a4c ldr r2, [pc, #304] @ (8003aa0 ) 800396e: 4013 ands r3, r2 8003970: 0019 movs r1, r3 8003972: 687b ldr r3, [r7, #4] 8003974: 6a1a ldr r2, [r3, #32] 8003976: 687b ldr r3, [r7, #4] 8003978: 6a5b ldr r3, [r3, #36] @ 0x24 800397a: 431a orrs r2, r3 800397c: 687b ldr r3, [r7, #4] 800397e: 6a9b ldr r3, [r3, #40] @ 0x28 8003980: 021b lsls r3, r3, #8 8003982: 431a orrs r2, r3 8003984: 687b ldr r3, [r7, #4] 8003986: 6adb ldr r3, [r3, #44] @ 0x2c 8003988: 431a orrs r2, r3 800398a: 687b ldr r3, [r7, #4] 800398c: 6b1b ldr r3, [r3, #48] @ 0x30 800398e: 431a orrs r2, r3 8003990: 4b3e ldr r3, [pc, #248] @ (8003a8c ) 8003992: 430a orrs r2, r1 8003994: 60da str r2, [r3, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLR); #endif /* RCC_PLLQ_SUPPORT */ /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8003996: 4b3d ldr r3, [pc, #244] @ (8003a8c ) 8003998: 681a ldr r2, [r3, #0] 800399a: 4b3c ldr r3, [pc, #240] @ (8003a8c ) 800399c: 2180 movs r1, #128 @ 0x80 800399e: 0449 lsls r1, r1, #17 80039a0: 430a orrs r2, r1 80039a2: 601a str r2, [r3, #0] /* Enable PLLR Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); 80039a4: 4b39 ldr r3, [pc, #228] @ (8003a8c ) 80039a6: 68da ldr r2, [r3, #12] 80039a8: 4b38 ldr r3, [pc, #224] @ (8003a8c ) 80039aa: 2180 movs r1, #128 @ 0x80 80039ac: 0549 lsls r1, r1, #21 80039ae: 430a orrs r2, r1 80039b0: 60da str r2, [r3, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039b2: f7fd fbe9 bl 8001188 80039b6: 0003 movs r3, r0 80039b8: 613b str r3, [r7, #16] /* Wait till PLL is ready */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80039ba: e008 b.n 80039ce { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80039bc: f7fd fbe4 bl 8001188 80039c0: 0002 movs r2, r0 80039c2: 693b ldr r3, [r7, #16] 80039c4: 1ad3 subs r3, r2, r3 80039c6: 2b02 cmp r3, #2 80039c8: d901 bls.n 80039ce { return HAL_TIMEOUT; 80039ca: 2303 movs r3, #3 80039cc: e059 b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 80039ce: 4b2f ldr r3, [pc, #188] @ (8003a8c ) 80039d0: 681a ldr r2, [r3, #0] 80039d2: 2380 movs r3, #128 @ 0x80 80039d4: 049b lsls r3, r3, #18 80039d6: 4013 ands r3, r2 80039d8: d0f0 beq.n 80039bc 80039da: e051 b.n 8003a80 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80039dc: 4b2b ldr r3, [pc, #172] @ (8003a8c ) 80039de: 681a ldr r2, [r3, #0] 80039e0: 4b2a ldr r3, [pc, #168] @ (8003a8c ) 80039e2: 492e ldr r1, [pc, #184] @ (8003a9c ) 80039e4: 400a ands r2, r1 80039e6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80039e8: f7fd fbce bl 8001188 80039ec: 0003 movs r3, r0 80039ee: 613b str r3, [r7, #16] /* Wait till PLL is disabled */ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 80039f0: e008 b.n 8003a04 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80039f2: f7fd fbc9 bl 8001188 80039f6: 0002 movs r2, r0 80039f8: 693b ldr r3, [r7, #16] 80039fa: 1ad3 subs r3, r2, r3 80039fc: 2b02 cmp r3, #2 80039fe: d901 bls.n 8003a04 { return HAL_TIMEOUT; 8003a00: 2303 movs r3, #3 8003a02: e03e b.n 8003a82 while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) 8003a04: 4b21 ldr r3, [pc, #132] @ (8003a8c ) 8003a06: 681a ldr r2, [r3, #0] 8003a08: 2380 movs r3, #128 @ 0x80 8003a0a: 049b lsls r3, r3, #18 8003a0c: 4013 ands r3, r2 8003a0e: d1f0 bne.n 80039f2 } /* Unselect main PLL clock source and disable main PLL outputs to save power */ #if defined(RCC_PLLQ_SUPPORT) RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); #else RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); 8003a10: 4b1e ldr r3, [pc, #120] @ (8003a8c ) 8003a12: 68da ldr r2, [r3, #12] 8003a14: 4b1d ldr r3, [pc, #116] @ (8003a8c ) 8003a16: 4923 ldr r1, [pc, #140] @ (8003aa4 ) 8003a18: 400a ands r2, r1 8003a1a: 60da str r2, [r3, #12] 8003a1c: e030 b.n 8003a80 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8003a1e: 687b ldr r3, [r7, #4] 8003a20: 69db ldr r3, [r3, #28] 8003a22: 2b01 cmp r3, #1 8003a24: d101 bne.n 8003a2a { return HAL_ERROR; 8003a26: 2301 movs r3, #1 8003a28: e02b b.n 8003a82 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp_pllckcfg = RCC->PLLCFGR; 8003a2a: 4b18 ldr r3, [pc, #96] @ (8003a8c ) 8003a2c: 68db ldr r3, [r3, #12] 8003a2e: 617b str r3, [r7, #20] if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a30: 697b ldr r3, [r7, #20] 8003a32: 2203 movs r2, #3 8003a34: 401a ands r2, r3 8003a36: 687b ldr r3, [r7, #4] 8003a38: 6a1b ldr r3, [r3, #32] 8003a3a: 429a cmp r2, r3 8003a3c: d11e bne.n 8003a7c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003a3e: 697b ldr r3, [r7, #20] 8003a40: 2270 movs r2, #112 @ 0x70 8003a42: 401a ands r2, r3 8003a44: 687b ldr r3, [r7, #4] 8003a46: 6a5b ldr r3, [r3, #36] @ 0x24 if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8003a48: 429a cmp r2, r3 8003a4a: d117 bne.n 8003a7c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003a4c: 697a ldr r2, [r7, #20] 8003a4e: 23fe movs r3, #254 @ 0xfe 8003a50: 01db lsls r3, r3, #7 8003a52: 401a ands r2, r3 8003a54: 687b ldr r3, [r7, #4] 8003a56: 6a9b ldr r3, [r3, #40] @ 0x28 8003a58: 021b lsls r3, r3, #8 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || 8003a5a: 429a cmp r2, r3 8003a5c: d10e bne.n 8003a7c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003a5e: 697a ldr r2, [r7, #20] 8003a60: 23f8 movs r3, #248 @ 0xf8 8003a62: 039b lsls r3, r3, #14 8003a64: 401a ands r2, r3 8003a66: 687b ldr r3, [r7, #4] 8003a68: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || 8003a6a: 429a cmp r2, r3 8003a6c: d106 bne.n 8003a7c #if defined (RCC_PLLQ_SUPPORT) (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || #endif /* RCC_PLLQ_SUPPORT */ (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) 8003a6e: 697b ldr r3, [r7, #20] 8003a70: 0f5b lsrs r3, r3, #29 8003a72: 075a lsls r2, r3, #29 8003a74: 687b ldr r3, [r7, #4] 8003a76: 6b1b ldr r3, [r3, #48] @ 0x30 (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || 8003a78: 429a cmp r2, r3 8003a7a: d001 beq.n 8003a80 { return HAL_ERROR; 8003a7c: 2301 movs r3, #1 8003a7e: e000 b.n 8003a82 } } } } return HAL_OK; 8003a80: 2300 movs r3, #0 } 8003a82: 0018 movs r0, r3 8003a84: 46bd mov sp, r7 8003a86: b008 add sp, #32 8003a88: bd80 pop {r7, pc} 8003a8a: 46c0 nop @ (mov r8, r8) 8003a8c: 40021000 .word 0x40021000 8003a90: 40007000 .word 0x40007000 8003a94: 00001388 .word 0x00001388 8003a98: efffffff .word 0xefffffff 8003a9c: feffffff .word 0xfeffffff 8003aa0: 1fc1808c .word 0x1fc1808c 8003aa4: effefffc .word 0xeffefffc 08003aa8 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8003aa8: b580 push {r7, lr} 8003aaa: b084 sub sp, #16 8003aac: af00 add r7, sp, #0 8003aae: 6078 str r0, [r7, #4] 8003ab0: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8003ab2: 687b ldr r3, [r7, #4] 8003ab4: 2b00 cmp r3, #0 8003ab6: d101 bne.n 8003abc { return HAL_ERROR; 8003ab8: 2301 movs r3, #1 8003aba: e0e9 b.n 8003c90 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8003abc: 4b76 ldr r3, [pc, #472] @ (8003c98 ) 8003abe: 681b ldr r3, [r3, #0] 8003ac0: 2207 movs r2, #7 8003ac2: 4013 ands r3, r2 8003ac4: 683a ldr r2, [r7, #0] 8003ac6: 429a cmp r2, r3 8003ac8: d91e bls.n 8003b08 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003aca: 4b73 ldr r3, [pc, #460] @ (8003c98 ) 8003acc: 681b ldr r3, [r3, #0] 8003ace: 2207 movs r2, #7 8003ad0: 4393 bics r3, r2 8003ad2: 0019 movs r1, r3 8003ad4: 4b70 ldr r3, [pc, #448] @ (8003c98 ) 8003ad6: 683a ldr r2, [r7, #0] 8003ad8: 430a orrs r2, r1 8003ada: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8003adc: f7fd fb54 bl 8001188 8003ae0: 0003 movs r3, r0 8003ae2: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003ae4: e009 b.n 8003afa { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003ae6: f7fd fb4f bl 8001188 8003aea: 0002 movs r2, r0 8003aec: 68fb ldr r3, [r7, #12] 8003aee: 1ad3 subs r3, r2, r3 8003af0: 4a6a ldr r2, [pc, #424] @ (8003c9c ) 8003af2: 4293 cmp r3, r2 8003af4: d901 bls.n 8003afa { return HAL_TIMEOUT; 8003af6: 2303 movs r3, #3 8003af8: e0ca b.n 8003c90 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003afa: 4b67 ldr r3, [pc, #412] @ (8003c98 ) 8003afc: 681b ldr r3, [r3, #0] 8003afe: 2207 movs r2, #7 8003b00: 4013 ands r3, r2 8003b02: 683a ldr r2, [r7, #0] 8003b04: 429a cmp r2, r3 8003b06: d1ee bne.n 8003ae6 } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8003b08: 687b ldr r3, [r7, #4] 8003b0a: 681b ldr r3, [r3, #0] 8003b0c: 2202 movs r2, #2 8003b0e: 4013 ands r3, r2 8003b10: d015 beq.n 8003b3e { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003b12: 687b ldr r3, [r7, #4] 8003b14: 681b ldr r3, [r3, #0] 8003b16: 2204 movs r2, #4 8003b18: 4013 ands r3, r2 8003b1a: d006 beq.n 8003b2a { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8003b1c: 4b60 ldr r3, [pc, #384] @ (8003ca0 ) 8003b1e: 689a ldr r2, [r3, #8] 8003b20: 4b5f ldr r3, [pc, #380] @ (8003ca0 ) 8003b22: 21e0 movs r1, #224 @ 0xe0 8003b24: 01c9 lsls r1, r1, #7 8003b26: 430a orrs r2, r1 8003b28: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8003b2a: 4b5d ldr r3, [pc, #372] @ (8003ca0 ) 8003b2c: 689b ldr r3, [r3, #8] 8003b2e: 4a5d ldr r2, [pc, #372] @ (8003ca4 ) 8003b30: 4013 ands r3, r2 8003b32: 0019 movs r1, r3 8003b34: 687b ldr r3, [r7, #4] 8003b36: 689a ldr r2, [r3, #8] 8003b38: 4b59 ldr r3, [pc, #356] @ (8003ca0 ) 8003b3a: 430a orrs r2, r1 8003b3c: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8003b3e: 687b ldr r3, [r7, #4] 8003b40: 681b ldr r3, [r3, #0] 8003b42: 2201 movs r2, #1 8003b44: 4013 ands r3, r2 8003b46: d057 beq.n 8003bf8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8003b48: 687b ldr r3, [r7, #4] 8003b4a: 685b ldr r3, [r3, #4] 8003b4c: 2b01 cmp r3, #1 8003b4e: d107 bne.n 8003b60 { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8003b50: 4b53 ldr r3, [pc, #332] @ (8003ca0 ) 8003b52: 681a ldr r2, [r3, #0] 8003b54: 2380 movs r3, #128 @ 0x80 8003b56: 029b lsls r3, r3, #10 8003b58: 4013 ands r3, r2 8003b5a: d12b bne.n 8003bb4 { return HAL_ERROR; 8003b5c: 2301 movs r3, #1 8003b5e: e097 b.n 8003c90 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8003b60: 687b ldr r3, [r7, #4] 8003b62: 685b ldr r3, [r3, #4] 8003b64: 2b02 cmp r3, #2 8003b66: d107 bne.n 8003b78 { /* Check the PLL ready flag */ if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) 8003b68: 4b4d ldr r3, [pc, #308] @ (8003ca0 ) 8003b6a: 681a ldr r2, [r3, #0] 8003b6c: 2380 movs r3, #128 @ 0x80 8003b6e: 049b lsls r3, r3, #18 8003b70: 4013 ands r3, r2 8003b72: d11f bne.n 8003bb4 { return HAL_ERROR; 8003b74: 2301 movs r3, #1 8003b76: e08b b.n 8003c90 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 8003b78: 687b ldr r3, [r7, #4] 8003b7a: 685b ldr r3, [r3, #4] 8003b7c: 2b00 cmp r3, #0 8003b7e: d107 bne.n 8003b90 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8003b80: 4b47 ldr r3, [pc, #284] @ (8003ca0 ) 8003b82: 681a ldr r2, [r3, #0] 8003b84: 2380 movs r3, #128 @ 0x80 8003b86: 00db lsls r3, r3, #3 8003b88: 4013 ands r3, r2 8003b8a: d113 bne.n 8003bb4 { return HAL_ERROR; 8003b8c: 2301 movs r3, #1 8003b8e: e07f b.n 8003c90 } } /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8003b90: 687b ldr r3, [r7, #4] 8003b92: 685b ldr r3, [r3, #4] 8003b94: 2b03 cmp r3, #3 8003b96: d106 bne.n 8003ba6 { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) 8003b98: 4b41 ldr r3, [pc, #260] @ (8003ca0 ) 8003b9a: 6e1b ldr r3, [r3, #96] @ 0x60 8003b9c: 2202 movs r2, #2 8003b9e: 4013 ands r3, r2 8003ba0: d108 bne.n 8003bb4 { return HAL_ERROR; 8003ba2: 2301 movs r3, #1 8003ba4: e074 b.n 8003c90 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003ba6: 4b3e ldr r3, [pc, #248] @ (8003ca0 ) 8003ba8: 6ddb ldr r3, [r3, #92] @ 0x5c 8003baa: 2202 movs r2, #2 8003bac: 4013 ands r3, r2 8003bae: d101 bne.n 8003bb4 { return HAL_ERROR; 8003bb0: 2301 movs r3, #1 8003bb2: e06d b.n 8003c90 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8003bb4: 4b3a ldr r3, [pc, #232] @ (8003ca0 ) 8003bb6: 689b ldr r3, [r3, #8] 8003bb8: 2207 movs r2, #7 8003bba: 4393 bics r3, r2 8003bbc: 0019 movs r1, r3 8003bbe: 687b ldr r3, [r7, #4] 8003bc0: 685a ldr r2, [r3, #4] 8003bc2: 4b37 ldr r3, [pc, #220] @ (8003ca0 ) 8003bc4: 430a orrs r2, r1 8003bc6: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003bc8: f7fd fade bl 8001188 8003bcc: 0003 movs r3, r0 8003bce: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003bd0: e009 b.n 8003be6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003bd2: f7fd fad9 bl 8001188 8003bd6: 0002 movs r2, r0 8003bd8: 68fb ldr r3, [r7, #12] 8003bda: 1ad3 subs r3, r2, r3 8003bdc: 4a2f ldr r2, [pc, #188] @ (8003c9c ) 8003bde: 4293 cmp r3, r2 8003be0: d901 bls.n 8003be6 { return HAL_TIMEOUT; 8003be2: 2303 movs r3, #3 8003be4: e054 b.n 8003c90 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8003be6: 4b2e ldr r3, [pc, #184] @ (8003ca0 ) 8003be8: 689b ldr r3, [r3, #8] 8003bea: 2238 movs r2, #56 @ 0x38 8003bec: 401a ands r2, r3 8003bee: 687b ldr r3, [r7, #4] 8003bf0: 685b ldr r3, [r3, #4] 8003bf2: 00db lsls r3, r3, #3 8003bf4: 429a cmp r2, r3 8003bf6: d1ec bne.n 8003bd2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8003bf8: 4b27 ldr r3, [pc, #156] @ (8003c98 ) 8003bfa: 681b ldr r3, [r3, #0] 8003bfc: 2207 movs r2, #7 8003bfe: 4013 ands r3, r2 8003c00: 683a ldr r2, [r7, #0] 8003c02: 429a cmp r2, r3 8003c04: d21e bcs.n 8003c44 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8003c06: 4b24 ldr r3, [pc, #144] @ (8003c98 ) 8003c08: 681b ldr r3, [r3, #0] 8003c0a: 2207 movs r2, #7 8003c0c: 4393 bics r3, r2 8003c0e: 0019 movs r1, r3 8003c10: 4b21 ldr r3, [pc, #132] @ (8003c98 ) 8003c12: 683a ldr r2, [r7, #0] 8003c14: 430a orrs r2, r1 8003c16: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8003c18: f7fd fab6 bl 8001188 8003c1c: 0003 movs r3, r0 8003c1e: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003c20: e009 b.n 8003c36 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8003c22: f7fd fab1 bl 8001188 8003c26: 0002 movs r2, r0 8003c28: 68fb ldr r3, [r7, #12] 8003c2a: 1ad3 subs r3, r2, r3 8003c2c: 4a1b ldr r2, [pc, #108] @ (8003c9c ) 8003c2e: 4293 cmp r3, r2 8003c30: d901 bls.n 8003c36 { return HAL_TIMEOUT; 8003c32: 2303 movs r3, #3 8003c34: e02c b.n 8003c90 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8003c36: 4b18 ldr r3, [pc, #96] @ (8003c98 ) 8003c38: 681b ldr r3, [r3, #0] 8003c3a: 2207 movs r2, #7 8003c3c: 4013 ands r3, r2 8003c3e: 683a ldr r2, [r7, #0] 8003c40: 429a cmp r2, r3 8003c42: d1ee bne.n 8003c22 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8003c44: 687b ldr r3, [r7, #4] 8003c46: 681b ldr r3, [r3, #0] 8003c48: 2204 movs r2, #4 8003c4a: 4013 ands r3, r2 8003c4c: d009 beq.n 8003c62 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8003c4e: 4b14 ldr r3, [pc, #80] @ (8003ca0 ) 8003c50: 689b ldr r3, [r3, #8] 8003c52: 4a15 ldr r2, [pc, #84] @ (8003ca8 ) 8003c54: 4013 ands r3, r2 8003c56: 0019 movs r1, r3 8003c58: 687b ldr r3, [r7, #4] 8003c5a: 68da ldr r2, [r3, #12] 8003c5c: 4b10 ldr r3, [pc, #64] @ (8003ca0 ) 8003c5e: 430a orrs r2, r1 8003c60: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8003c62: f000 f829 bl 8003cb8 8003c66: 0001 movs r1, r0 8003c68: 4b0d ldr r3, [pc, #52] @ (8003ca0 ) 8003c6a: 689b ldr r3, [r3, #8] 8003c6c: 0a1b lsrs r3, r3, #8 8003c6e: 220f movs r2, #15 8003c70: 401a ands r2, r3 8003c72: 4b0e ldr r3, [pc, #56] @ (8003cac ) 8003c74: 0092 lsls r2, r2, #2 8003c76: 58d3 ldr r3, [r2, r3] 8003c78: 221f movs r2, #31 8003c7a: 4013 ands r3, r2 8003c7c: 000a movs r2, r1 8003c7e: 40da lsrs r2, r3 8003c80: 4b0b ldr r3, [pc, #44] @ (8003cb0 ) 8003c82: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8003c84: 4b0b ldr r3, [pc, #44] @ (8003cb4 ) 8003c86: 681b ldr r3, [r3, #0] 8003c88: 0018 movs r0, r3 8003c8a: f7fd fa21 bl 80010d0 8003c8e: 0003 movs r3, r0 } 8003c90: 0018 movs r0, r3 8003c92: 46bd mov sp, r7 8003c94: b004 add sp, #16 8003c96: bd80 pop {r7, pc} 8003c98: 40022000 .word 0x40022000 8003c9c: 00001388 .word 0x00001388 8003ca0: 40021000 .word 0x40021000 8003ca4: fffff0ff .word 0xfffff0ff 8003ca8: ffff8fff .word 0xffff8fff 8003cac: 08004b88 .word 0x08004b88 8003cb0: 20000004 .word 0x20000004 8003cb4: 20000008 .word 0x20000008 08003cb8 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8003cb8: b580 push {r7, lr} 8003cba: b086 sub sp, #24 8003cbc: af00 add r7, sp, #0 uint32_t pllvco, pllsource, pllr, pllm, hsidiv; uint32_t sysclockfreq; if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 8003cbe: 4b3c ldr r3, [pc, #240] @ (8003db0 ) 8003cc0: 689b ldr r3, [r3, #8] 8003cc2: 2238 movs r2, #56 @ 0x38 8003cc4: 4013 ands r3, r2 8003cc6: d10f bne.n 8003ce8 { /* HSISYS can be derived for HSI16 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 8003cc8: 4b39 ldr r3, [pc, #228] @ (8003db0 ) 8003cca: 681b ldr r3, [r3, #0] 8003ccc: 0adb lsrs r3, r3, #11 8003cce: 2207 movs r2, #7 8003cd0: 4013 ands r3, r2 8003cd2: 2201 movs r2, #1 8003cd4: 409a lsls r2, r3 8003cd6: 0013 movs r3, r2 8003cd8: 603b str r3, [r7, #0] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 8003cda: 6839 ldr r1, [r7, #0] 8003cdc: 4835 ldr r0, [pc, #212] @ (8003db4 ) 8003cde: f7fc fa0f bl 8000100 <__udivsi3> 8003ce2: 0003 movs r3, r0 8003ce4: 613b str r3, [r7, #16] 8003ce6: e05d b.n 8003da4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 8003ce8: 4b31 ldr r3, [pc, #196] @ (8003db0 ) 8003cea: 689b ldr r3, [r3, #8] 8003cec: 2238 movs r2, #56 @ 0x38 8003cee: 4013 ands r3, r2 8003cf0: 2b08 cmp r3, #8 8003cf2: d102 bne.n 8003cfa { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8003cf4: 4b30 ldr r3, [pc, #192] @ (8003db8 ) 8003cf6: 613b str r3, [r7, #16] 8003cf8: e054 b.n 8003da4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) 8003cfa: 4b2d ldr r3, [pc, #180] @ (8003db0 ) 8003cfc: 689b ldr r3, [r3, #8] 8003cfe: 2238 movs r2, #56 @ 0x38 8003d00: 4013 ands r3, r2 8003d02: 2b10 cmp r3, #16 8003d04: d138 bne.n 8003d78 /* PLL used as system clock source */ /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 8003d06: 4b2a ldr r3, [pc, #168] @ (8003db0 ) 8003d08: 68db ldr r3, [r3, #12] 8003d0a: 2203 movs r2, #3 8003d0c: 4013 ands r3, r2 8003d0e: 60fb str r3, [r7, #12] pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; 8003d10: 4b27 ldr r3, [pc, #156] @ (8003db0 ) 8003d12: 68db ldr r3, [r3, #12] 8003d14: 091b lsrs r3, r3, #4 8003d16: 2207 movs r2, #7 8003d18: 4013 ands r3, r2 8003d1a: 3301 adds r3, #1 8003d1c: 60bb str r3, [r7, #8] switch (pllsource) 8003d1e: 68fb ldr r3, [r7, #12] 8003d20: 2b03 cmp r3, #3 8003d22: d10d bne.n 8003d40 { case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 8003d24: 68b9 ldr r1, [r7, #8] 8003d26: 4824 ldr r0, [pc, #144] @ (8003db8 ) 8003d28: f7fc f9ea bl 8000100 <__udivsi3> 8003d2c: 0003 movs r3, r0 8003d2e: 0019 movs r1, r3 8003d30: 4b1f ldr r3, [pc, #124] @ (8003db0 ) 8003d32: 68db ldr r3, [r3, #12] 8003d34: 0a1b lsrs r3, r3, #8 8003d36: 227f movs r2, #127 @ 0x7f 8003d38: 4013 ands r3, r2 8003d3a: 434b muls r3, r1 8003d3c: 617b str r3, [r7, #20] break; 8003d3e: e00d b.n 8003d5c case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ default: /* HSI16 used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; 8003d40: 68b9 ldr r1, [r7, #8] 8003d42: 481c ldr r0, [pc, #112] @ (8003db4 ) 8003d44: f7fc f9dc bl 8000100 <__udivsi3> 8003d48: 0003 movs r3, r0 8003d4a: 0019 movs r1, r3 8003d4c: 4b18 ldr r3, [pc, #96] @ (8003db0 ) 8003d4e: 68db ldr r3, [r3, #12] 8003d50: 0a1b lsrs r3, r3, #8 8003d52: 227f movs r2, #127 @ 0x7f 8003d54: 4013 ands r3, r2 8003d56: 434b muls r3, r1 8003d58: 617b str r3, [r7, #20] break; 8003d5a: 46c0 nop @ (mov r8, r8) } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); 8003d5c: 4b14 ldr r3, [pc, #80] @ (8003db0 ) 8003d5e: 68db ldr r3, [r3, #12] 8003d60: 0f5b lsrs r3, r3, #29 8003d62: 2207 movs r2, #7 8003d64: 4013 ands r3, r2 8003d66: 3301 adds r3, #1 8003d68: 607b str r3, [r7, #4] sysclockfreq = pllvco / pllr; 8003d6a: 6879 ldr r1, [r7, #4] 8003d6c: 6978 ldr r0, [r7, #20] 8003d6e: f7fc f9c7 bl 8000100 <__udivsi3> 8003d72: 0003 movs r3, r0 8003d74: 613b str r3, [r7, #16] 8003d76: e015 b.n 8003da4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) 8003d78: 4b0d ldr r3, [pc, #52] @ (8003db0 ) 8003d7a: 689b ldr r3, [r3, #8] 8003d7c: 2238 movs r2, #56 @ 0x38 8003d7e: 4013 ands r3, r2 8003d80: 2b20 cmp r3, #32 8003d82: d103 bne.n 8003d8c { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 8003d84: 2380 movs r3, #128 @ 0x80 8003d86: 021b lsls r3, r3, #8 8003d88: 613b str r3, [r7, #16] 8003d8a: e00b b.n 8003da4 } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) 8003d8c: 4b08 ldr r3, [pc, #32] @ (8003db0 ) 8003d8e: 689b ldr r3, [r3, #8] 8003d90: 2238 movs r2, #56 @ 0x38 8003d92: 4013 ands r3, r2 8003d94: 2b18 cmp r3, #24 8003d96: d103 bne.n 8003da0 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 8003d98: 23fa movs r3, #250 @ 0xfa 8003d9a: 01db lsls r3, r3, #7 8003d9c: 613b str r3, [r7, #16] 8003d9e: e001 b.n 8003da4 } else { sysclockfreq = 0U; 8003da0: 2300 movs r3, #0 8003da2: 613b str r3, [r7, #16] } return sysclockfreq; 8003da4: 693b ldr r3, [r7, #16] } 8003da6: 0018 movs r0, r3 8003da8: 46bd mov sp, r7 8003daa: b006 add sp, #24 8003dac: bd80 pop {r7, pc} 8003dae: 46c0 nop @ (mov r8, r8) 8003db0: 40021000 .word 0x40021000 8003db4: 00f42400 .word 0x00f42400 8003db8: 007a1200 .word 0x007a1200 08003dbc : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8003dbc: b580 push {r7, lr} 8003dbe: af00 add r7, sp, #0 return SystemCoreClock; 8003dc0: 4b02 ldr r3, [pc, #8] @ (8003dcc ) 8003dc2: 681b ldr r3, [r3, #0] } 8003dc4: 0018 movs r0, r3 8003dc6: 46bd mov sp, r7 8003dc8: bd80 pop {r7, pc} 8003dca: 46c0 nop @ (mov r8, r8) 8003dcc: 20000004 .word 0x20000004 08003dd0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8003dd0: b5b0 push {r4, r5, r7, lr} 8003dd2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); 8003dd4: f7ff fff2 bl 8003dbc 8003dd8: 0004 movs r4, r0 8003dda: f7ff fb49 bl 8003470 8003dde: 0003 movs r3, r0 8003de0: 0b1a lsrs r2, r3, #12 8003de2: 4b05 ldr r3, [pc, #20] @ (8003df8 ) 8003de4: 0092 lsls r2, r2, #2 8003de6: 58d3 ldr r3, [r2, r3] 8003de8: 221f movs r2, #31 8003dea: 4013 ands r3, r2 8003dec: 40dc lsrs r4, r3 8003dee: 0023 movs r3, r4 } 8003df0: 0018 movs r0, r3 8003df2: 46bd mov sp, r7 8003df4: bdb0 pop {r4, r5, r7, pc} 8003df6: 46c0 nop @ (mov r8, r8) 8003df8: 08004bc8 .word 0x08004bc8 08003dfc : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8003dfc: b580 push {r7, lr} 8003dfe: b086 sub sp, #24 8003e00: af00 add r7, sp, #0 8003e02: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8003e04: 2313 movs r3, #19 8003e06: 18fb adds r3, r7, r3 8003e08: 2200 movs r2, #0 8003e0a: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 8003e0c: 2312 movs r3, #18 8003e0e: 18fb adds r3, r7, r3 8003e10: 2200 movs r2, #0 8003e12: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8003e14: 687b ldr r3, [r7, #4] 8003e16: 681a ldr r2, [r3, #0] 8003e18: 2380 movs r3, #128 @ 0x80 8003e1a: 029b lsls r3, r3, #10 8003e1c: 4013 ands r3, r2 8003e1e: d100 bne.n 8003e22 8003e20: e0a3 b.n 8003f6a { FlagStatus pwrclkchanged = RESET; 8003e22: 2011 movs r0, #17 8003e24: 183b adds r3, r7, r0 8003e26: 2200 movs r2, #0 8003e28: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 8003e2a: 4b86 ldr r3, [pc, #536] @ (8004044 ) 8003e2c: 6bda ldr r2, [r3, #60] @ 0x3c 8003e2e: 2380 movs r3, #128 @ 0x80 8003e30: 055b lsls r3, r3, #21 8003e32: 4013 ands r3, r2 8003e34: d110 bne.n 8003e58 { __HAL_RCC_PWR_CLK_ENABLE(); 8003e36: 4b83 ldr r3, [pc, #524] @ (8004044 ) 8003e38: 6bda ldr r2, [r3, #60] @ 0x3c 8003e3a: 4b82 ldr r3, [pc, #520] @ (8004044 ) 8003e3c: 2180 movs r1, #128 @ 0x80 8003e3e: 0549 lsls r1, r1, #21 8003e40: 430a orrs r2, r1 8003e42: 63da str r2, [r3, #60] @ 0x3c 8003e44: 4b7f ldr r3, [pc, #508] @ (8004044 ) 8003e46: 6bda ldr r2, [r3, #60] @ 0x3c 8003e48: 2380 movs r3, #128 @ 0x80 8003e4a: 055b lsls r3, r3, #21 8003e4c: 4013 ands r3, r2 8003e4e: 60bb str r3, [r7, #8] 8003e50: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8003e52: 183b adds r3, r7, r0 8003e54: 2201 movs r2, #1 8003e56: 701a strb r2, [r3, #0] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8003e58: 4b7b ldr r3, [pc, #492] @ (8004048 ) 8003e5a: 681a ldr r2, [r3, #0] 8003e5c: 4b7a ldr r3, [pc, #488] @ (8004048 ) 8003e5e: 2180 movs r1, #128 @ 0x80 8003e60: 0049 lsls r1, r1, #1 8003e62: 430a orrs r2, r1 8003e64: 601a str r2, [r3, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8003e66: f7fd f98f bl 8001188 8003e6a: 0003 movs r3, r0 8003e6c: 60fb str r3, [r7, #12] while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003e6e: e00b b.n 8003e88 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8003e70: f7fd f98a bl 8001188 8003e74: 0002 movs r2, r0 8003e76: 68fb ldr r3, [r7, #12] 8003e78: 1ad3 subs r3, r2, r3 8003e7a: 2b02 cmp r3, #2 8003e7c: d904 bls.n 8003e88 { ret = HAL_TIMEOUT; 8003e7e: 2313 movs r3, #19 8003e80: 18fb adds r3, r7, r3 8003e82: 2203 movs r2, #3 8003e84: 701a strb r2, [r3, #0] break; 8003e86: e005 b.n 8003e94 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8003e88: 4b6f ldr r3, [pc, #444] @ (8004048 ) 8003e8a: 681a ldr r2, [r3, #0] 8003e8c: 2380 movs r3, #128 @ 0x80 8003e8e: 005b lsls r3, r3, #1 8003e90: 4013 ands r3, r2 8003e92: d0ed beq.n 8003e70 } } if (ret == HAL_OK) 8003e94: 2313 movs r3, #19 8003e96: 18fb adds r3, r7, r3 8003e98: 781b ldrb r3, [r3, #0] 8003e9a: 2b00 cmp r3, #0 8003e9c: d154 bne.n 8003f48 { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8003e9e: 4b69 ldr r3, [pc, #420] @ (8004044 ) 8003ea0: 6dda ldr r2, [r3, #92] @ 0x5c 8003ea2: 23c0 movs r3, #192 @ 0xc0 8003ea4: 009b lsls r3, r3, #2 8003ea6: 4013 ands r3, r2 8003ea8: 617b str r3, [r7, #20] /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 8003eaa: 697b ldr r3, [r7, #20] 8003eac: 2b00 cmp r3, #0 8003eae: d019 beq.n 8003ee4 8003eb0: 687b ldr r3, [r7, #4] 8003eb2: 699b ldr r3, [r3, #24] 8003eb4: 697a ldr r2, [r7, #20] 8003eb6: 429a cmp r2, r3 8003eb8: d014 beq.n 8003ee4 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 8003eba: 4b62 ldr r3, [pc, #392] @ (8004044 ) 8003ebc: 6ddb ldr r3, [r3, #92] @ 0x5c 8003ebe: 4a63 ldr r2, [pc, #396] @ (800404c ) 8003ec0: 4013 ands r3, r2 8003ec2: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8003ec4: 4b5f ldr r3, [pc, #380] @ (8004044 ) 8003ec6: 6dda ldr r2, [r3, #92] @ 0x5c 8003ec8: 4b5e ldr r3, [pc, #376] @ (8004044 ) 8003eca: 2180 movs r1, #128 @ 0x80 8003ecc: 0249 lsls r1, r1, #9 8003ece: 430a orrs r2, r1 8003ed0: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); 8003ed2: 4b5c ldr r3, [pc, #368] @ (8004044 ) 8003ed4: 6dda ldr r2, [r3, #92] @ 0x5c 8003ed6: 4b5b ldr r3, [pc, #364] @ (8004044 ) 8003ed8: 495d ldr r1, [pc, #372] @ (8004050 ) 8003eda: 400a ands r2, r1 8003edc: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 8003ede: 4b59 ldr r3, [pc, #356] @ (8004044 ) 8003ee0: 697a ldr r2, [r7, #20] 8003ee2: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 8003ee4: 697b ldr r3, [r7, #20] 8003ee6: 2201 movs r2, #1 8003ee8: 4013 ands r3, r2 8003eea: d016 beq.n 8003f1a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8003eec: f7fd f94c bl 8001188 8003ef0: 0003 movs r3, r0 8003ef2: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003ef4: e00c b.n 8003f10 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8003ef6: f7fd f947 bl 8001188 8003efa: 0002 movs r2, r0 8003efc: 68fb ldr r3, [r7, #12] 8003efe: 1ad3 subs r3, r2, r3 8003f00: 4a54 ldr r2, [pc, #336] @ (8004054 ) 8003f02: 4293 cmp r3, r2 8003f04: d904 bls.n 8003f10 { ret = HAL_TIMEOUT; 8003f06: 2313 movs r3, #19 8003f08: 18fb adds r3, r7, r3 8003f0a: 2203 movs r2, #3 8003f0c: 701a strb r2, [r3, #0] break; 8003f0e: e004 b.n 8003f1a while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) 8003f10: 4b4c ldr r3, [pc, #304] @ (8004044 ) 8003f12: 6ddb ldr r3, [r3, #92] @ 0x5c 8003f14: 2202 movs r2, #2 8003f16: 4013 ands r3, r2 8003f18: d0ed beq.n 8003ef6 } } } if (ret == HAL_OK) 8003f1a: 2313 movs r3, #19 8003f1c: 18fb adds r3, r7, r3 8003f1e: 781b ldrb r3, [r3, #0] 8003f20: 2b00 cmp r3, #0 8003f22: d10a bne.n 8003f3a { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8003f24: 4b47 ldr r3, [pc, #284] @ (8004044 ) 8003f26: 6ddb ldr r3, [r3, #92] @ 0x5c 8003f28: 4a48 ldr r2, [pc, #288] @ (800404c ) 8003f2a: 4013 ands r3, r2 8003f2c: 0019 movs r1, r3 8003f2e: 687b ldr r3, [r7, #4] 8003f30: 699a ldr r2, [r3, #24] 8003f32: 4b44 ldr r3, [pc, #272] @ (8004044 ) 8003f34: 430a orrs r2, r1 8003f36: 65da str r2, [r3, #92] @ 0x5c 8003f38: e00c b.n 8003f54 } else { /* set overall return value */ status = ret; 8003f3a: 2312 movs r3, #18 8003f3c: 18fb adds r3, r7, r3 8003f3e: 2213 movs r2, #19 8003f40: 18ba adds r2, r7, r2 8003f42: 7812 ldrb r2, [r2, #0] 8003f44: 701a strb r2, [r3, #0] 8003f46: e005 b.n 8003f54 } } else { /* set overall return value */ status = ret; 8003f48: 2312 movs r3, #18 8003f4a: 18fb adds r3, r7, r3 8003f4c: 2213 movs r2, #19 8003f4e: 18ba adds r2, r7, r2 8003f50: 7812 ldrb r2, [r2, #0] 8003f52: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8003f54: 2311 movs r3, #17 8003f56: 18fb adds r3, r7, r3 8003f58: 781b ldrb r3, [r3, #0] 8003f5a: 2b01 cmp r3, #1 8003f5c: d105 bne.n 8003f6a { __HAL_RCC_PWR_CLK_DISABLE(); 8003f5e: 4b39 ldr r3, [pc, #228] @ (8004044 ) 8003f60: 6bda ldr r2, [r3, #60] @ 0x3c 8003f62: 4b38 ldr r3, [pc, #224] @ (8004044 ) 8003f64: 493c ldr r1, [pc, #240] @ (8004058 ) 8003f66: 400a ands r2, r1 8003f68: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8003f6a: 687b ldr r3, [r7, #4] 8003f6c: 681b ldr r3, [r3, #0] 8003f6e: 2201 movs r2, #1 8003f70: 4013 ands r3, r2 8003f72: d009 beq.n 8003f88 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 8003f74: 4b33 ldr r3, [pc, #204] @ (8004044 ) 8003f76: 6d5b ldr r3, [r3, #84] @ 0x54 8003f78: 2203 movs r2, #3 8003f7a: 4393 bics r3, r2 8003f7c: 0019 movs r1, r3 8003f7e: 687b ldr r3, [r7, #4] 8003f80: 685a ldr r2, [r3, #4] 8003f82: 4b30 ldr r3, [pc, #192] @ (8004044 ) 8003f84: 430a orrs r2, r1 8003f86: 655a str r2, [r3, #84] @ 0x54 } #if defined(RCC_CCIPR_USART2SEL) /*-------------------------- USART2 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8003f88: 687b ldr r3, [r7, #4] 8003f8a: 681b ldr r3, [r3, #0] 8003f8c: 2202 movs r2, #2 8003f8e: 4013 ands r3, r2 8003f90: d009 beq.n 8003fa6 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8003f92: 4b2c ldr r3, [pc, #176] @ (8004044 ) 8003f94: 6d5b ldr r3, [r3, #84] @ 0x54 8003f96: 220c movs r2, #12 8003f98: 4393 bics r3, r2 8003f9a: 0019 movs r1, r3 8003f9c: 687b ldr r3, [r7, #4] 8003f9e: 689a ldr r2, [r3, #8] 8003fa0: 4b28 ldr r3, [pc, #160] @ (8004044 ) 8003fa2: 430a orrs r2, r1 8003fa4: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); } #endif /* RCC_CCIPR_LPTIM2SEL */ /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 681b ldr r3, [r3, #0] 8003faa: 2220 movs r2, #32 8003fac: 4013 ands r3, r2 8003fae: d009 beq.n 8003fc4 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 8003fb0: 4b24 ldr r3, [pc, #144] @ (8004044 ) 8003fb2: 6d5b ldr r3, [r3, #84] @ 0x54 8003fb4: 4a29 ldr r2, [pc, #164] @ (800405c ) 8003fb6: 4013 ands r3, r2 8003fb8: 0019 movs r1, r3 8003fba: 687b ldr r3, [r7, #4] 8003fbc: 68da ldr r2, [r3, #12] 8003fbe: 4b21 ldr r3, [pc, #132] @ (8004044 ) 8003fc0: 430a orrs r2, r1 8003fc2: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* RNG */ /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8003fc4: 687b ldr r3, [r7, #4] 8003fc6: 681a ldr r2, [r3, #0] 8003fc8: 2380 movs r3, #128 @ 0x80 8003fca: 01db lsls r3, r3, #7 8003fcc: 4013 ands r3, r2 8003fce: d015 beq.n 8003ffc { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8003fd0: 4b1c ldr r3, [pc, #112] @ (8004044 ) 8003fd2: 6d5b ldr r3, [r3, #84] @ 0x54 8003fd4: 009b lsls r3, r3, #2 8003fd6: 0899 lsrs r1, r3, #2 8003fd8: 687b ldr r3, [r7, #4] 8003fda: 695a ldr r2, [r3, #20] 8003fdc: 4b19 ldr r3, [pc, #100] @ (8004044 ) 8003fde: 430a orrs r2, r1 8003fe0: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) 8003fe2: 687b ldr r3, [r7, #4] 8003fe4: 695a ldr r2, [r3, #20] 8003fe6: 2380 movs r3, #128 @ 0x80 8003fe8: 05db lsls r3, r3, #23 8003fea: 429a cmp r2, r3 8003fec: d106 bne.n 8003ffc { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 8003fee: 4b15 ldr r3, [pc, #84] @ (8004044 ) 8003ff0: 68da ldr r2, [r3, #12] 8003ff2: 4b14 ldr r3, [pc, #80] @ (8004044 ) 8003ff4: 2180 movs r1, #128 @ 0x80 8003ff6: 0249 lsls r1, r1, #9 8003ff8: 430a orrs r2, r1 8003ffa: 60da str r2, [r3, #12] } } #endif /* RCC_CCIPR_TIM15SEL */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 681a ldr r2, [r3, #0] 8004000: 2380 movs r3, #128 @ 0x80 8004002: 011b lsls r3, r3, #4 8004004: 4013 ands r3, r2 8004006: d016 beq.n 8004036 { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); 8004008: 4b0e ldr r3, [pc, #56] @ (8004044 ) 800400a: 6d5b ldr r3, [r3, #84] @ 0x54 800400c: 4a14 ldr r2, [pc, #80] @ (8004060 ) 800400e: 4013 ands r3, r2 8004010: 0019 movs r1, r3 8004012: 687b ldr r3, [r7, #4] 8004014: 691a ldr r2, [r3, #16] 8004016: 4b0b ldr r3, [pc, #44] @ (8004044 ) 8004018: 430a orrs r2, r1 800401a: 655a str r2, [r3, #84] @ 0x54 if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) 800401c: 687b ldr r3, [r7, #4] 800401e: 691a ldr r2, [r3, #16] 8004020: 2380 movs r3, #128 @ 0x80 8004022: 01db lsls r3, r3, #7 8004024: 429a cmp r2, r3 8004026: d106 bne.n 8004036 { /* Enable PLLPCLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); 8004028: 4b06 ldr r3, [pc, #24] @ (8004044 ) 800402a: 68da ldr r2, [r3, #12] 800402c: 4b05 ldr r3, [pc, #20] @ (8004044 ) 800402e: 2180 movs r1, #128 @ 0x80 8004030: 0249 lsls r1, r1, #9 8004032: 430a orrs r2, r1 8004034: 60da str r2, [r3, #12] __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); } } #endif /* FDCAN1 || FDCAN2 */ return status; 8004036: 2312 movs r3, #18 8004038: 18fb adds r3, r7, r3 800403a: 781b ldrb r3, [r3, #0] } 800403c: 0018 movs r0, r3 800403e: 46bd mov sp, r7 8004040: b006 add sp, #24 8004042: bd80 pop {r7, pc} 8004044: 40021000 .word 0x40021000 8004048: 40007000 .word 0x40007000 800404c: fffffcff .word 0xfffffcff 8004050: fffeffff .word 0xfffeffff 8004054: 00001388 .word 0x00001388 8004058: efffffff .word 0xefffffff 800405c: ffffcfff .word 0xffffcfff 8004060: ffff3fff .word 0xffff3fff 08004064 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8004064: b580 push {r7, lr} 8004066: b082 sub sp, #8 8004068: af00 add r7, sp, #0 800406a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 800406c: 687b ldr r3, [r7, #4] 800406e: 2b00 cmp r3, #0 8004070: d101 bne.n 8004076 { return HAL_ERROR; 8004072: 2301 movs r3, #1 8004074: e046 b.n 8004104 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 8004076: 687b ldr r3, [r7, #4] 8004078: 2288 movs r2, #136 @ 0x88 800407a: 589b ldr r3, [r3, r2] 800407c: 2b00 cmp r3, #0 800407e: d107 bne.n 8004090 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8004080: 687b ldr r3, [r7, #4] 8004082: 2284 movs r2, #132 @ 0x84 8004084: 2100 movs r1, #0 8004086: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8004088: 687b ldr r3, [r7, #4] 800408a: 0018 movs r0, r3 800408c: f7fc ff3e bl 8000f0c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8004090: 687b ldr r3, [r7, #4] 8004092: 2288 movs r2, #136 @ 0x88 8004094: 2124 movs r1, #36 @ 0x24 8004096: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); 8004098: 687b ldr r3, [r7, #4] 800409a: 681b ldr r3, [r3, #0] 800409c: 681a ldr r2, [r3, #0] 800409e: 687b ldr r3, [r7, #4] 80040a0: 681b ldr r3, [r3, #0] 80040a2: 2101 movs r1, #1 80040a4: 438a bics r2, r1 80040a6: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80040a8: 687b ldr r3, [r7, #4] 80040aa: 6a9b ldr r3, [r3, #40] @ 0x28 80040ac: 2b00 cmp r3, #0 80040ae: d003 beq.n 80040b8 { UART_AdvFeatureConfig(huart); 80040b0: 687b ldr r3, [r7, #4] 80040b2: 0018 movs r0, r3 80040b4: f000 f9d0 bl 8004458 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 80040b8: 687b ldr r3, [r7, #4] 80040ba: 0018 movs r0, r3 80040bc: f000 f828 bl 8004110 80040c0: 0003 movs r3, r0 80040c2: 2b01 cmp r3, #1 80040c4: d101 bne.n 80040ca { return HAL_ERROR; 80040c6: 2301 movs r3, #1 80040c8: e01c b.n 8004104 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 80040ca: 687b ldr r3, [r7, #4] 80040cc: 681b ldr r3, [r3, #0] 80040ce: 685a ldr r2, [r3, #4] 80040d0: 687b ldr r3, [r7, #4] 80040d2: 681b ldr r3, [r3, #0] 80040d4: 490d ldr r1, [pc, #52] @ (800410c ) 80040d6: 400a ands r2, r1 80040d8: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80040da: 687b ldr r3, [r7, #4] 80040dc: 681b ldr r3, [r3, #0] 80040de: 689a ldr r2, [r3, #8] 80040e0: 687b ldr r3, [r7, #4] 80040e2: 681b ldr r3, [r3, #0] 80040e4: 212a movs r1, #42 @ 0x2a 80040e6: 438a bics r2, r1 80040e8: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80040ea: 687b ldr r3, [r7, #4] 80040ec: 681b ldr r3, [r3, #0] 80040ee: 681a ldr r2, [r3, #0] 80040f0: 687b ldr r3, [r7, #4] 80040f2: 681b ldr r3, [r3, #0] 80040f4: 2101 movs r1, #1 80040f6: 430a orrs r2, r1 80040f8: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80040fa: 687b ldr r3, [r7, #4] 80040fc: 0018 movs r0, r3 80040fe: f000 fa5f bl 80045c0 8004102: 0003 movs r3, r0 } 8004104: 0018 movs r0, r3 8004106: 46bd mov sp, r7 8004108: b002 add sp, #8 800410a: bd80 pop {r7, pc} 800410c: ffffb7ff .word 0xffffb7ff 08004110 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8004110: b580 push {r7, lr} 8004112: b088 sub sp, #32 8004114: af00 add r7, sp, #0 8004116: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8004118: 231a movs r3, #26 800411a: 18fb adds r3, r7, r3 800411c: 2200 movs r2, #0 800411e: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8004120: 687b ldr r3, [r7, #4] 8004122: 689a ldr r2, [r3, #8] 8004124: 687b ldr r3, [r7, #4] 8004126: 691b ldr r3, [r3, #16] 8004128: 431a orrs r2, r3 800412a: 687b ldr r3, [r7, #4] 800412c: 695b ldr r3, [r3, #20] 800412e: 431a orrs r2, r3 8004130: 687b ldr r3, [r7, #4] 8004132: 69db ldr r3, [r3, #28] 8004134: 4313 orrs r3, r2 8004136: 61fb str r3, [r7, #28] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8004138: 687b ldr r3, [r7, #4] 800413a: 681b ldr r3, [r3, #0] 800413c: 681b ldr r3, [r3, #0] 800413e: 4abc ldr r2, [pc, #752] @ (8004430 ) 8004140: 4013 ands r3, r2 8004142: 0019 movs r1, r3 8004144: 687b ldr r3, [r7, #4] 8004146: 681b ldr r3, [r3, #0] 8004148: 69fa ldr r2, [r7, #28] 800414a: 430a orrs r2, r1 800414c: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800414e: 687b ldr r3, [r7, #4] 8004150: 681b ldr r3, [r3, #0] 8004152: 685b ldr r3, [r3, #4] 8004154: 4ab7 ldr r2, [pc, #732] @ (8004434 ) 8004156: 4013 ands r3, r2 8004158: 0019 movs r1, r3 800415a: 687b ldr r3, [r7, #4] 800415c: 68da ldr r2, [r3, #12] 800415e: 687b ldr r3, [r7, #4] 8004160: 681b ldr r3, [r3, #0] 8004162: 430a orrs r2, r1 8004164: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8004166: 687b ldr r3, [r7, #4] 8004168: 699b ldr r3, [r3, #24] 800416a: 61fb str r3, [r7, #28] if (!(UART_INSTANCE_LOWPOWER(huart))) { tmpreg |= huart->Init.OneBitSampling; 800416c: 687b ldr r3, [r7, #4] 800416e: 6a1b ldr r3, [r3, #32] 8004170: 69fa ldr r2, [r7, #28] 8004172: 4313 orrs r3, r2 8004174: 61fb str r3, [r7, #28] } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8004176: 687b ldr r3, [r7, #4] 8004178: 681b ldr r3, [r3, #0] 800417a: 689b ldr r3, [r3, #8] 800417c: 4aae ldr r2, [pc, #696] @ (8004438 ) 800417e: 4013 ands r3, r2 8004180: 0019 movs r1, r3 8004182: 687b ldr r3, [r7, #4] 8004184: 681b ldr r3, [r3, #0] 8004186: 69fa ldr r2, [r7, #28] 8004188: 430a orrs r2, r1 800418a: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800418c: 687b ldr r3, [r7, #4] 800418e: 681b ldr r3, [r3, #0] 8004190: 6adb ldr r3, [r3, #44] @ 0x2c 8004192: 220f movs r2, #15 8004194: 4393 bics r3, r2 8004196: 0019 movs r1, r3 8004198: 687b ldr r3, [r7, #4] 800419a: 6a5a ldr r2, [r3, #36] @ 0x24 800419c: 687b ldr r3, [r7, #4] 800419e: 681b ldr r3, [r3, #0] 80041a0: 430a orrs r2, r1 80041a2: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 80041a4: 687b ldr r3, [r7, #4] 80041a6: 681b ldr r3, [r3, #0] 80041a8: 4aa4 ldr r2, [pc, #656] @ (800443c ) 80041aa: 4293 cmp r3, r2 80041ac: d127 bne.n 80041fe 80041ae: 4ba4 ldr r3, [pc, #656] @ (8004440 ) 80041b0: 6d5b ldr r3, [r3, #84] @ 0x54 80041b2: 2203 movs r2, #3 80041b4: 4013 ands r3, r2 80041b6: 2b03 cmp r3, #3 80041b8: d017 beq.n 80041ea 80041ba: d81b bhi.n 80041f4 80041bc: 2b02 cmp r3, #2 80041be: d00a beq.n 80041d6 80041c0: d818 bhi.n 80041f4 80041c2: 2b00 cmp r3, #0 80041c4: d002 beq.n 80041cc 80041c6: 2b01 cmp r3, #1 80041c8: d00a beq.n 80041e0 80041ca: e013 b.n 80041f4 80041cc: 231b movs r3, #27 80041ce: 18fb adds r3, r7, r3 80041d0: 2200 movs r2, #0 80041d2: 701a strb r2, [r3, #0] 80041d4: e058 b.n 8004288 80041d6: 231b movs r3, #27 80041d8: 18fb adds r3, r7, r3 80041da: 2202 movs r2, #2 80041dc: 701a strb r2, [r3, #0] 80041de: e053 b.n 8004288 80041e0: 231b movs r3, #27 80041e2: 18fb adds r3, r7, r3 80041e4: 2204 movs r2, #4 80041e6: 701a strb r2, [r3, #0] 80041e8: e04e b.n 8004288 80041ea: 231b movs r3, #27 80041ec: 18fb adds r3, r7, r3 80041ee: 2208 movs r2, #8 80041f0: 701a strb r2, [r3, #0] 80041f2: e049 b.n 8004288 80041f4: 231b movs r3, #27 80041f6: 18fb adds r3, r7, r3 80041f8: 2210 movs r2, #16 80041fa: 701a strb r2, [r3, #0] 80041fc: e044 b.n 8004288 80041fe: 687b ldr r3, [r7, #4] 8004200: 681b ldr r3, [r3, #0] 8004202: 4a90 ldr r2, [pc, #576] @ (8004444 ) 8004204: 4293 cmp r3, r2 8004206: d127 bne.n 8004258 8004208: 4b8d ldr r3, [pc, #564] @ (8004440 ) 800420a: 6d5b ldr r3, [r3, #84] @ 0x54 800420c: 220c movs r2, #12 800420e: 4013 ands r3, r2 8004210: 2b0c cmp r3, #12 8004212: d017 beq.n 8004244 8004214: d81b bhi.n 800424e 8004216: 2b08 cmp r3, #8 8004218: d00a beq.n 8004230 800421a: d818 bhi.n 800424e 800421c: 2b00 cmp r3, #0 800421e: d002 beq.n 8004226 8004220: 2b04 cmp r3, #4 8004222: d00a beq.n 800423a 8004224: e013 b.n 800424e 8004226: 231b movs r3, #27 8004228: 18fb adds r3, r7, r3 800422a: 2200 movs r2, #0 800422c: 701a strb r2, [r3, #0] 800422e: e02b b.n 8004288 8004230: 231b movs r3, #27 8004232: 18fb adds r3, r7, r3 8004234: 2202 movs r2, #2 8004236: 701a strb r2, [r3, #0] 8004238: e026 b.n 8004288 800423a: 231b movs r3, #27 800423c: 18fb adds r3, r7, r3 800423e: 2204 movs r2, #4 8004240: 701a strb r2, [r3, #0] 8004242: e021 b.n 8004288 8004244: 231b movs r3, #27 8004246: 18fb adds r3, r7, r3 8004248: 2208 movs r2, #8 800424a: 701a strb r2, [r3, #0] 800424c: e01c b.n 8004288 800424e: 231b movs r3, #27 8004250: 18fb adds r3, r7, r3 8004252: 2210 movs r2, #16 8004254: 701a strb r2, [r3, #0] 8004256: e017 b.n 8004288 8004258: 687b ldr r3, [r7, #4] 800425a: 681b ldr r3, [r3, #0] 800425c: 4a7a ldr r2, [pc, #488] @ (8004448 ) 800425e: 4293 cmp r3, r2 8004260: d104 bne.n 800426c 8004262: 231b movs r3, #27 8004264: 18fb adds r3, r7, r3 8004266: 2200 movs r2, #0 8004268: 701a strb r2, [r3, #0] 800426a: e00d b.n 8004288 800426c: 687b ldr r3, [r7, #4] 800426e: 681b ldr r3, [r3, #0] 8004270: 4a76 ldr r2, [pc, #472] @ (800444c ) 8004272: 4293 cmp r3, r2 8004274: d104 bne.n 8004280 8004276: 231b movs r3, #27 8004278: 18fb adds r3, r7, r3 800427a: 2200 movs r2, #0 800427c: 701a strb r2, [r3, #0] 800427e: e003 b.n 8004288 8004280: 231b movs r3, #27 8004282: 18fb adds r3, r7, r3 8004284: 2210 movs r2, #16 8004286: 701a strb r2, [r3, #0] } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8004288: 687b ldr r3, [r7, #4] 800428a: 69da ldr r2, [r3, #28] 800428c: 2380 movs r3, #128 @ 0x80 800428e: 021b lsls r3, r3, #8 8004290: 429a cmp r2, r3 8004292: d000 beq.n 8004296 8004294: e065 b.n 8004362 { switch (clocksource) 8004296: 231b movs r3, #27 8004298: 18fb adds r3, r7, r3 800429a: 781b ldrb r3, [r3, #0] 800429c: 2b08 cmp r3, #8 800429e: d015 beq.n 80042cc 80042a0: dc18 bgt.n 80042d4 80042a2: 2b04 cmp r3, #4 80042a4: d00d beq.n 80042c2 80042a6: dc15 bgt.n 80042d4 80042a8: 2b00 cmp r3, #0 80042aa: d002 beq.n 80042b2 80042ac: 2b02 cmp r3, #2 80042ae: d005 beq.n 80042bc 80042b0: e010 b.n 80042d4 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80042b2: f7ff fd8d bl 8003dd0 80042b6: 0003 movs r3, r0 80042b8: 617b str r3, [r7, #20] break; 80042ba: e012 b.n 80042e2 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 80042bc: 4b64 ldr r3, [pc, #400] @ (8004450 ) 80042be: 617b str r3, [r7, #20] break; 80042c0: e00f b.n 80042e2 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 80042c2: f7ff fcf9 bl 8003cb8 80042c6: 0003 movs r3, r0 80042c8: 617b str r3, [r7, #20] break; 80042ca: e00a b.n 80042e2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80042cc: 2380 movs r3, #128 @ 0x80 80042ce: 021b lsls r3, r3, #8 80042d0: 617b str r3, [r7, #20] break; 80042d2: e006 b.n 80042e2 default: pclk = 0U; 80042d4: 2300 movs r3, #0 80042d6: 617b str r3, [r7, #20] ret = HAL_ERROR; 80042d8: 231a movs r3, #26 80042da: 18fb adds r3, r7, r3 80042dc: 2201 movs r2, #1 80042de: 701a strb r2, [r3, #0] break; 80042e0: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80042e2: 697b ldr r3, [r7, #20] 80042e4: 2b00 cmp r3, #0 80042e6: d100 bne.n 80042ea 80042e8: e08d b.n 8004406 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80042ea: 687b ldr r3, [r7, #4] 80042ec: 6a5a ldr r2, [r3, #36] @ 0x24 80042ee: 4b59 ldr r3, [pc, #356] @ (8004454 ) 80042f0: 0052 lsls r2, r2, #1 80042f2: 5ad3 ldrh r3, [r2, r3] 80042f4: 0019 movs r1, r3 80042f6: 6978 ldr r0, [r7, #20] 80042f8: f7fb ff02 bl 8000100 <__udivsi3> 80042fc: 0003 movs r3, r0 80042fe: 005a lsls r2, r3, #1 8004300: 687b ldr r3, [r7, #4] 8004302: 685b ldr r3, [r3, #4] 8004304: 085b lsrs r3, r3, #1 8004306: 18d2 adds r2, r2, r3 8004308: 687b ldr r3, [r7, #4] 800430a: 685b ldr r3, [r3, #4] 800430c: 0019 movs r1, r3 800430e: 0010 movs r0, r2 8004310: f7fb fef6 bl 8000100 <__udivsi3> 8004314: 0003 movs r3, r0 8004316: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8004318: 693b ldr r3, [r7, #16] 800431a: 2b0f cmp r3, #15 800431c: d91c bls.n 8004358 800431e: 693a ldr r2, [r7, #16] 8004320: 2380 movs r3, #128 @ 0x80 8004322: 025b lsls r3, r3, #9 8004324: 429a cmp r2, r3 8004326: d217 bcs.n 8004358 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8004328: 693b ldr r3, [r7, #16] 800432a: b29a uxth r2, r3 800432c: 200e movs r0, #14 800432e: 183b adds r3, r7, r0 8004330: 210f movs r1, #15 8004332: 438a bics r2, r1 8004334: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8004336: 693b ldr r3, [r7, #16] 8004338: 085b lsrs r3, r3, #1 800433a: b29b uxth r3, r3 800433c: 2207 movs r2, #7 800433e: 4013 ands r3, r2 8004340: b299 uxth r1, r3 8004342: 183b adds r3, r7, r0 8004344: 183a adds r2, r7, r0 8004346: 8812 ldrh r2, [r2, #0] 8004348: 430a orrs r2, r1 800434a: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; 800434c: 687b ldr r3, [r7, #4] 800434e: 681b ldr r3, [r3, #0] 8004350: 183a adds r2, r7, r0 8004352: 8812 ldrh r2, [r2, #0] 8004354: 60da str r2, [r3, #12] 8004356: e056 b.n 8004406 } else { ret = HAL_ERROR; 8004358: 231a movs r3, #26 800435a: 18fb adds r3, r7, r3 800435c: 2201 movs r2, #1 800435e: 701a strb r2, [r3, #0] 8004360: e051 b.n 8004406 } } } else { switch (clocksource) 8004362: 231b movs r3, #27 8004364: 18fb adds r3, r7, r3 8004366: 781b ldrb r3, [r3, #0] 8004368: 2b08 cmp r3, #8 800436a: d015 beq.n 8004398 800436c: dc18 bgt.n 80043a0 800436e: 2b04 cmp r3, #4 8004370: d00d beq.n 800438e 8004372: dc15 bgt.n 80043a0 8004374: 2b00 cmp r3, #0 8004376: d002 beq.n 800437e 8004378: 2b02 cmp r3, #2 800437a: d005 beq.n 8004388 800437c: e010 b.n 80043a0 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 800437e: f7ff fd27 bl 8003dd0 8004382: 0003 movs r3, r0 8004384: 617b str r3, [r7, #20] break; 8004386: e012 b.n 80043ae case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; 8004388: 4b31 ldr r3, [pc, #196] @ (8004450 ) 800438a: 617b str r3, [r7, #20] break; 800438c: e00f b.n 80043ae case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 800438e: f7ff fc93 bl 8003cb8 8004392: 0003 movs r3, r0 8004394: 617b str r3, [r7, #20] break; 8004396: e00a b.n 80043ae case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8004398: 2380 movs r3, #128 @ 0x80 800439a: 021b lsls r3, r3, #8 800439c: 617b str r3, [r7, #20] break; 800439e: e006 b.n 80043ae default: pclk = 0U; 80043a0: 2300 movs r3, #0 80043a2: 617b str r3, [r7, #20] ret = HAL_ERROR; 80043a4: 231a movs r3, #26 80043a6: 18fb adds r3, r7, r3 80043a8: 2201 movs r2, #1 80043aa: 701a strb r2, [r3, #0] break; 80043ac: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) 80043ae: 697b ldr r3, [r7, #20] 80043b0: 2b00 cmp r3, #0 80043b2: d028 beq.n 8004406 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80043b4: 687b ldr r3, [r7, #4] 80043b6: 6a5a ldr r2, [r3, #36] @ 0x24 80043b8: 4b26 ldr r3, [pc, #152] @ (8004454 ) 80043ba: 0052 lsls r2, r2, #1 80043bc: 5ad3 ldrh r3, [r2, r3] 80043be: 0019 movs r1, r3 80043c0: 6978 ldr r0, [r7, #20] 80043c2: f7fb fe9d bl 8000100 <__udivsi3> 80043c6: 0003 movs r3, r0 80043c8: 001a movs r2, r3 80043ca: 687b ldr r3, [r7, #4] 80043cc: 685b ldr r3, [r3, #4] 80043ce: 085b lsrs r3, r3, #1 80043d0: 18d2 adds r2, r2, r3 80043d2: 687b ldr r3, [r7, #4] 80043d4: 685b ldr r3, [r3, #4] 80043d6: 0019 movs r1, r3 80043d8: 0010 movs r0, r2 80043da: f7fb fe91 bl 8000100 <__udivsi3> 80043de: 0003 movs r3, r0 80043e0: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80043e2: 693b ldr r3, [r7, #16] 80043e4: 2b0f cmp r3, #15 80043e6: d90a bls.n 80043fe 80043e8: 693a ldr r2, [r7, #16] 80043ea: 2380 movs r3, #128 @ 0x80 80043ec: 025b lsls r3, r3, #9 80043ee: 429a cmp r2, r3 80043f0: d205 bcs.n 80043fe { huart->Instance->BRR = (uint16_t)usartdiv; 80043f2: 693b ldr r3, [r7, #16] 80043f4: b29a uxth r2, r3 80043f6: 687b ldr r3, [r7, #4] 80043f8: 681b ldr r3, [r3, #0] 80043fa: 60da str r2, [r3, #12] 80043fc: e003 b.n 8004406 } else { ret = HAL_ERROR; 80043fe: 231a movs r3, #26 8004400: 18fb adds r3, r7, r3 8004402: 2201 movs r2, #1 8004404: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8004406: 687b ldr r3, [r7, #4] 8004408: 226a movs r2, #106 @ 0x6a 800440a: 2101 movs r1, #1 800440c: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; 800440e: 687b ldr r3, [r7, #4] 8004410: 2268 movs r2, #104 @ 0x68 8004412: 2101 movs r1, #1 8004414: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; 8004416: 687b ldr r3, [r7, #4] 8004418: 2200 movs r2, #0 800441a: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 800441c: 687b ldr r3, [r7, #4] 800441e: 2200 movs r2, #0 8004420: 679a str r2, [r3, #120] @ 0x78 return ret; 8004422: 231a movs r3, #26 8004424: 18fb adds r3, r7, r3 8004426: 781b ldrb r3, [r3, #0] } 8004428: 0018 movs r0, r3 800442a: 46bd mov sp, r7 800442c: b008 add sp, #32 800442e: bd80 pop {r7, pc} 8004430: cfff69f3 .word 0xcfff69f3 8004434: ffffcfff .word 0xffffcfff 8004438: 11fff4ff .word 0x11fff4ff 800443c: 40013800 .word 0x40013800 8004440: 40021000 .word 0x40021000 8004444: 40004400 .word 0x40004400 8004448: 40004800 .word 0x40004800 800444c: 40004c00 .word 0x40004c00 8004450: 00f42400 .word 0x00f42400 8004454: 08004be8 .word 0x08004be8 08004458 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8004458: b580 push {r7, lr} 800445a: b082 sub sp, #8 800445c: af00 add r7, sp, #0 800445e: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8004460: 687b ldr r3, [r7, #4] 8004462: 6a9b ldr r3, [r3, #40] @ 0x28 8004464: 2208 movs r2, #8 8004466: 4013 ands r3, r2 8004468: d00b beq.n 8004482 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800446a: 687b ldr r3, [r7, #4] 800446c: 681b ldr r3, [r3, #0] 800446e: 685b ldr r3, [r3, #4] 8004470: 4a4a ldr r2, [pc, #296] @ (800459c ) 8004472: 4013 ands r3, r2 8004474: 0019 movs r1, r3 8004476: 687b ldr r3, [r7, #4] 8004478: 6b9a ldr r2, [r3, #56] @ 0x38 800447a: 687b ldr r3, [r7, #4] 800447c: 681b ldr r3, [r3, #0] 800447e: 430a orrs r2, r1 8004480: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8004482: 687b ldr r3, [r7, #4] 8004484: 6a9b ldr r3, [r3, #40] @ 0x28 8004486: 2201 movs r2, #1 8004488: 4013 ands r3, r2 800448a: d00b beq.n 80044a4 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800448c: 687b ldr r3, [r7, #4] 800448e: 681b ldr r3, [r3, #0] 8004490: 685b ldr r3, [r3, #4] 8004492: 4a43 ldr r2, [pc, #268] @ (80045a0 ) 8004494: 4013 ands r3, r2 8004496: 0019 movs r1, r3 8004498: 687b ldr r3, [r7, #4] 800449a: 6ada ldr r2, [r3, #44] @ 0x2c 800449c: 687b ldr r3, [r7, #4] 800449e: 681b ldr r3, [r3, #0] 80044a0: 430a orrs r2, r1 80044a2: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 80044a4: 687b ldr r3, [r7, #4] 80044a6: 6a9b ldr r3, [r3, #40] @ 0x28 80044a8: 2202 movs r2, #2 80044aa: 4013 ands r3, r2 80044ac: d00b beq.n 80044c6 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 80044ae: 687b ldr r3, [r7, #4] 80044b0: 681b ldr r3, [r3, #0] 80044b2: 685b ldr r3, [r3, #4] 80044b4: 4a3b ldr r2, [pc, #236] @ (80045a4 ) 80044b6: 4013 ands r3, r2 80044b8: 0019 movs r1, r3 80044ba: 687b ldr r3, [r7, #4] 80044bc: 6b1a ldr r2, [r3, #48] @ 0x30 80044be: 687b ldr r3, [r7, #4] 80044c0: 681b ldr r3, [r3, #0] 80044c2: 430a orrs r2, r1 80044c4: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 80044c6: 687b ldr r3, [r7, #4] 80044c8: 6a9b ldr r3, [r3, #40] @ 0x28 80044ca: 2204 movs r2, #4 80044cc: 4013 ands r3, r2 80044ce: d00b beq.n 80044e8 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 80044d0: 687b ldr r3, [r7, #4] 80044d2: 681b ldr r3, [r3, #0] 80044d4: 685b ldr r3, [r3, #4] 80044d6: 4a34 ldr r2, [pc, #208] @ (80045a8 ) 80044d8: 4013 ands r3, r2 80044da: 0019 movs r1, r3 80044dc: 687b ldr r3, [r7, #4] 80044de: 6b5a ldr r2, [r3, #52] @ 0x34 80044e0: 687b ldr r3, [r7, #4] 80044e2: 681b ldr r3, [r3, #0] 80044e4: 430a orrs r2, r1 80044e6: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80044e8: 687b ldr r3, [r7, #4] 80044ea: 6a9b ldr r3, [r3, #40] @ 0x28 80044ec: 2210 movs r2, #16 80044ee: 4013 ands r3, r2 80044f0: d00b beq.n 800450a { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 80044f2: 687b ldr r3, [r7, #4] 80044f4: 681b ldr r3, [r3, #0] 80044f6: 689b ldr r3, [r3, #8] 80044f8: 4a2c ldr r2, [pc, #176] @ (80045ac ) 80044fa: 4013 ands r3, r2 80044fc: 0019 movs r1, r3 80044fe: 687b ldr r3, [r7, #4] 8004500: 6bda ldr r2, [r3, #60] @ 0x3c 8004502: 687b ldr r3, [r7, #4] 8004504: 681b ldr r3, [r3, #0] 8004506: 430a orrs r2, r1 8004508: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 800450a: 687b ldr r3, [r7, #4] 800450c: 6a9b ldr r3, [r3, #40] @ 0x28 800450e: 2220 movs r2, #32 8004510: 4013 ands r3, r2 8004512: d00b beq.n 800452c { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8004514: 687b ldr r3, [r7, #4] 8004516: 681b ldr r3, [r3, #0] 8004518: 689b ldr r3, [r3, #8] 800451a: 4a25 ldr r2, [pc, #148] @ (80045b0 ) 800451c: 4013 ands r3, r2 800451e: 0019 movs r1, r3 8004520: 687b ldr r3, [r7, #4] 8004522: 6c1a ldr r2, [r3, #64] @ 0x40 8004524: 687b ldr r3, [r7, #4] 8004526: 681b ldr r3, [r3, #0] 8004528: 430a orrs r2, r1 800452a: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 800452c: 687b ldr r3, [r7, #4] 800452e: 6a9b ldr r3, [r3, #40] @ 0x28 8004530: 2240 movs r2, #64 @ 0x40 8004532: 4013 ands r3, r2 8004534: d01d beq.n 8004572 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8004536: 687b ldr r3, [r7, #4] 8004538: 681b ldr r3, [r3, #0] 800453a: 685b ldr r3, [r3, #4] 800453c: 4a1d ldr r2, [pc, #116] @ (80045b4 ) 800453e: 4013 ands r3, r2 8004540: 0019 movs r1, r3 8004542: 687b ldr r3, [r7, #4] 8004544: 6c5a ldr r2, [r3, #68] @ 0x44 8004546: 687b ldr r3, [r7, #4] 8004548: 681b ldr r3, [r3, #0] 800454a: 430a orrs r2, r1 800454c: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800454e: 687b ldr r3, [r7, #4] 8004550: 6c5a ldr r2, [r3, #68] @ 0x44 8004552: 2380 movs r3, #128 @ 0x80 8004554: 035b lsls r3, r3, #13 8004556: 429a cmp r2, r3 8004558: d10b bne.n 8004572 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800455a: 687b ldr r3, [r7, #4] 800455c: 681b ldr r3, [r3, #0] 800455e: 685b ldr r3, [r3, #4] 8004560: 4a15 ldr r2, [pc, #84] @ (80045b8 ) 8004562: 4013 ands r3, r2 8004564: 0019 movs r1, r3 8004566: 687b ldr r3, [r7, #4] 8004568: 6c9a ldr r2, [r3, #72] @ 0x48 800456a: 687b ldr r3, [r7, #4] 800456c: 681b ldr r3, [r3, #0] 800456e: 430a orrs r2, r1 8004570: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8004572: 687b ldr r3, [r7, #4] 8004574: 6a9b ldr r3, [r3, #40] @ 0x28 8004576: 2280 movs r2, #128 @ 0x80 8004578: 4013 ands r3, r2 800457a: d00b beq.n 8004594 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 800457c: 687b ldr r3, [r7, #4] 800457e: 681b ldr r3, [r3, #0] 8004580: 685b ldr r3, [r3, #4] 8004582: 4a0e ldr r2, [pc, #56] @ (80045bc ) 8004584: 4013 ands r3, r2 8004586: 0019 movs r1, r3 8004588: 687b ldr r3, [r7, #4] 800458a: 6cda ldr r2, [r3, #76] @ 0x4c 800458c: 687b ldr r3, [r7, #4] 800458e: 681b ldr r3, [r3, #0] 8004590: 430a orrs r2, r1 8004592: 605a str r2, [r3, #4] } } 8004594: 46c0 nop @ (mov r8, r8) 8004596: 46bd mov sp, r7 8004598: b002 add sp, #8 800459a: bd80 pop {r7, pc} 800459c: ffff7fff .word 0xffff7fff 80045a0: fffdffff .word 0xfffdffff 80045a4: fffeffff .word 0xfffeffff 80045a8: fffbffff .word 0xfffbffff 80045ac: ffffefff .word 0xffffefff 80045b0: ffffdfff .word 0xffffdfff 80045b4: ffefffff .word 0xffefffff 80045b8: ff9fffff .word 0xff9fffff 80045bc: fff7ffff .word 0xfff7ffff 080045c0 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 80045c0: b580 push {r7, lr} 80045c2: b092 sub sp, #72 @ 0x48 80045c4: af02 add r7, sp, #8 80045c6: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80045c8: 687b ldr r3, [r7, #4] 80045ca: 2290 movs r2, #144 @ 0x90 80045cc: 2100 movs r1, #0 80045ce: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 80045d0: f7fc fdda bl 8001188 80045d4: 0003 movs r3, r0 80045d6: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 80045d8: 687b ldr r3, [r7, #4] 80045da: 681b ldr r3, [r3, #0] 80045dc: 681b ldr r3, [r3, #0] 80045de: 2208 movs r2, #8 80045e0: 4013 ands r3, r2 80045e2: 2b08 cmp r3, #8 80045e4: d12d bne.n 8004642 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80045e6: 6bfb ldr r3, [r7, #60] @ 0x3c 80045e8: 2280 movs r2, #128 @ 0x80 80045ea: 0391 lsls r1, r2, #14 80045ec: 6878 ldr r0, [r7, #4] 80045ee: 4a47 ldr r2, [pc, #284] @ (800470c ) 80045f0: 9200 str r2, [sp, #0] 80045f2: 2200 movs r2, #0 80045f4: f000 f88e bl 8004714 80045f8: 1e03 subs r3, r0, #0 80045fa: d022 beq.n 8004642 */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80045fc: f3ef 8310 mrs r3, PRIMASK 8004600: 627b str r3, [r7, #36] @ 0x24 return(result); 8004602: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8004604: 63bb str r3, [r7, #56] @ 0x38 8004606: 2301 movs r3, #1 8004608: 62bb str r3, [r7, #40] @ 0x28 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800460a: 6abb ldr r3, [r7, #40] @ 0x28 800460c: f383 8810 msr PRIMASK, r3 } 8004610: 46c0 nop @ (mov r8, r8) 8004612: 687b ldr r3, [r7, #4] 8004614: 681b ldr r3, [r3, #0] 8004616: 681a ldr r2, [r3, #0] 8004618: 687b ldr r3, [r7, #4] 800461a: 681b ldr r3, [r3, #0] 800461c: 2180 movs r1, #128 @ 0x80 800461e: 438a bics r2, r1 8004620: 601a str r2, [r3, #0] 8004622: 6bbb ldr r3, [r7, #56] @ 0x38 8004624: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004626: 6afb ldr r3, [r7, #44] @ 0x2c 8004628: f383 8810 msr PRIMASK, r3 } 800462c: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; 800462e: 687b ldr r3, [r7, #4] 8004630: 2288 movs r2, #136 @ 0x88 8004632: 2120 movs r1, #32 8004634: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 8004636: 687b ldr r3, [r7, #4] 8004638: 2284 movs r2, #132 @ 0x84 800463a: 2100 movs r1, #0 800463c: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 800463e: 2303 movs r3, #3 8004640: e060 b.n 8004704 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8004642: 687b ldr r3, [r7, #4] 8004644: 681b ldr r3, [r3, #0] 8004646: 681b ldr r3, [r3, #0] 8004648: 2204 movs r2, #4 800464a: 4013 ands r3, r2 800464c: 2b04 cmp r3, #4 800464e: d146 bne.n 80046de { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8004650: 6bfb ldr r3, [r7, #60] @ 0x3c 8004652: 2280 movs r2, #128 @ 0x80 8004654: 03d1 lsls r1, r2, #15 8004656: 6878 ldr r0, [r7, #4] 8004658: 4a2c ldr r2, [pc, #176] @ (800470c ) 800465a: 9200 str r2, [sp, #0] 800465c: 2200 movs r2, #0 800465e: f000 f859 bl 8004714 8004662: 1e03 subs r3, r0, #0 8004664: d03b beq.n 80046de __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004666: f3ef 8310 mrs r3, PRIMASK 800466a: 60fb str r3, [r7, #12] return(result); 800466c: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800466e: 637b str r3, [r7, #52] @ 0x34 8004670: 2301 movs r3, #1 8004672: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004674: 693b ldr r3, [r7, #16] 8004676: f383 8810 msr PRIMASK, r3 } 800467a: 46c0 nop @ (mov r8, r8) 800467c: 687b ldr r3, [r7, #4] 800467e: 681b ldr r3, [r3, #0] 8004680: 681a ldr r2, [r3, #0] 8004682: 687b ldr r3, [r7, #4] 8004684: 681b ldr r3, [r3, #0] 8004686: 4922 ldr r1, [pc, #136] @ (8004710 ) 8004688: 400a ands r2, r1 800468a: 601a str r2, [r3, #0] 800468c: 6b7b ldr r3, [r7, #52] @ 0x34 800468e: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004690: 697b ldr r3, [r7, #20] 8004692: f383 8810 msr PRIMASK, r3 } 8004696: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004698: f3ef 8310 mrs r3, PRIMASK 800469c: 61bb str r3, [r7, #24] return(result); 800469e: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80046a0: 633b str r3, [r7, #48] @ 0x30 80046a2: 2301 movs r3, #1 80046a4: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80046a6: 69fb ldr r3, [r7, #28] 80046a8: f383 8810 msr PRIMASK, r3 } 80046ac: 46c0 nop @ (mov r8, r8) 80046ae: 687b ldr r3, [r7, #4] 80046b0: 681b ldr r3, [r3, #0] 80046b2: 689a ldr r2, [r3, #8] 80046b4: 687b ldr r3, [r7, #4] 80046b6: 681b ldr r3, [r3, #0] 80046b8: 2101 movs r1, #1 80046ba: 438a bics r2, r1 80046bc: 609a str r2, [r3, #8] 80046be: 6b3b ldr r3, [r7, #48] @ 0x30 80046c0: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80046c2: 6a3b ldr r3, [r7, #32] 80046c4: f383 8810 msr PRIMASK, r3 } 80046c8: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; 80046ca: 687b ldr r3, [r7, #4] 80046cc: 228c movs r2, #140 @ 0x8c 80046ce: 2120 movs r1, #32 80046d0: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 80046d2: 687b ldr r3, [r7, #4] 80046d4: 2284 movs r2, #132 @ 0x84 80046d6: 2100 movs r1, #0 80046d8: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 80046da: 2303 movs r3, #3 80046dc: e012 b.n 8004704 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 80046de: 687b ldr r3, [r7, #4] 80046e0: 2288 movs r2, #136 @ 0x88 80046e2: 2120 movs r1, #32 80046e4: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; 80046e6: 687b ldr r3, [r7, #4] 80046e8: 228c movs r2, #140 @ 0x8c 80046ea: 2120 movs r1, #32 80046ec: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80046ee: 687b ldr r3, [r7, #4] 80046f0: 2200 movs r2, #0 80046f2: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 80046f4: 687b ldr r3, [r7, #4] 80046f6: 2200 movs r2, #0 80046f8: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 80046fa: 687b ldr r3, [r7, #4] 80046fc: 2284 movs r2, #132 @ 0x84 80046fe: 2100 movs r1, #0 8004700: 5499 strb r1, [r3, r2] return HAL_OK; 8004702: 2300 movs r3, #0 } 8004704: 0018 movs r0, r3 8004706: 46bd mov sp, r7 8004708: b010 add sp, #64 @ 0x40 800470a: bd80 pop {r7, pc} 800470c: 01ffffff .word 0x01ffffff 8004710: fffffedf .word 0xfffffedf 08004714 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8004714: b580 push {r7, lr} 8004716: b084 sub sp, #16 8004718: af00 add r7, sp, #0 800471a: 60f8 str r0, [r7, #12] 800471c: 60b9 str r1, [r7, #8] 800471e: 603b str r3, [r7, #0] 8004720: 1dfb adds r3, r7, #7 8004722: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8004724: e051 b.n 80047ca { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8004726: 69bb ldr r3, [r7, #24] 8004728: 3301 adds r3, #1 800472a: d04e beq.n 80047ca { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800472c: f7fc fd2c bl 8001188 8004730: 0002 movs r2, r0 8004732: 683b ldr r3, [r7, #0] 8004734: 1ad3 subs r3, r2, r3 8004736: 69ba ldr r2, [r7, #24] 8004738: 429a cmp r2, r3 800473a: d302 bcc.n 8004742 800473c: 69bb ldr r3, [r7, #24] 800473e: 2b00 cmp r3, #0 8004740: d101 bne.n 8004746 { return HAL_TIMEOUT; 8004742: 2303 movs r3, #3 8004744: e051 b.n 80047ea } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8004746: 68fb ldr r3, [r7, #12] 8004748: 681b ldr r3, [r3, #0] 800474a: 681b ldr r3, [r3, #0] 800474c: 2204 movs r2, #4 800474e: 4013 ands r3, r2 8004750: d03b beq.n 80047ca 8004752: 68bb ldr r3, [r7, #8] 8004754: 2b80 cmp r3, #128 @ 0x80 8004756: d038 beq.n 80047ca 8004758: 68bb ldr r3, [r7, #8] 800475a: 2b40 cmp r3, #64 @ 0x40 800475c: d035 beq.n 80047ca { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800475e: 68fb ldr r3, [r7, #12] 8004760: 681b ldr r3, [r3, #0] 8004762: 69db ldr r3, [r3, #28] 8004764: 2208 movs r2, #8 8004766: 4013 ands r3, r2 8004768: 2b08 cmp r3, #8 800476a: d111 bne.n 8004790 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800476c: 68fb ldr r3, [r7, #12] 800476e: 681b ldr r3, [r3, #0] 8004770: 2208 movs r2, #8 8004772: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8004774: 68fb ldr r3, [r7, #12] 8004776: 0018 movs r0, r3 8004778: f000 f83c bl 80047f4 huart->ErrorCode = HAL_UART_ERROR_ORE; 800477c: 68fb ldr r3, [r7, #12] 800477e: 2290 movs r2, #144 @ 0x90 8004780: 2108 movs r1, #8 8004782: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004784: 68fb ldr r3, [r7, #12] 8004786: 2284 movs r2, #132 @ 0x84 8004788: 2100 movs r1, #0 800478a: 5499 strb r1, [r3, r2] return HAL_ERROR; 800478c: 2301 movs r3, #1 800478e: e02c b.n 80047ea } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8004790: 68fb ldr r3, [r7, #12] 8004792: 681b ldr r3, [r3, #0] 8004794: 69da ldr r2, [r3, #28] 8004796: 2380 movs r3, #128 @ 0x80 8004798: 011b lsls r3, r3, #4 800479a: 401a ands r2, r3 800479c: 2380 movs r3, #128 @ 0x80 800479e: 011b lsls r3, r3, #4 80047a0: 429a cmp r2, r3 80047a2: d112 bne.n 80047ca { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 80047a4: 68fb ldr r3, [r7, #12] 80047a6: 681b ldr r3, [r3, #0] 80047a8: 2280 movs r2, #128 @ 0x80 80047aa: 0112 lsls r2, r2, #4 80047ac: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80047ae: 68fb ldr r3, [r7, #12] 80047b0: 0018 movs r0, r3 80047b2: f000 f81f bl 80047f4 huart->ErrorCode = HAL_UART_ERROR_RTO; 80047b6: 68fb ldr r3, [r7, #12] 80047b8: 2290 movs r2, #144 @ 0x90 80047ba: 2120 movs r1, #32 80047bc: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 80047be: 68fb ldr r3, [r7, #12] 80047c0: 2284 movs r2, #132 @ 0x84 80047c2: 2100 movs r1, #0 80047c4: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 80047c6: 2303 movs r3, #3 80047c8: e00f b.n 80047ea while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80047ca: 68fb ldr r3, [r7, #12] 80047cc: 681b ldr r3, [r3, #0] 80047ce: 69db ldr r3, [r3, #28] 80047d0: 68ba ldr r2, [r7, #8] 80047d2: 4013 ands r3, r2 80047d4: 68ba ldr r2, [r7, #8] 80047d6: 1ad3 subs r3, r2, r3 80047d8: 425a negs r2, r3 80047da: 4153 adcs r3, r2 80047dc: b2db uxtb r3, r3 80047de: 001a movs r2, r3 80047e0: 1dfb adds r3, r7, #7 80047e2: 781b ldrb r3, [r3, #0] 80047e4: 429a cmp r2, r3 80047e6: d09e beq.n 8004726 } } } } return HAL_OK; 80047e8: 2300 movs r3, #0 } 80047ea: 0018 movs r0, r3 80047ec: 46bd mov sp, r7 80047ee: b004 add sp, #16 80047f0: bd80 pop {r7, pc} ... 080047f4 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80047f4: b580 push {r7, lr} 80047f6: b08e sub sp, #56 @ 0x38 80047f8: af00 add r7, sp, #0 80047fa: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 80047fc: f3ef 8310 mrs r3, PRIMASK 8004800: 617b str r3, [r7, #20] return(result); 8004802: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8004804: 637b str r3, [r7, #52] @ 0x34 8004806: 2301 movs r3, #1 8004808: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800480a: 69bb ldr r3, [r7, #24] 800480c: f383 8810 msr PRIMASK, r3 } 8004810: 46c0 nop @ (mov r8, r8) 8004812: 687b ldr r3, [r7, #4] 8004814: 681b ldr r3, [r3, #0] 8004816: 681a ldr r2, [r3, #0] 8004818: 687b ldr r3, [r7, #4] 800481a: 681b ldr r3, [r3, #0] 800481c: 4926 ldr r1, [pc, #152] @ (80048b8 ) 800481e: 400a ands r2, r1 8004820: 601a str r2, [r3, #0] 8004822: 6b7b ldr r3, [r7, #52] @ 0x34 8004824: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004826: 69fb ldr r3, [r7, #28] 8004828: f383 8810 msr PRIMASK, r3 } 800482c: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 800482e: f3ef 8310 mrs r3, PRIMASK 8004832: 623b str r3, [r7, #32] return(result); 8004834: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8004836: 633b str r3, [r7, #48] @ 0x30 8004838: 2301 movs r3, #1 800483a: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800483c: 6a7b ldr r3, [r7, #36] @ 0x24 800483e: f383 8810 msr PRIMASK, r3 } 8004842: 46c0 nop @ (mov r8, r8) 8004844: 687b ldr r3, [r7, #4] 8004846: 681b ldr r3, [r3, #0] 8004848: 689a ldr r2, [r3, #8] 800484a: 687b ldr r3, [r7, #4] 800484c: 681b ldr r3, [r3, #0] 800484e: 491b ldr r1, [pc, #108] @ (80048bc ) 8004850: 400a ands r2, r1 8004852: 609a str r2, [r3, #8] 8004854: 6b3b ldr r3, [r7, #48] @ 0x30 8004856: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004858: 6abb ldr r3, [r7, #40] @ 0x28 800485a: f383 8810 msr PRIMASK, r3 } 800485e: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8004860: 687b ldr r3, [r7, #4] 8004862: 6edb ldr r3, [r3, #108] @ 0x6c 8004864: 2b01 cmp r3, #1 8004866: d118 bne.n 800489a __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 8004868: f3ef 8310 mrs r3, PRIMASK 800486c: 60bb str r3, [r7, #8] return(result); 800486e: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8004870: 62fb str r3, [r7, #44] @ 0x2c 8004872: 2301 movs r3, #1 8004874: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004876: 68fb ldr r3, [r7, #12] 8004878: f383 8810 msr PRIMASK, r3 } 800487c: 46c0 nop @ (mov r8, r8) 800487e: 687b ldr r3, [r7, #4] 8004880: 681b ldr r3, [r3, #0] 8004882: 681a ldr r2, [r3, #0] 8004884: 687b ldr r3, [r7, #4] 8004886: 681b ldr r3, [r3, #0] 8004888: 2110 movs r1, #16 800488a: 438a bics r2, r1 800488c: 601a str r2, [r3, #0] 800488e: 6afb ldr r3, [r7, #44] @ 0x2c 8004890: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8004892: 693b ldr r3, [r7, #16] 8004894: f383 8810 msr PRIMASK, r3 } 8004898: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800489a: 687b ldr r3, [r7, #4] 800489c: 228c movs r2, #140 @ 0x8c 800489e: 2120 movs r1, #32 80048a0: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80048a2: 687b ldr r3, [r7, #4] 80048a4: 2200 movs r2, #0 80048a6: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 80048a8: 687b ldr r3, [r7, #4] 80048aa: 2200 movs r2, #0 80048ac: 675a str r2, [r3, #116] @ 0x74 } 80048ae: 46c0 nop @ (mov r8, r8) 80048b0: 46bd mov sp, r7 80048b2: b00e add sp, #56 @ 0x38 80048b4: bd80 pop {r7, pc} 80048b6: 46c0 nop @ (mov r8, r8) 80048b8: fffffedf .word 0xfffffedf 80048bc: effffffe .word 0xeffffffe 080048c0 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 80048c0: b580 push {r7, lr} 80048c2: b084 sub sp, #16 80048c4: af00 add r7, sp, #0 80048c6: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 80048c8: 687b ldr r3, [r7, #4] 80048ca: 2284 movs r2, #132 @ 0x84 80048cc: 5c9b ldrb r3, [r3, r2] 80048ce: 2b01 cmp r3, #1 80048d0: d101 bne.n 80048d6 80048d2: 2302 movs r3, #2 80048d4: e027 b.n 8004926 80048d6: 687b ldr r3, [r7, #4] 80048d8: 2284 movs r2, #132 @ 0x84 80048da: 2101 movs r1, #1 80048dc: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 80048de: 687b ldr r3, [r7, #4] 80048e0: 2288 movs r2, #136 @ 0x88 80048e2: 2124 movs r1, #36 @ 0x24 80048e4: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80048e6: 687b ldr r3, [r7, #4] 80048e8: 681b ldr r3, [r3, #0] 80048ea: 681b ldr r3, [r3, #0] 80048ec: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80048ee: 687b ldr r3, [r7, #4] 80048f0: 681b ldr r3, [r3, #0] 80048f2: 681a ldr r2, [r3, #0] 80048f4: 687b ldr r3, [r7, #4] 80048f6: 681b ldr r3, [r3, #0] 80048f8: 2101 movs r1, #1 80048fa: 438a bics r2, r1 80048fc: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 80048fe: 68fb ldr r3, [r7, #12] 8004900: 4a0b ldr r2, [pc, #44] @ (8004930 ) 8004902: 4013 ands r3, r2 8004904: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8004906: 687b ldr r3, [r7, #4] 8004908: 2200 movs r2, #0 800490a: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800490c: 687b ldr r3, [r7, #4] 800490e: 681b ldr r3, [r3, #0] 8004910: 68fa ldr r2, [r7, #12] 8004912: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8004914: 687b ldr r3, [r7, #4] 8004916: 2288 movs r2, #136 @ 0x88 8004918: 2120 movs r1, #32 800491a: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 800491c: 687b ldr r3, [r7, #4] 800491e: 2284 movs r2, #132 @ 0x84 8004920: 2100 movs r1, #0 8004922: 5499 strb r1, [r3, r2] return HAL_OK; 8004924: 2300 movs r3, #0 } 8004926: 0018 movs r0, r3 8004928: 46bd mov sp, r7 800492a: b004 add sp, #16 800492c: bd80 pop {r7, pc} 800492e: 46c0 nop @ (mov r8, r8) 8004930: dfffffff .word 0xdfffffff 08004934 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8004934: b580 push {r7, lr} 8004936: b084 sub sp, #16 8004938: af00 add r7, sp, #0 800493a: 6078 str r0, [r7, #4] 800493c: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800493e: 687b ldr r3, [r7, #4] 8004940: 2284 movs r2, #132 @ 0x84 8004942: 5c9b ldrb r3, [r3, r2] 8004944: 2b01 cmp r3, #1 8004946: d101 bne.n 800494c 8004948: 2302 movs r3, #2 800494a: e02e b.n 80049aa 800494c: 687b ldr r3, [r7, #4] 800494e: 2284 movs r2, #132 @ 0x84 8004950: 2101 movs r1, #1 8004952: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 8004954: 687b ldr r3, [r7, #4] 8004956: 2288 movs r2, #136 @ 0x88 8004958: 2124 movs r1, #36 @ 0x24 800495a: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800495c: 687b ldr r3, [r7, #4] 800495e: 681b ldr r3, [r3, #0] 8004960: 681b ldr r3, [r3, #0] 8004962: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8004964: 687b ldr r3, [r7, #4] 8004966: 681b ldr r3, [r3, #0] 8004968: 681a ldr r2, [r3, #0] 800496a: 687b ldr r3, [r7, #4] 800496c: 681b ldr r3, [r3, #0] 800496e: 2101 movs r1, #1 8004970: 438a bics r2, r1 8004972: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8004974: 687b ldr r3, [r7, #4] 8004976: 681b ldr r3, [r3, #0] 8004978: 689b ldr r3, [r3, #8] 800497a: 00db lsls r3, r3, #3 800497c: 08d9 lsrs r1, r3, #3 800497e: 687b ldr r3, [r7, #4] 8004980: 681b ldr r3, [r3, #0] 8004982: 683a ldr r2, [r7, #0] 8004984: 430a orrs r2, r1 8004986: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8004988: 687b ldr r3, [r7, #4] 800498a: 0018 movs r0, r3 800498c: f000 f854 bl 8004a38 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8004990: 687b ldr r3, [r7, #4] 8004992: 681b ldr r3, [r3, #0] 8004994: 68fa ldr r2, [r7, #12] 8004996: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8004998: 687b ldr r3, [r7, #4] 800499a: 2288 movs r2, #136 @ 0x88 800499c: 2120 movs r1, #32 800499e: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 80049a0: 687b ldr r3, [r7, #4] 80049a2: 2284 movs r2, #132 @ 0x84 80049a4: 2100 movs r1, #0 80049a6: 5499 strb r1, [r3, r2] return HAL_OK; 80049a8: 2300 movs r3, #0 } 80049aa: 0018 movs r0, r3 80049ac: 46bd mov sp, r7 80049ae: b004 add sp, #16 80049b0: bd80 pop {r7, pc} ... 080049b4 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80049b4: b580 push {r7, lr} 80049b6: b084 sub sp, #16 80049b8: af00 add r7, sp, #0 80049ba: 6078 str r0, [r7, #4] 80049bc: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80049be: 687b ldr r3, [r7, #4] 80049c0: 2284 movs r2, #132 @ 0x84 80049c2: 5c9b ldrb r3, [r3, r2] 80049c4: 2b01 cmp r3, #1 80049c6: d101 bne.n 80049cc 80049c8: 2302 movs r3, #2 80049ca: e02f b.n 8004a2c 80049cc: 687b ldr r3, [r7, #4] 80049ce: 2284 movs r2, #132 @ 0x84 80049d0: 2101 movs r1, #1 80049d2: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 80049d4: 687b ldr r3, [r7, #4] 80049d6: 2288 movs r2, #136 @ 0x88 80049d8: 2124 movs r1, #36 @ 0x24 80049da: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80049dc: 687b ldr r3, [r7, #4] 80049de: 681b ldr r3, [r3, #0] 80049e0: 681b ldr r3, [r3, #0] 80049e2: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80049e4: 687b ldr r3, [r7, #4] 80049e6: 681b ldr r3, [r3, #0] 80049e8: 681a ldr r2, [r3, #0] 80049ea: 687b ldr r3, [r7, #4] 80049ec: 681b ldr r3, [r3, #0] 80049ee: 2101 movs r1, #1 80049f0: 438a bics r2, r1 80049f2: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 80049f4: 687b ldr r3, [r7, #4] 80049f6: 681b ldr r3, [r3, #0] 80049f8: 689b ldr r3, [r3, #8] 80049fa: 4a0e ldr r2, [pc, #56] @ (8004a34 ) 80049fc: 4013 ands r3, r2 80049fe: 0019 movs r1, r3 8004a00: 687b ldr r3, [r7, #4] 8004a02: 681b ldr r3, [r3, #0] 8004a04: 683a ldr r2, [r7, #0] 8004a06: 430a orrs r2, r1 8004a08: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8004a0a: 687b ldr r3, [r7, #4] 8004a0c: 0018 movs r0, r3 8004a0e: f000 f813 bl 8004a38 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8004a12: 687b ldr r3, [r7, #4] 8004a14: 681b ldr r3, [r3, #0] 8004a16: 68fa ldr r2, [r7, #12] 8004a18: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8004a1a: 687b ldr r3, [r7, #4] 8004a1c: 2288 movs r2, #136 @ 0x88 8004a1e: 2120 movs r1, #32 8004a20: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8004a22: 687b ldr r3, [r7, #4] 8004a24: 2284 movs r2, #132 @ 0x84 8004a26: 2100 movs r1, #0 8004a28: 5499 strb r1, [r3, r2] return HAL_OK; 8004a2a: 2300 movs r3, #0 } 8004a2c: 0018 movs r0, r3 8004a2e: 46bd mov sp, r7 8004a30: b004 add sp, #16 8004a32: bd80 pop {r7, pc} 8004a34: f1ffffff .word 0xf1ffffff 08004a38 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8004a38: b5f0 push {r4, r5, r6, r7, lr} 8004a3a: b085 sub sp, #20 8004a3c: af00 add r7, sp, #0 8004a3e: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8004a40: 687b ldr r3, [r7, #4] 8004a42: 6e5b ldr r3, [r3, #100] @ 0x64 8004a44: 2b00 cmp r3, #0 8004a46: d108 bne.n 8004a5a { huart->NbTxDataToProcess = 1U; 8004a48: 687b ldr r3, [r7, #4] 8004a4a: 226a movs r2, #106 @ 0x6a 8004a4c: 2101 movs r1, #1 8004a4e: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1U; 8004a50: 687b ldr r3, [r7, #4] 8004a52: 2268 movs r2, #104 @ 0x68 8004a54: 2101 movs r1, #1 8004a56: 5299 strh r1, [r3, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8004a58: e043 b.n 8004ae2 rx_fifo_depth = RX_FIFO_DEPTH; 8004a5a: 260f movs r6, #15 8004a5c: 19bb adds r3, r7, r6 8004a5e: 2208 movs r2, #8 8004a60: 701a strb r2, [r3, #0] tx_fifo_depth = TX_FIFO_DEPTH; 8004a62: 200e movs r0, #14 8004a64: 183b adds r3, r7, r0 8004a66: 2208 movs r2, #8 8004a68: 701a strb r2, [r3, #0] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8004a6a: 687b ldr r3, [r7, #4] 8004a6c: 681b ldr r3, [r3, #0] 8004a6e: 689b ldr r3, [r3, #8] 8004a70: 0e5b lsrs r3, r3, #25 8004a72: b2da uxtb r2, r3 8004a74: 240d movs r4, #13 8004a76: 193b adds r3, r7, r4 8004a78: 2107 movs r1, #7 8004a7a: 400a ands r2, r1 8004a7c: 701a strb r2, [r3, #0] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8004a7e: 687b ldr r3, [r7, #4] 8004a80: 681b ldr r3, [r3, #0] 8004a82: 689b ldr r3, [r3, #8] 8004a84: 0f5b lsrs r3, r3, #29 8004a86: b2da uxtb r2, r3 8004a88: 250c movs r5, #12 8004a8a: 197b adds r3, r7, r5 8004a8c: 2107 movs r1, #7 8004a8e: 400a ands r2, r1 8004a90: 701a strb r2, [r3, #0] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8004a92: 183b adds r3, r7, r0 8004a94: 781b ldrb r3, [r3, #0] 8004a96: 197a adds r2, r7, r5 8004a98: 7812 ldrb r2, [r2, #0] 8004a9a: 4914 ldr r1, [pc, #80] @ (8004aec ) 8004a9c: 5c8a ldrb r2, [r1, r2] 8004a9e: 435a muls r2, r3 8004aa0: 0010 movs r0, r2 (uint16_t)denominator[tx_fifo_threshold]; 8004aa2: 197b adds r3, r7, r5 8004aa4: 781b ldrb r3, [r3, #0] 8004aa6: 4a12 ldr r2, [pc, #72] @ (8004af0 ) 8004aa8: 5cd3 ldrb r3, [r2, r3] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8004aaa: 0019 movs r1, r3 8004aac: f7fb fbb2 bl 8000214 <__divsi3> 8004ab0: 0003 movs r3, r0 8004ab2: b299 uxth r1, r3 8004ab4: 687b ldr r3, [r7, #4] 8004ab6: 226a movs r2, #106 @ 0x6a 8004ab8: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8004aba: 19bb adds r3, r7, r6 8004abc: 781b ldrb r3, [r3, #0] 8004abe: 193a adds r2, r7, r4 8004ac0: 7812 ldrb r2, [r2, #0] 8004ac2: 490a ldr r1, [pc, #40] @ (8004aec ) 8004ac4: 5c8a ldrb r2, [r1, r2] 8004ac6: 435a muls r2, r3 8004ac8: 0010 movs r0, r2 (uint16_t)denominator[rx_fifo_threshold]; 8004aca: 193b adds r3, r7, r4 8004acc: 781b ldrb r3, [r3, #0] 8004ace: 4a08 ldr r2, [pc, #32] @ (8004af0 ) 8004ad0: 5cd3 ldrb r3, [r2, r3] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8004ad2: 0019 movs r1, r3 8004ad4: f7fb fb9e bl 8000214 <__divsi3> 8004ad8: 0003 movs r3, r0 8004ada: b299 uxth r1, r3 8004adc: 687b ldr r3, [r7, #4] 8004ade: 2268 movs r2, #104 @ 0x68 8004ae0: 5299 strh r1, [r3, r2] } 8004ae2: 46c0 nop @ (mov r8, r8) 8004ae4: 46bd mov sp, r7 8004ae6: b005 add sp, #20 8004ae8: bdf0 pop {r4, r5, r6, r7, pc} 8004aea: 46c0 nop @ (mov r8, r8) 8004aec: 08004c00 .word 0x08004c00 8004af0: 08004c08 .word 0x08004c08 08004af4 : 8004af4: 0003 movs r3, r0 8004af6: 1882 adds r2, r0, r2 8004af8: 4293 cmp r3, r2 8004afa: d100 bne.n 8004afe 8004afc: 4770 bx lr 8004afe: 7019 strb r1, [r3, #0] 8004b00: 3301 adds r3, #1 8004b02: e7f9 b.n 8004af8 08004b04 <__libc_init_array>: 8004b04: b570 push {r4, r5, r6, lr} 8004b06: 2600 movs r6, #0 8004b08: 4c0c ldr r4, [pc, #48] @ (8004b3c <__libc_init_array+0x38>) 8004b0a: 4d0d ldr r5, [pc, #52] @ (8004b40 <__libc_init_array+0x3c>) 8004b0c: 1b64 subs r4, r4, r5 8004b0e: 10a4 asrs r4, r4, #2 8004b10: 42a6 cmp r6, r4 8004b12: d109 bne.n 8004b28 <__libc_init_array+0x24> 8004b14: 2600 movs r6, #0 8004b16: f000 f819 bl 8004b4c <_init> 8004b1a: 4c0a ldr r4, [pc, #40] @ (8004b44 <__libc_init_array+0x40>) 8004b1c: 4d0a ldr r5, [pc, #40] @ (8004b48 <__libc_init_array+0x44>) 8004b1e: 1b64 subs r4, r4, r5 8004b20: 10a4 asrs r4, r4, #2 8004b22: 42a6 cmp r6, r4 8004b24: d105 bne.n 8004b32 <__libc_init_array+0x2e> 8004b26: bd70 pop {r4, r5, r6, pc} 8004b28: 00b3 lsls r3, r6, #2 8004b2a: 58eb ldr r3, [r5, r3] 8004b2c: 4798 blx r3 8004b2e: 3601 adds r6, #1 8004b30: e7ee b.n 8004b10 <__libc_init_array+0xc> 8004b32: 00b3 lsls r3, r6, #2 8004b34: 58eb ldr r3, [r5, r3] 8004b36: 4798 blx r3 8004b38: 3601 adds r6, #1 8004b3a: e7f2 b.n 8004b22 <__libc_init_array+0x1e> 8004b3c: 08004c10 .word 0x08004c10 8004b40: 08004c10 .word 0x08004c10 8004b44: 08004c14 .word 0x08004c14 8004b48: 08004c10 .word 0x08004c10 08004b4c <_init>: 8004b4c: b5f8 push {r3, r4, r5, r6, r7, lr} 8004b4e: 46c0 nop @ (mov r8, r8) 8004b50: bcf8 pop {r3, r4, r5, r6, r7} 8004b52: bc08 pop {r3} 8004b54: 469e mov lr, r3 8004b56: 4770 bx lr 08004b58 <_fini>: 8004b58: b5f8 push {r3, r4, r5, r6, r7, lr} 8004b5a: 46c0 nop @ (mov r8, r8) 8004b5c: bcf8 pop {r3, r4, r5, r6, r7} 8004b5e: bc08 pop {r3} 8004b60: 469e mov lr, r3 8004b62: 4770 bx lr