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wires/Debug/wires.list
Mitchell M e3de5f7ae5 init
2024-09-10 20:17:31 -05:00

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wires.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000b8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004a40 080000b8 080000b8 000010b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000ac 08004af8 08004af8 00005af8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004ba4 08004ba4 00006010 2**0
CONTENTS
4 .ARM 00000000 08004ba4 08004ba4 00006010 2**0
CONTENTS
5 .preinit_array 00000000 08004ba4 08004ba4 00006010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004ba4 08004ba4 00005ba4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08004ba8 08004ba8 00005ba8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000010 20000000 08004bac 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 0000012c 20000010 08004bbc 00006010 2**2
ALLOC
10 ._user_heap_stack 00000604 2000013c 08004bbc 0000613c 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00006010 2**0
CONTENTS, READONLY
12 .debug_info 0000e935 00000000 00000000 00006038 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000224a 00000000 00000000 0001496d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000ba8 00000000 00000000 00016bb8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 00000924 00000000 00000000 00017760 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00015028 00000000 00000000 00018084 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000101eb 00000000 00000000 0002d0ac 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 00083ada 00000000 00000000 0003d297 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 000c0d71 2**0
CONTENTS, READONLY
20 .debug_frame 00002940 00000000 00000000 000c0db4 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000061 00000000 00000000 000c36f4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000b8 <__do_global_dtors_aux>:
80000b8: b510 push {r4, lr}
80000ba: 4c06 ldr r4, [pc, #24] @ (80000d4 <__do_global_dtors_aux+0x1c>)
80000bc: 7823 ldrb r3, [r4, #0]
80000be: 2b00 cmp r3, #0
80000c0: d107 bne.n 80000d2 <__do_global_dtors_aux+0x1a>
80000c2: 4b05 ldr r3, [pc, #20] @ (80000d8 <__do_global_dtors_aux+0x20>)
80000c4: 2b00 cmp r3, #0
80000c6: d002 beq.n 80000ce <__do_global_dtors_aux+0x16>
80000c8: 4804 ldr r0, [pc, #16] @ (80000dc <__do_global_dtors_aux+0x24>)
80000ca: e000 b.n 80000ce <__do_global_dtors_aux+0x16>
80000cc: bf00 nop
80000ce: 2301 movs r3, #1
80000d0: 7023 strb r3, [r4, #0]
80000d2: bd10 pop {r4, pc}
80000d4: 20000010 .word 0x20000010
80000d8: 00000000 .word 0x00000000
80000dc: 08004ae0 .word 0x08004ae0
080000e0 <frame_dummy>:
80000e0: 4b04 ldr r3, [pc, #16] @ (80000f4 <frame_dummy+0x14>)
80000e2: b510 push {r4, lr}
80000e4: 2b00 cmp r3, #0
80000e6: d003 beq.n 80000f0 <frame_dummy+0x10>
80000e8: 4903 ldr r1, [pc, #12] @ (80000f8 <frame_dummy+0x18>)
80000ea: 4804 ldr r0, [pc, #16] @ (80000fc <frame_dummy+0x1c>)
80000ec: e000 b.n 80000f0 <frame_dummy+0x10>
80000ee: bf00 nop
80000f0: bd10 pop {r4, pc}
80000f2: 46c0 nop @ (mov r8, r8)
80000f4: 00000000 .word 0x00000000
80000f8: 20000014 .word 0x20000014
80000fc: 08004ae0 .word 0x08004ae0
08000100 <__udivsi3>:
8000100: 2200 movs r2, #0
8000102: 0843 lsrs r3, r0, #1
8000104: 428b cmp r3, r1
8000106: d374 bcc.n 80001f2 <__udivsi3+0xf2>
8000108: 0903 lsrs r3, r0, #4
800010a: 428b cmp r3, r1
800010c: d35f bcc.n 80001ce <__udivsi3+0xce>
800010e: 0a03 lsrs r3, r0, #8
8000110: 428b cmp r3, r1
8000112: d344 bcc.n 800019e <__udivsi3+0x9e>
8000114: 0b03 lsrs r3, r0, #12
8000116: 428b cmp r3, r1
8000118: d328 bcc.n 800016c <__udivsi3+0x6c>
800011a: 0c03 lsrs r3, r0, #16
800011c: 428b cmp r3, r1
800011e: d30d bcc.n 800013c <__udivsi3+0x3c>
8000120: 22ff movs r2, #255 @ 0xff
8000122: 0209 lsls r1, r1, #8
8000124: ba12 rev r2, r2
8000126: 0c03 lsrs r3, r0, #16
8000128: 428b cmp r3, r1
800012a: d302 bcc.n 8000132 <__udivsi3+0x32>
800012c: 1212 asrs r2, r2, #8
800012e: 0209 lsls r1, r1, #8
8000130: d065 beq.n 80001fe <__udivsi3+0xfe>
8000132: 0b03 lsrs r3, r0, #12
8000134: 428b cmp r3, r1
8000136: d319 bcc.n 800016c <__udivsi3+0x6c>
8000138: e000 b.n 800013c <__udivsi3+0x3c>
800013a: 0a09 lsrs r1, r1, #8
800013c: 0bc3 lsrs r3, r0, #15
800013e: 428b cmp r3, r1
8000140: d301 bcc.n 8000146 <__udivsi3+0x46>
8000142: 03cb lsls r3, r1, #15
8000144: 1ac0 subs r0, r0, r3
8000146: 4152 adcs r2, r2
8000148: 0b83 lsrs r3, r0, #14
800014a: 428b cmp r3, r1
800014c: d301 bcc.n 8000152 <__udivsi3+0x52>
800014e: 038b lsls r3, r1, #14
8000150: 1ac0 subs r0, r0, r3
8000152: 4152 adcs r2, r2
8000154: 0b43 lsrs r3, r0, #13
8000156: 428b cmp r3, r1
8000158: d301 bcc.n 800015e <__udivsi3+0x5e>
800015a: 034b lsls r3, r1, #13
800015c: 1ac0 subs r0, r0, r3
800015e: 4152 adcs r2, r2
8000160: 0b03 lsrs r3, r0, #12
8000162: 428b cmp r3, r1
8000164: d301 bcc.n 800016a <__udivsi3+0x6a>
8000166: 030b lsls r3, r1, #12
8000168: 1ac0 subs r0, r0, r3
800016a: 4152 adcs r2, r2
800016c: 0ac3 lsrs r3, r0, #11
800016e: 428b cmp r3, r1
8000170: d301 bcc.n 8000176 <__udivsi3+0x76>
8000172: 02cb lsls r3, r1, #11
8000174: 1ac0 subs r0, r0, r3
8000176: 4152 adcs r2, r2
8000178: 0a83 lsrs r3, r0, #10
800017a: 428b cmp r3, r1
800017c: d301 bcc.n 8000182 <__udivsi3+0x82>
800017e: 028b lsls r3, r1, #10
8000180: 1ac0 subs r0, r0, r3
8000182: 4152 adcs r2, r2
8000184: 0a43 lsrs r3, r0, #9
8000186: 428b cmp r3, r1
8000188: d301 bcc.n 800018e <__udivsi3+0x8e>
800018a: 024b lsls r3, r1, #9
800018c: 1ac0 subs r0, r0, r3
800018e: 4152 adcs r2, r2
8000190: 0a03 lsrs r3, r0, #8
8000192: 428b cmp r3, r1
8000194: d301 bcc.n 800019a <__udivsi3+0x9a>
8000196: 020b lsls r3, r1, #8
8000198: 1ac0 subs r0, r0, r3
800019a: 4152 adcs r2, r2
800019c: d2cd bcs.n 800013a <__udivsi3+0x3a>
800019e: 09c3 lsrs r3, r0, #7
80001a0: 428b cmp r3, r1
80001a2: d301 bcc.n 80001a8 <__udivsi3+0xa8>
80001a4: 01cb lsls r3, r1, #7
80001a6: 1ac0 subs r0, r0, r3
80001a8: 4152 adcs r2, r2
80001aa: 0983 lsrs r3, r0, #6
80001ac: 428b cmp r3, r1
80001ae: d301 bcc.n 80001b4 <__udivsi3+0xb4>
80001b0: 018b lsls r3, r1, #6
80001b2: 1ac0 subs r0, r0, r3
80001b4: 4152 adcs r2, r2
80001b6: 0943 lsrs r3, r0, #5
80001b8: 428b cmp r3, r1
80001ba: d301 bcc.n 80001c0 <__udivsi3+0xc0>
80001bc: 014b lsls r3, r1, #5
80001be: 1ac0 subs r0, r0, r3
80001c0: 4152 adcs r2, r2
80001c2: 0903 lsrs r3, r0, #4
80001c4: 428b cmp r3, r1
80001c6: d301 bcc.n 80001cc <__udivsi3+0xcc>
80001c8: 010b lsls r3, r1, #4
80001ca: 1ac0 subs r0, r0, r3
80001cc: 4152 adcs r2, r2
80001ce: 08c3 lsrs r3, r0, #3
80001d0: 428b cmp r3, r1
80001d2: d301 bcc.n 80001d8 <__udivsi3+0xd8>
80001d4: 00cb lsls r3, r1, #3
80001d6: 1ac0 subs r0, r0, r3
80001d8: 4152 adcs r2, r2
80001da: 0883 lsrs r3, r0, #2
80001dc: 428b cmp r3, r1
80001de: d301 bcc.n 80001e4 <__udivsi3+0xe4>
80001e0: 008b lsls r3, r1, #2
80001e2: 1ac0 subs r0, r0, r3
80001e4: 4152 adcs r2, r2
80001e6: 0843 lsrs r3, r0, #1
80001e8: 428b cmp r3, r1
80001ea: d301 bcc.n 80001f0 <__udivsi3+0xf0>
80001ec: 004b lsls r3, r1, #1
80001ee: 1ac0 subs r0, r0, r3
80001f0: 4152 adcs r2, r2
80001f2: 1a41 subs r1, r0, r1
80001f4: d200 bcs.n 80001f8 <__udivsi3+0xf8>
80001f6: 4601 mov r1, r0
80001f8: 4152 adcs r2, r2
80001fa: 4610 mov r0, r2
80001fc: 4770 bx lr
80001fe: e7ff b.n 8000200 <__udivsi3+0x100>
8000200: b501 push {r0, lr}
8000202: 2000 movs r0, #0
8000204: f000 f8f0 bl 80003e8 <__aeabi_idiv0>
8000208: bd02 pop {r1, pc}
800020a: 46c0 nop @ (mov r8, r8)
0800020c <__aeabi_uidivmod>:
800020c: 2900 cmp r1, #0
800020e: d0f7 beq.n 8000200 <__udivsi3+0x100>
8000210: e776 b.n 8000100 <__udivsi3>
8000212: 4770 bx lr
08000214 <__divsi3>:
8000214: 4603 mov r3, r0
8000216: 430b orrs r3, r1
8000218: d47f bmi.n 800031a <__divsi3+0x106>
800021a: 2200 movs r2, #0
800021c: 0843 lsrs r3, r0, #1
800021e: 428b cmp r3, r1
8000220: d374 bcc.n 800030c <__divsi3+0xf8>
8000222: 0903 lsrs r3, r0, #4
8000224: 428b cmp r3, r1
8000226: d35f bcc.n 80002e8 <__divsi3+0xd4>
8000228: 0a03 lsrs r3, r0, #8
800022a: 428b cmp r3, r1
800022c: d344 bcc.n 80002b8 <__divsi3+0xa4>
800022e: 0b03 lsrs r3, r0, #12
8000230: 428b cmp r3, r1
8000232: d328 bcc.n 8000286 <__divsi3+0x72>
8000234: 0c03 lsrs r3, r0, #16
8000236: 428b cmp r3, r1
8000238: d30d bcc.n 8000256 <__divsi3+0x42>
800023a: 22ff movs r2, #255 @ 0xff
800023c: 0209 lsls r1, r1, #8
800023e: ba12 rev r2, r2
8000240: 0c03 lsrs r3, r0, #16
8000242: 428b cmp r3, r1
8000244: d302 bcc.n 800024c <__divsi3+0x38>
8000246: 1212 asrs r2, r2, #8
8000248: 0209 lsls r1, r1, #8
800024a: d065 beq.n 8000318 <__divsi3+0x104>
800024c: 0b03 lsrs r3, r0, #12
800024e: 428b cmp r3, r1
8000250: d319 bcc.n 8000286 <__divsi3+0x72>
8000252: e000 b.n 8000256 <__divsi3+0x42>
8000254: 0a09 lsrs r1, r1, #8
8000256: 0bc3 lsrs r3, r0, #15
8000258: 428b cmp r3, r1
800025a: d301 bcc.n 8000260 <__divsi3+0x4c>
800025c: 03cb lsls r3, r1, #15
800025e: 1ac0 subs r0, r0, r3
8000260: 4152 adcs r2, r2
8000262: 0b83 lsrs r3, r0, #14
8000264: 428b cmp r3, r1
8000266: d301 bcc.n 800026c <__divsi3+0x58>
8000268: 038b lsls r3, r1, #14
800026a: 1ac0 subs r0, r0, r3
800026c: 4152 adcs r2, r2
800026e: 0b43 lsrs r3, r0, #13
8000270: 428b cmp r3, r1
8000272: d301 bcc.n 8000278 <__divsi3+0x64>
8000274: 034b lsls r3, r1, #13
8000276: 1ac0 subs r0, r0, r3
8000278: 4152 adcs r2, r2
800027a: 0b03 lsrs r3, r0, #12
800027c: 428b cmp r3, r1
800027e: d301 bcc.n 8000284 <__divsi3+0x70>
8000280: 030b lsls r3, r1, #12
8000282: 1ac0 subs r0, r0, r3
8000284: 4152 adcs r2, r2
8000286: 0ac3 lsrs r3, r0, #11
8000288: 428b cmp r3, r1
800028a: d301 bcc.n 8000290 <__divsi3+0x7c>
800028c: 02cb lsls r3, r1, #11
800028e: 1ac0 subs r0, r0, r3
8000290: 4152 adcs r2, r2
8000292: 0a83 lsrs r3, r0, #10
8000294: 428b cmp r3, r1
8000296: d301 bcc.n 800029c <__divsi3+0x88>
8000298: 028b lsls r3, r1, #10
800029a: 1ac0 subs r0, r0, r3
800029c: 4152 adcs r2, r2
800029e: 0a43 lsrs r3, r0, #9
80002a0: 428b cmp r3, r1
80002a2: d301 bcc.n 80002a8 <__divsi3+0x94>
80002a4: 024b lsls r3, r1, #9
80002a6: 1ac0 subs r0, r0, r3
80002a8: 4152 adcs r2, r2
80002aa: 0a03 lsrs r3, r0, #8
80002ac: 428b cmp r3, r1
80002ae: d301 bcc.n 80002b4 <__divsi3+0xa0>
80002b0: 020b lsls r3, r1, #8
80002b2: 1ac0 subs r0, r0, r3
80002b4: 4152 adcs r2, r2
80002b6: d2cd bcs.n 8000254 <__divsi3+0x40>
80002b8: 09c3 lsrs r3, r0, #7
80002ba: 428b cmp r3, r1
80002bc: d301 bcc.n 80002c2 <__divsi3+0xae>
80002be: 01cb lsls r3, r1, #7
80002c0: 1ac0 subs r0, r0, r3
80002c2: 4152 adcs r2, r2
80002c4: 0983 lsrs r3, r0, #6
80002c6: 428b cmp r3, r1
80002c8: d301 bcc.n 80002ce <__divsi3+0xba>
80002ca: 018b lsls r3, r1, #6
80002cc: 1ac0 subs r0, r0, r3
80002ce: 4152 adcs r2, r2
80002d0: 0943 lsrs r3, r0, #5
80002d2: 428b cmp r3, r1
80002d4: d301 bcc.n 80002da <__divsi3+0xc6>
80002d6: 014b lsls r3, r1, #5
80002d8: 1ac0 subs r0, r0, r3
80002da: 4152 adcs r2, r2
80002dc: 0903 lsrs r3, r0, #4
80002de: 428b cmp r3, r1
80002e0: d301 bcc.n 80002e6 <__divsi3+0xd2>
80002e2: 010b lsls r3, r1, #4
80002e4: 1ac0 subs r0, r0, r3
80002e6: 4152 adcs r2, r2
80002e8: 08c3 lsrs r3, r0, #3
80002ea: 428b cmp r3, r1
80002ec: d301 bcc.n 80002f2 <__divsi3+0xde>
80002ee: 00cb lsls r3, r1, #3
80002f0: 1ac0 subs r0, r0, r3
80002f2: 4152 adcs r2, r2
80002f4: 0883 lsrs r3, r0, #2
80002f6: 428b cmp r3, r1
80002f8: d301 bcc.n 80002fe <__divsi3+0xea>
80002fa: 008b lsls r3, r1, #2
80002fc: 1ac0 subs r0, r0, r3
80002fe: 4152 adcs r2, r2
8000300: 0843 lsrs r3, r0, #1
8000302: 428b cmp r3, r1
8000304: d301 bcc.n 800030a <__divsi3+0xf6>
8000306: 004b lsls r3, r1, #1
8000308: 1ac0 subs r0, r0, r3
800030a: 4152 adcs r2, r2
800030c: 1a41 subs r1, r0, r1
800030e: d200 bcs.n 8000312 <__divsi3+0xfe>
8000310: 4601 mov r1, r0
8000312: 4152 adcs r2, r2
8000314: 4610 mov r0, r2
8000316: 4770 bx lr
8000318: e05d b.n 80003d6 <__divsi3+0x1c2>
800031a: 0fca lsrs r2, r1, #31
800031c: d000 beq.n 8000320 <__divsi3+0x10c>
800031e: 4249 negs r1, r1
8000320: 1003 asrs r3, r0, #32
8000322: d300 bcc.n 8000326 <__divsi3+0x112>
8000324: 4240 negs r0, r0
8000326: 4053 eors r3, r2
8000328: 2200 movs r2, #0
800032a: 469c mov ip, r3
800032c: 0903 lsrs r3, r0, #4
800032e: 428b cmp r3, r1
8000330: d32d bcc.n 800038e <__divsi3+0x17a>
8000332: 0a03 lsrs r3, r0, #8
8000334: 428b cmp r3, r1
8000336: d312 bcc.n 800035e <__divsi3+0x14a>
8000338: 22fc movs r2, #252 @ 0xfc
800033a: 0189 lsls r1, r1, #6
800033c: ba12 rev r2, r2
800033e: 0a03 lsrs r3, r0, #8
8000340: 428b cmp r3, r1
8000342: d30c bcc.n 800035e <__divsi3+0x14a>
8000344: 0189 lsls r1, r1, #6
8000346: 1192 asrs r2, r2, #6
8000348: 428b cmp r3, r1
800034a: d308 bcc.n 800035e <__divsi3+0x14a>
800034c: 0189 lsls r1, r1, #6
800034e: 1192 asrs r2, r2, #6
8000350: 428b cmp r3, r1
8000352: d304 bcc.n 800035e <__divsi3+0x14a>
8000354: 0189 lsls r1, r1, #6
8000356: d03a beq.n 80003ce <__divsi3+0x1ba>
8000358: 1192 asrs r2, r2, #6
800035a: e000 b.n 800035e <__divsi3+0x14a>
800035c: 0989 lsrs r1, r1, #6
800035e: 09c3 lsrs r3, r0, #7
8000360: 428b cmp r3, r1
8000362: d301 bcc.n 8000368 <__divsi3+0x154>
8000364: 01cb lsls r3, r1, #7
8000366: 1ac0 subs r0, r0, r3
8000368: 4152 adcs r2, r2
800036a: 0983 lsrs r3, r0, #6
800036c: 428b cmp r3, r1
800036e: d301 bcc.n 8000374 <__divsi3+0x160>
8000370: 018b lsls r3, r1, #6
8000372: 1ac0 subs r0, r0, r3
8000374: 4152 adcs r2, r2
8000376: 0943 lsrs r3, r0, #5
8000378: 428b cmp r3, r1
800037a: d301 bcc.n 8000380 <__divsi3+0x16c>
800037c: 014b lsls r3, r1, #5
800037e: 1ac0 subs r0, r0, r3
8000380: 4152 adcs r2, r2
8000382: 0903 lsrs r3, r0, #4
8000384: 428b cmp r3, r1
8000386: d301 bcc.n 800038c <__divsi3+0x178>
8000388: 010b lsls r3, r1, #4
800038a: 1ac0 subs r0, r0, r3
800038c: 4152 adcs r2, r2
800038e: 08c3 lsrs r3, r0, #3
8000390: 428b cmp r3, r1
8000392: d301 bcc.n 8000398 <__divsi3+0x184>
8000394: 00cb lsls r3, r1, #3
8000396: 1ac0 subs r0, r0, r3
8000398: 4152 adcs r2, r2
800039a: 0883 lsrs r3, r0, #2
800039c: 428b cmp r3, r1
800039e: d301 bcc.n 80003a4 <__divsi3+0x190>
80003a0: 008b lsls r3, r1, #2
80003a2: 1ac0 subs r0, r0, r3
80003a4: 4152 adcs r2, r2
80003a6: d2d9 bcs.n 800035c <__divsi3+0x148>
80003a8: 0843 lsrs r3, r0, #1
80003aa: 428b cmp r3, r1
80003ac: d301 bcc.n 80003b2 <__divsi3+0x19e>
80003ae: 004b lsls r3, r1, #1
80003b0: 1ac0 subs r0, r0, r3
80003b2: 4152 adcs r2, r2
80003b4: 1a41 subs r1, r0, r1
80003b6: d200 bcs.n 80003ba <__divsi3+0x1a6>
80003b8: 4601 mov r1, r0
80003ba: 4663 mov r3, ip
80003bc: 4152 adcs r2, r2
80003be: 105b asrs r3, r3, #1
80003c0: 4610 mov r0, r2
80003c2: d301 bcc.n 80003c8 <__divsi3+0x1b4>
80003c4: 4240 negs r0, r0
80003c6: 2b00 cmp r3, #0
80003c8: d500 bpl.n 80003cc <__divsi3+0x1b8>
80003ca: 4249 negs r1, r1
80003cc: 4770 bx lr
80003ce: 4663 mov r3, ip
80003d0: 105b asrs r3, r3, #1
80003d2: d300 bcc.n 80003d6 <__divsi3+0x1c2>
80003d4: 4240 negs r0, r0
80003d6: b501 push {r0, lr}
80003d8: 2000 movs r0, #0
80003da: f000 f805 bl 80003e8 <__aeabi_idiv0>
80003de: bd02 pop {r1, pc}
080003e0 <__aeabi_idivmod>:
80003e0: 2900 cmp r1, #0
80003e2: d0f8 beq.n 80003d6 <__divsi3+0x1c2>
80003e4: e716 b.n 8000214 <__divsi3>
80003e6: 4770 bx lr
080003e8 <__aeabi_idiv0>:
80003e8: 4770 bx lr
80003ea: 46c0 nop @ (mov r8, r8)
080003ec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80003ec: b580 push {r7, lr}
80003ee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80003f0: f000 fe18 bl 8001024 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80003f4: f000 f81a bl 800042c <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80003f8: f000 f8ee bl 80005d8 <MX_GPIO_Init>
MX_I2C1_Init();
80003fc: f000 f85e bl 80004bc <MX_I2C1_Init>
MX_USART2_UART_Init();
8000400: f000 f89c bl 800053c <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
HAL_I2C_EnableListen_IT(&hi2c1);
8000404: 4b08 ldr r3, [pc, #32] @ (8000428 <main+0x3c>)
8000406: 0018 movs r0, r3
8000408: f001 fbc2 bl 8001b90 <HAL_I2C_EnableListen_IT>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
scan_wires();
800040c: f000 fac8 bl 80009a0 <scan_wires>
scan_button();
8000410: f000 fb82 bl 8000b18 <scan_button>
handle_strike();
8000414: f000 fc42 bl 8000c9c <handle_strike>
set_relay_buzz();
8000418: f000 fbaa bl 8000b70 <set_relay_buzz>
set_leds();
800041c: f000 fbd6 bl 8000bcc <set_leds>
send_interupt();
8000420: f000 fc1c bl 8000c5c <send_interupt>
scan_wires();
8000424: 46c0 nop @ (mov r8, r8)
8000426: e7f1 b.n 800040c <main+0x20>
8000428: 20000030 .word 0x20000030
0800042c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800042c: b590 push {r4, r7, lr}
800042e: b093 sub sp, #76 @ 0x4c
8000430: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000432: 2414 movs r4, #20
8000434: 193b adds r3, r7, r4
8000436: 0018 movs r0, r3
8000438: 2334 movs r3, #52 @ 0x34
800043a: 001a movs r2, r3
800043c: 2100 movs r1, #0
800043e: f004 fb23 bl 8004a88 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000442: 1d3b adds r3, r7, #4
8000444: 0018 movs r0, r3
8000446: 2310 movs r3, #16
8000448: 001a movs r2, r3
800044a: 2100 movs r1, #0
800044c: f004 fb1c bl 8004a88 <memset>
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
8000450: 2380 movs r3, #128 @ 0x80
8000452: 009b lsls r3, r3, #2
8000454: 0018 movs r0, r3
8000456: f002 ff95 bl 8003384 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800045a: 193b adds r3, r7, r4
800045c: 2202 movs r2, #2
800045e: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000460: 193b adds r3, r7, r4
8000462: 2280 movs r2, #128 @ 0x80
8000464: 0052 lsls r2, r2, #1
8000466: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
8000468: 193b adds r3, r7, r4
800046a: 2200 movs r2, #0
800046c: 611a str r2, [r3, #16]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800046e: 193b adds r3, r7, r4
8000470: 2240 movs r2, #64 @ 0x40
8000472: 615a str r2, [r3, #20]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8000474: 193b adds r3, r7, r4
8000476: 2200 movs r2, #0
8000478: 61da str r2, [r3, #28]
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800047a: 193b adds r3, r7, r4
800047c: 0018 movs r0, r3
800047e: f002 ffcd bl 800341c <HAL_RCC_OscConfig>
8000482: 1e03 subs r3, r0, #0
8000484: d001 beq.n 800048a <SystemClock_Config+0x5e>
{
Error_Handler();
8000486: f000 fc73 bl 8000d70 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800048a: 1d3b adds r3, r7, #4
800048c: 2207 movs r2, #7
800048e: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
8000490: 1d3b adds r3, r7, #4
8000492: 2200 movs r2, #0
8000494: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000496: 1d3b adds r3, r7, #4
8000498: 2200 movs r2, #0
800049a: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
800049c: 1d3b adds r3, r7, #4
800049e: 2200 movs r2, #0
80004a0: 60da str r2, [r3, #12]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80004a2: 1d3b adds r3, r7, #4
80004a4: 2100 movs r1, #0
80004a6: 0018 movs r0, r3
80004a8: f003 fac8 bl 8003a3c <HAL_RCC_ClockConfig>
80004ac: 1e03 subs r3, r0, #0
80004ae: d001 beq.n 80004b4 <SystemClock_Config+0x88>
{
Error_Handler();
80004b0: f000 fc5e bl 8000d70 <Error_Handler>
}
}
80004b4: 46c0 nop @ (mov r8, r8)
80004b6: 46bd mov sp, r7
80004b8: b013 add sp, #76 @ 0x4c
80004ba: bd90 pop {r4, r7, pc}
080004bc <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
80004bc: b580 push {r7, lr}
80004be: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
80004c0: 4b1b ldr r3, [pc, #108] @ (8000530 <MX_I2C1_Init+0x74>)
80004c2: 4a1c ldr r2, [pc, #112] @ (8000534 <MX_I2C1_Init+0x78>)
80004c4: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x00303D5B;
80004c6: 4b1a ldr r3, [pc, #104] @ (8000530 <MX_I2C1_Init+0x74>)
80004c8: 4a1b ldr r2, [pc, #108] @ (8000538 <MX_I2C1_Init+0x7c>)
80004ca: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 250;
80004cc: 4b18 ldr r3, [pc, #96] @ (8000530 <MX_I2C1_Init+0x74>)
80004ce: 22fa movs r2, #250 @ 0xfa
80004d0: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
80004d2: 4b17 ldr r3, [pc, #92] @ (8000530 <MX_I2C1_Init+0x74>)
80004d4: 2201 movs r2, #1
80004d6: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
80004d8: 4b15 ldr r3, [pc, #84] @ (8000530 <MX_I2C1_Init+0x74>)
80004da: 2200 movs r2, #0
80004dc: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
80004de: 4b14 ldr r3, [pc, #80] @ (8000530 <MX_I2C1_Init+0x74>)
80004e0: 2200 movs r2, #0
80004e2: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
80004e4: 4b12 ldr r3, [pc, #72] @ (8000530 <MX_I2C1_Init+0x74>)
80004e6: 2200 movs r2, #0
80004e8: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
80004ea: 4b11 ldr r3, [pc, #68] @ (8000530 <MX_I2C1_Init+0x74>)
80004ec: 2200 movs r2, #0
80004ee: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80004f0: 4b0f ldr r3, [pc, #60] @ (8000530 <MX_I2C1_Init+0x74>)
80004f2: 2200 movs r2, #0
80004f4: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
80004f6: 4b0e ldr r3, [pc, #56] @ (8000530 <MX_I2C1_Init+0x74>)
80004f8: 0018 movs r0, r3
80004fa: f001 f921 bl 8001740 <HAL_I2C_Init>
80004fe: 1e03 subs r3, r0, #0
8000500: d001 beq.n 8000506 <MX_I2C1_Init+0x4a>
{
Error_Handler();
8000502: f000 fc35 bl 8000d70 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8000506: 4b0a ldr r3, [pc, #40] @ (8000530 <MX_I2C1_Init+0x74>)
8000508: 2100 movs r1, #0
800050a: 0018 movs r0, r3
800050c: f002 fea2 bl 8003254 <HAL_I2CEx_ConfigAnalogFilter>
8000510: 1e03 subs r3, r0, #0
8000512: d001 beq.n 8000518 <MX_I2C1_Init+0x5c>
{
Error_Handler();
8000514: f000 fc2c bl 8000d70 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
8000518: 4b05 ldr r3, [pc, #20] @ (8000530 <MX_I2C1_Init+0x74>)
800051a: 2100 movs r1, #0
800051c: 0018 movs r0, r3
800051e: f002 fee5 bl 80032ec <HAL_I2CEx_ConfigDigitalFilter>
8000522: 1e03 subs r3, r0, #0
8000524: d001 beq.n 800052a <MX_I2C1_Init+0x6e>
{
Error_Handler();
8000526: f000 fc23 bl 8000d70 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
800052a: 46c0 nop @ (mov r8, r8)
800052c: 46bd mov sp, r7
800052e: bd80 pop {r7, pc}
8000530: 20000030 .word 0x20000030
8000534: 40005400 .word 0x40005400
8000538: 00303d5b .word 0x00303d5b
0800053c <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
800053c: b580 push {r7, lr}
800053e: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000540: 4b23 ldr r3, [pc, #140] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000542: 4a24 ldr r2, [pc, #144] @ (80005d4 <MX_USART2_UART_Init+0x98>)
8000544: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000546: 4b22 ldr r3, [pc, #136] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000548: 22e1 movs r2, #225 @ 0xe1
800054a: 0252 lsls r2, r2, #9
800054c: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800054e: 4b20 ldr r3, [pc, #128] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000550: 2200 movs r2, #0
8000552: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000554: 4b1e ldr r3, [pc, #120] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000556: 2200 movs r2, #0
8000558: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
800055a: 4b1d ldr r3, [pc, #116] @ (80005d0 <MX_USART2_UART_Init+0x94>)
800055c: 2200 movs r2, #0
800055e: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000560: 4b1b ldr r3, [pc, #108] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000562: 220c movs r2, #12
8000564: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000566: 4b1a ldr r3, [pc, #104] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000568: 2200 movs r2, #0
800056a: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
800056c: 4b18 ldr r3, [pc, #96] @ (80005d0 <MX_USART2_UART_Init+0x94>)
800056e: 2200 movs r2, #0
8000570: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8000572: 4b17 ldr r3, [pc, #92] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000574: 2200 movs r2, #0
8000576: 621a str r2, [r3, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8000578: 4b15 ldr r3, [pc, #84] @ (80005d0 <MX_USART2_UART_Init+0x94>)
800057a: 2200 movs r2, #0
800057c: 625a str r2, [r3, #36] @ 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
800057e: 4b14 ldr r3, [pc, #80] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000580: 2200 movs r2, #0
8000582: 629a str r2, [r3, #40] @ 0x28
if (HAL_UART_Init(&huart2) != HAL_OK)
8000584: 4b12 ldr r3, [pc, #72] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000586: 0018 movs r0, r3
8000588: f003 fd36 bl 8003ff8 <HAL_UART_Init>
800058c: 1e03 subs r3, r0, #0
800058e: d001 beq.n 8000594 <MX_USART2_UART_Init+0x58>
{
Error_Handler();
8000590: f000 fbee bl 8000d70 <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8000594: 4b0e ldr r3, [pc, #56] @ (80005d0 <MX_USART2_UART_Init+0x94>)
8000596: 2100 movs r1, #0
8000598: 0018 movs r0, r3
800059a: f004 f995 bl 80048c8 <HAL_UARTEx_SetTxFifoThreshold>
800059e: 1e03 subs r3, r0, #0
80005a0: d001 beq.n 80005a6 <MX_USART2_UART_Init+0x6a>
{
Error_Handler();
80005a2: f000 fbe5 bl 8000d70 <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
80005a6: 4b0a ldr r3, [pc, #40] @ (80005d0 <MX_USART2_UART_Init+0x94>)
80005a8: 2100 movs r1, #0
80005aa: 0018 movs r0, r3
80005ac: f004 f9cc bl 8004948 <HAL_UARTEx_SetRxFifoThreshold>
80005b0: 1e03 subs r3, r0, #0
80005b2: d001 beq.n 80005b8 <MX_USART2_UART_Init+0x7c>
{
Error_Handler();
80005b4: f000 fbdc bl 8000d70 <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
80005b8: 4b05 ldr r3, [pc, #20] @ (80005d0 <MX_USART2_UART_Init+0x94>)
80005ba: 0018 movs r0, r3
80005bc: f004 f94a bl 8004854 <HAL_UARTEx_DisableFifoMode>
80005c0: 1e03 subs r3, r0, #0
80005c2: d001 beq.n 80005c8 <MX_USART2_UART_Init+0x8c>
{
Error_Handler();
80005c4: f000 fbd4 bl 8000d70 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
80005c8: 46c0 nop @ (mov r8, r8)
80005ca: 46bd mov sp, r7
80005cc: bd80 pop {r7, pc}
80005ce: 46c0 nop @ (mov r8, r8)
80005d0: 20000084 .word 0x20000084
80005d4: 40004400 .word 0x40004400
080005d8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80005d8: b590 push {r4, r7, lr}
80005da: b089 sub sp, #36 @ 0x24
80005dc: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80005de: 240c movs r4, #12
80005e0: 193b adds r3, r7, r4
80005e2: 0018 movs r0, r3
80005e4: 2314 movs r3, #20
80005e6: 001a movs r2, r3
80005e8: 2100 movs r1, #0
80005ea: f004 fa4d bl 8004a88 <memset>
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80005ee: 4b3e ldr r3, [pc, #248] @ (80006e8 <MX_GPIO_Init+0x110>)
80005f0: 6b5a ldr r2, [r3, #52] @ 0x34
80005f2: 4b3d ldr r3, [pc, #244] @ (80006e8 <MX_GPIO_Init+0x110>)
80005f4: 2120 movs r1, #32
80005f6: 430a orrs r2, r1
80005f8: 635a str r2, [r3, #52] @ 0x34
80005fa: 4b3b ldr r3, [pc, #236] @ (80006e8 <MX_GPIO_Init+0x110>)
80005fc: 6b5b ldr r3, [r3, #52] @ 0x34
80005fe: 2220 movs r2, #32
8000600: 4013 ands r3, r2
8000602: 60bb str r3, [r7, #8]
8000604: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000606: 4b38 ldr r3, [pc, #224] @ (80006e8 <MX_GPIO_Init+0x110>)
8000608: 6b5a ldr r2, [r3, #52] @ 0x34
800060a: 4b37 ldr r3, [pc, #220] @ (80006e8 <MX_GPIO_Init+0x110>)
800060c: 2101 movs r1, #1
800060e: 430a orrs r2, r1
8000610: 635a str r2, [r3, #52] @ 0x34
8000612: 4b35 ldr r3, [pc, #212] @ (80006e8 <MX_GPIO_Init+0x110>)
8000614: 6b5b ldr r3, [r3, #52] @ 0x34
8000616: 2201 movs r2, #1
8000618: 4013 ands r3, r2
800061a: 607b str r3, [r7, #4]
800061c: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
800061e: 4b32 ldr r3, [pc, #200] @ (80006e8 <MX_GPIO_Init+0x110>)
8000620: 6b5a ldr r2, [r3, #52] @ 0x34
8000622: 4b31 ldr r3, [pc, #196] @ (80006e8 <MX_GPIO_Init+0x110>)
8000624: 2102 movs r1, #2
8000626: 430a orrs r2, r1
8000628: 635a str r2, [r3, #52] @ 0x34
800062a: 4b2f ldr r3, [pc, #188] @ (80006e8 <MX_GPIO_Init+0x110>)
800062c: 6b5b ldr r3, [r3, #52] @ 0x34
800062e: 2202 movs r2, #2
8000630: 4013 ands r3, r2
8000632: 603b str r3, [r7, #0]
8000634: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, LED3_Pin|HELP_BTN_Pin|INT_Pin, GPIO_PIN_RESET);
8000636: 492d ldr r1, [pc, #180] @ (80006ec <MX_GPIO_Init+0x114>)
8000638: 23a0 movs r3, #160 @ 0xa0
800063a: 05db lsls r3, r3, #23
800063c: 2200 movs r2, #0
800063e: 0018 movs r0, r3
8000640: f001 f861 bl 8001706 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, BUZZ_Pin|LED4_Pin|RELAY_Pin|LED1_Pin
8000644: 23e3 movs r3, #227 @ 0xe3
8000646: 021b lsls r3, r3, #8
8000648: 4829 ldr r0, [pc, #164] @ (80006f0 <MX_GPIO_Init+0x118>)
800064a: 2200 movs r2, #0
800064c: 0019 movs r1, r3
800064e: f001 f85a bl 8001706 <HAL_GPIO_WritePin>
|LED2_Pin, GPIO_PIN_RESET);
/*Configure GPIO pins : LED3_Pin HELP_BTN_Pin INT_Pin */
GPIO_InitStruct.Pin = LED3_Pin|HELP_BTN_Pin|INT_Pin;
8000652: 193b adds r3, r7, r4
8000654: 4a25 ldr r2, [pc, #148] @ (80006ec <MX_GPIO_Init+0x114>)
8000656: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000658: 193b adds r3, r7, r4
800065a: 2201 movs r2, #1
800065c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800065e: 193b adds r3, r7, r4
8000660: 2200 movs r2, #0
8000662: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000664: 193b adds r3, r7, r4
8000666: 2200 movs r2, #0
8000668: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800066a: 193a adds r2, r7, r4
800066c: 23a0 movs r3, #160 @ 0xa0
800066e: 05db lsls r3, r3, #23
8000670: 0011 movs r1, r2
8000672: 0018 movs r0, r3
8000674: f000 fec6 bl 8001404 <HAL_GPIO_Init>
/*Configure GPIO pins : WIRE8_Pin WIRE7_Pin WIRE6_Pin WIRE5_Pin */
GPIO_InitStruct.Pin = WIRE8_Pin|WIRE7_Pin|WIRE6_Pin|WIRE5_Pin;
8000678: 193b adds r3, r7, r4
800067a: 22f0 movs r2, #240 @ 0xf0
800067c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800067e: 193b adds r3, r7, r4
8000680: 2200 movs r2, #0
8000682: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000684: 193b adds r3, r7, r4
8000686: 2201 movs r2, #1
8000688: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800068a: 193a adds r2, r7, r4
800068c: 23a0 movs r3, #160 @ 0xa0
800068e: 05db lsls r3, r3, #23
8000690: 0011 movs r1, r2
8000692: 0018 movs r0, r3
8000694: f000 feb6 bl 8001404 <HAL_GPIO_Init>
/*Configure GPIO pins : WIRE4_Pin WIRE3_Pin WIRE2_Pin WIRE1_Pin */
GPIO_InitStruct.Pin = WIRE4_Pin|WIRE3_Pin|WIRE2_Pin|WIRE1_Pin;
8000698: 193b adds r3, r7, r4
800069a: 4a16 ldr r2, [pc, #88] @ (80006f4 <MX_GPIO_Init+0x11c>)
800069c: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
800069e: 193b adds r3, r7, r4
80006a0: 2200 movs r2, #0
80006a2: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
80006a4: 193b adds r3, r7, r4
80006a6: 2201 movs r2, #1
80006a8: 609a str r2, [r3, #8]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006aa: 193b adds r3, r7, r4
80006ac: 4a10 ldr r2, [pc, #64] @ (80006f0 <MX_GPIO_Init+0x118>)
80006ae: 0019 movs r1, r3
80006b0: 0010 movs r0, r2
80006b2: f000 fea7 bl 8001404 <HAL_GPIO_Init>
/*Configure GPIO pins : BUZZ_Pin LED4_Pin RELAY_Pin LED1_Pin
LED2_Pin */
GPIO_InitStruct.Pin = BUZZ_Pin|LED4_Pin|RELAY_Pin|LED1_Pin
80006b6: 0021 movs r1, r4
80006b8: 187b adds r3, r7, r1
80006ba: 22e3 movs r2, #227 @ 0xe3
80006bc: 0212 lsls r2, r2, #8
80006be: 601a str r2, [r3, #0]
|LED2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80006c0: 187b adds r3, r7, r1
80006c2: 2201 movs r2, #1
80006c4: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80006c6: 187b adds r3, r7, r1
80006c8: 2200 movs r2, #0
80006ca: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80006cc: 187b adds r3, r7, r1
80006ce: 2200 movs r2, #0
80006d0: 60da str r2, [r3, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006d2: 187b adds r3, r7, r1
80006d4: 4a06 ldr r2, [pc, #24] @ (80006f0 <MX_GPIO_Init+0x118>)
80006d6: 0019 movs r1, r3
80006d8: 0010 movs r0, r2
80006da: f000 fe93 bl 8001404 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80006de: 46c0 nop @ (mov r8, r8)
80006e0: 46bd mov sp, r7
80006e2: b009 add sp, #36 @ 0x24
80006e4: bd90 pop {r4, r7, pc}
80006e6: 46c0 nop @ (mov r8, r8)
80006e8: 40021000 .word 0x40021000
80006ec: 00000501 .word 0x00000501
80006f0: 50000400 .word 0x50000400
80006f4: 00000407 .word 0x00000407
080006f8 <HAL_I2C_ListenCpltCallback>:
return ch;
}
bool has_received_data;
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
{
80006f8: b580 push {r7, lr}
80006fa: b082 sub sp, #8
80006fc: af00 add r7, sp, #0
80006fe: 6078 str r0, [r7, #4]
i2c_register = 0;
8000700: 4b06 ldr r3, [pc, #24] @ (800071c <HAL_I2C_ListenCpltCallback+0x24>)
8000702: 2200 movs r2, #0
8000704: 701a strb r2, [r3, #0]
has_received_data = false;
8000706: 4b06 ldr r3, [pc, #24] @ (8000720 <HAL_I2C_ListenCpltCallback+0x28>)
8000708: 2200 movs r2, #0
800070a: 701a strb r2, [r3, #0]
HAL_I2C_EnableListen_IT(hi2c);
800070c: 687b ldr r3, [r7, #4]
800070e: 0018 movs r0, r3
8000710: f001 fa3e bl 8001b90 <HAL_I2C_EnableListen_IT>
}
8000714: 46c0 nop @ (mov r8, r8)
8000716: 46bd mov sp, r7
8000718: b002 add sp, #8
800071a: bd80 pop {r7, pc}
800071c: 2000002c .word 0x2000002c
8000720: 20000128 .word 0x20000128
08000724 <HAL_I2C_AddrCallback>:
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) {
8000724: b580 push {r7, lr}
8000726: b082 sub sp, #8
8000728: af00 add r7, sp, #0
800072a: 6078 str r0, [r7, #4]
800072c: 0008 movs r0, r1
800072e: 0011 movs r1, r2
8000730: 1cfb adds r3, r7, #3
8000732: 1c02 adds r2, r0, #0
8000734: 701a strb r2, [r3, #0]
8000736: 003b movs r3, r7
8000738: 1c0a adds r2, r1, #0
800073a: 801a strh r2, [r3, #0]
if (TransferDirection == I2C_DIRECTION_TRANSMIT) {
800073c: 1cfb adds r3, r7, #3
800073e: 781b ldrb r3, [r3, #0]
8000740: 2b00 cmp r3, #0
8000742: d107 bne.n 8000754 <HAL_I2C_AddrCallback+0x30>
HAL_I2C_Slave_Seq_Receive_IT(hi2c, &i2c_register, 1, I2C_NEXT_FRAME);
8000744: 2380 movs r3, #128 @ 0x80
8000746: 045b lsls r3, r3, #17
8000748: 4905 ldr r1, [pc, #20] @ (8000760 <HAL_I2C_AddrCallback+0x3c>)
800074a: 6878 ldr r0, [r7, #4]
800074c: 2201 movs r2, #1
800074e: f001 f95d bl 8001a0c <HAL_I2C_Slave_Seq_Receive_IT>
} else {
send_register();
}
}
8000752: e001 b.n 8000758 <HAL_I2C_AddrCallback+0x34>
send_register();
8000754: f000 f806 bl 8000764 <send_register>
}
8000758: 46c0 nop @ (mov r8, r8)
800075a: 46bd mov sp, r7
800075c: b002 add sp, #8
800075e: bd80 pop {r7, pc}
8000760: 2000002c .word 0x2000002c
08000764 <send_register>:
uint8_t send_data[2];
void send_register(void) {
8000764: b580 push {r7, lr}
8000766: af00 add r7, sp, #0
switch (i2c_register) {
8000768: 4b35 ldr r3, [pc, #212] @ (8000840 <send_register+0xdc>)
800076a: 781b ldrb r3, [r3, #0]
800076c: 2b08 cmp r3, #8
800076e: d862 bhi.n 8000836 <send_register+0xd2>
8000770: 009a lsls r2, r3, #2
8000772: 4b34 ldr r3, [pc, #208] @ (8000844 <send_register+0xe0>)
8000774: 18d3 adds r3, r2, r3
8000776: 681b ldr r3, [r3, #0]
8000778: 469f mov pc, r3
case I2C_REGISTER_DELTA:
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &delta, 1, I2C_NEXT_FRAME);
800077a: 2380 movs r3, #128 @ 0x80
800077c: 045b lsls r3, r3, #17
800077e: 4932 ldr r1, [pc, #200] @ (8000848 <send_register+0xe4>)
8000780: 4832 ldr r0, [pc, #200] @ (800084c <send_register+0xe8>)
8000782: 2201 movs r2, #1
8000784: f001 f882 bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
break;
8000788: e056 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_WIRES:
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &wires, 1, I2C_NEXT_FRAME);
800078a: 2380 movs r3, #128 @ 0x80
800078c: 045b lsls r3, r3, #17
800078e: 4930 ldr r1, [pc, #192] @ (8000850 <send_register+0xec>)
8000790: 482e ldr r0, [pc, #184] @ (800084c <send_register+0xe8>)
8000792: 2201 movs r2, #1
8000794: f001 f87a bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
delta &= ~(1 << DELTA_BIT_WIRES);
8000798: 4b2b ldr r3, [pc, #172] @ (8000848 <send_register+0xe4>)
800079a: 781b ldrb r3, [r3, #0]
800079c: 2201 movs r2, #1
800079e: 4393 bics r3, r2
80007a0: b2da uxtb r2, r3
80007a2: 4b29 ldr r3, [pc, #164] @ (8000848 <send_register+0xe4>)
80007a4: 701a strb r2, [r3, #0]
break;
80007a6: e047 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_BUTTON:
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &button, 1, I2C_NEXT_FRAME);
80007a8: 2380 movs r3, #128 @ 0x80
80007aa: 045b lsls r3, r3, #17
80007ac: 4929 ldr r1, [pc, #164] @ (8000854 <send_register+0xf0>)
80007ae: 4827 ldr r0, [pc, #156] @ (800084c <send_register+0xe8>)
80007b0: 2201 movs r2, #1
80007b2: f001 f86b bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
delta &= ~(1 << DELTA_BIT_BUTTON);
80007b6: 4b24 ldr r3, [pc, #144] @ (8000848 <send_register+0xe4>)
80007b8: 781b ldrb r3, [r3, #0]
80007ba: 2202 movs r2, #2
80007bc: 4393 bics r3, r2
80007be: b2da uxtb r2, r3
80007c0: 4b21 ldr r3, [pc, #132] @ (8000848 <send_register+0xe4>)
80007c2: 701a strb r2, [r3, #0]
break;
80007c4: e038 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_RELAY_BUZZ:
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &relay_buzz, 1, I2C_NEXT_FRAME);
80007c6: 2380 movs r3, #128 @ 0x80
80007c8: 045b lsls r3, r3, #17
80007ca: 4923 ldr r1, [pc, #140] @ (8000858 <send_register+0xf4>)
80007cc: 481f ldr r0, [pc, #124] @ (800084c <send_register+0xe8>)
80007ce: 2201 movs r2, #1
80007d0: f001 f85c bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
break;
80007d4: e030 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_LED:
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, &leds, 1, I2C_NEXT_FRAME);
80007d6: 2380 movs r3, #128 @ 0x80
80007d8: 045b lsls r3, r3, #17
80007da: 4920 ldr r1, [pc, #128] @ (800085c <send_register+0xf8>)
80007dc: 481b ldr r0, [pc, #108] @ (800084c <send_register+0xe8>)
80007de: 2201 movs r2, #1
80007e0: f001 f854 bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
break;
80007e4: e028 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_STRIKE_BUZZ_LEN:
send_data[0] = strike_buzz_len & 0xFF;
80007e6: 4b1e ldr r3, [pc, #120] @ (8000860 <send_register+0xfc>)
80007e8: 881b ldrh r3, [r3, #0]
80007ea: b2da uxtb r2, r3
80007ec: 4b1d ldr r3, [pc, #116] @ (8000864 <send_register+0x100>)
80007ee: 701a strb r2, [r3, #0]
send_data[1] = strike_buzz_len >> 8;
80007f0: 4b1b ldr r3, [pc, #108] @ (8000860 <send_register+0xfc>)
80007f2: 881b ldrh r3, [r3, #0]
80007f4: 0a1b lsrs r3, r3, #8
80007f6: b29b uxth r3, r3
80007f8: b2da uxtb r2, r3
80007fa: 4b1a ldr r3, [pc, #104] @ (8000864 <send_register+0x100>)
80007fc: 705a strb r2, [r3, #1]
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, send_data, 2, I2C_NEXT_FRAME);
80007fe: 2380 movs r3, #128 @ 0x80
8000800: 045b lsls r3, r3, #17
8000802: 4918 ldr r1, [pc, #96] @ (8000864 <send_register+0x100>)
8000804: 4811 ldr r0, [pc, #68] @ (800084c <send_register+0xe8>)
8000806: 2202 movs r2, #2
8000808: f001 f840 bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
break;
800080c: e014 b.n 8000838 <send_register+0xd4>
case I2C_REGISTER_STRIKE_RELAY_LEN:
send_data[0] = strike_relay_len & 0xFF;
800080e: 4b16 ldr r3, [pc, #88] @ (8000868 <send_register+0x104>)
8000810: 881b ldrh r3, [r3, #0]
8000812: b2da uxtb r2, r3
8000814: 4b13 ldr r3, [pc, #76] @ (8000864 <send_register+0x100>)
8000816: 701a strb r2, [r3, #0]
send_data[1] = strike_relay_len >> 8;
8000818: 4b13 ldr r3, [pc, #76] @ (8000868 <send_register+0x104>)
800081a: 881b ldrh r3, [r3, #0]
800081c: 0a1b lsrs r3, r3, #8
800081e: b29b uxth r3, r3
8000820: b2da uxtb r2, r3
8000822: 4b10 ldr r3, [pc, #64] @ (8000864 <send_register+0x100>)
8000824: 705a strb r2, [r3, #1]
HAL_I2C_Slave_Seq_Transmit_IT(&hi2c1, send_data, 2, I2C_NEXT_FRAME);
8000826: 2380 movs r3, #128 @ 0x80
8000828: 045b lsls r3, r3, #17
800082a: 490e ldr r1, [pc, #56] @ (8000864 <send_register+0x100>)
800082c: 4807 ldr r0, [pc, #28] @ (800084c <send_register+0xe8>)
800082e: 2202 movs r2, #2
8000830: f001 f82c bl 800188c <HAL_I2C_Slave_Seq_Transmit_IT>
break;
8000834: e000 b.n 8000838 <send_register+0xd4>
default:
break;
8000836: 46c0 nop @ (mov r8, r8)
}
}
8000838: 46c0 nop @ (mov r8, r8)
800083a: 46bd mov sp, r7
800083c: bd80 pop {r7, pc}
800083e: 46c0 nop @ (mov r8, r8)
8000840: 2000002c .word 0x2000002c
8000844: 08004af8 .word 0x08004af8
8000848: 20000119 .word 0x20000119
800084c: 20000030 .word 0x20000030
8000850: 2000011b .word 0x2000011b
8000854: 2000011d .word 0x2000011d
8000858: 2000011f .word 0x2000011f
800085c: 20000121 .word 0x20000121
8000860: 20000000 .word 0x20000000
8000864: 2000012c .word 0x2000012c
8000868: 20000002 .word 0x20000002
0800086c <recv_register>:
uint8_t recv_data[2];
void recv_register(void) {
800086c: b580 push {r7, lr}
800086e: af00 add r7, sp, #0
switch (i2c_register) {
8000870: 4b19 ldr r3, [pc, #100] @ (80008d8 <recv_register+0x6c>)
8000872: 781b ldrb r3, [r3, #0]
8000874: 2b08 cmp r3, #8
8000876: d020 beq.n 80008ba <recv_register+0x4e>
8000878: dc27 bgt.n 80008ca <recv_register+0x5e>
800087a: 2b07 cmp r3, #7
800087c: d015 beq.n 80008aa <recv_register+0x3e>
800087e: dc24 bgt.n 80008ca <recv_register+0x5e>
8000880: 2b04 cmp r3, #4
8000882: d002 beq.n 800088a <recv_register+0x1e>
8000884: 2b05 cmp r3, #5
8000886: d008 beq.n 800089a <recv_register+0x2e>
break;
case I2C_REGISTER_STRIKE_RELAY_LEN:
HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME);
break;
default:
break;
8000888: e01f b.n 80008ca <recv_register+0x5e>
HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, &relay_buzz, 1, I2C_NEXT_FRAME);
800088a: 2380 movs r3, #128 @ 0x80
800088c: 045b lsls r3, r3, #17
800088e: 4913 ldr r1, [pc, #76] @ (80008dc <recv_register+0x70>)
8000890: 4813 ldr r0, [pc, #76] @ (80008e0 <recv_register+0x74>)
8000892: 2201 movs r2, #1
8000894: f001 f8ba bl 8001a0c <HAL_I2C_Slave_Seq_Receive_IT>
break;
8000898: e018 b.n 80008cc <recv_register+0x60>
HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, &leds, 1, I2C_NEXT_FRAME);
800089a: 2380 movs r3, #128 @ 0x80
800089c: 045b lsls r3, r3, #17
800089e: 4911 ldr r1, [pc, #68] @ (80008e4 <recv_register+0x78>)
80008a0: 480f ldr r0, [pc, #60] @ (80008e0 <recv_register+0x74>)
80008a2: 2201 movs r2, #1
80008a4: f001 f8b2 bl 8001a0c <HAL_I2C_Slave_Seq_Receive_IT>
break;
80008a8: e010 b.n 80008cc <recv_register+0x60>
HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME);
80008aa: 2380 movs r3, #128 @ 0x80
80008ac: 045b lsls r3, r3, #17
80008ae: 490e ldr r1, [pc, #56] @ (80008e8 <recv_register+0x7c>)
80008b0: 480b ldr r0, [pc, #44] @ (80008e0 <recv_register+0x74>)
80008b2: 2202 movs r2, #2
80008b4: f001 f8aa bl 8001a0c <HAL_I2C_Slave_Seq_Receive_IT>
break;
80008b8: e008 b.n 80008cc <recv_register+0x60>
HAL_I2C_Slave_Seq_Receive_IT(&hi2c1, recv_data, 2, I2C_NEXT_FRAME);
80008ba: 2380 movs r3, #128 @ 0x80
80008bc: 045b lsls r3, r3, #17
80008be: 490a ldr r1, [pc, #40] @ (80008e8 <recv_register+0x7c>)
80008c0: 4807 ldr r0, [pc, #28] @ (80008e0 <recv_register+0x74>)
80008c2: 2202 movs r2, #2
80008c4: f001 f8a2 bl 8001a0c <HAL_I2C_Slave_Seq_Receive_IT>
break;
80008c8: e000 b.n 80008cc <recv_register+0x60>
break;
80008ca: 46c0 nop @ (mov r8, r8)
}
has_received_data = true;
80008cc: 4b07 ldr r3, [pc, #28] @ (80008ec <recv_register+0x80>)
80008ce: 2201 movs r2, #1
80008d0: 701a strb r2, [r3, #0]
}
80008d2: 46c0 nop @ (mov r8, r8)
80008d4: 46bd mov sp, r7
80008d6: bd80 pop {r7, pc}
80008d8: 2000002c .word 0x2000002c
80008dc: 2000011f .word 0x2000011f
80008e0: 20000030 .word 0x20000030
80008e4: 20000121 .word 0x20000121
80008e8: 20000130 .word 0x20000130
80008ec: 20000128 .word 0x20000128
080008f0 <HAL_I2C_SlaveRxCpltCallback>:
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
80008f0: b580 push {r7, lr}
80008f2: b082 sub sp, #8
80008f4: af00 add r7, sp, #0
80008f6: 6078 str r0, [r7, #4]
if (i2c_register == I2C_REGISTER_ISSUE_STRIKE) {
80008f8: 4b1f ldr r3, [pc, #124] @ (8000978 <HAL_I2C_SlaveRxCpltCallback+0x88>)
80008fa: 781b ldrb r3, [r3, #0]
80008fc: 2b06 cmp r3, #6
80008fe: d102 bne.n 8000906 <HAL_I2C_SlaveRxCpltCallback+0x16>
strike_issued = true;
8000900: 4b1e ldr r3, [pc, #120] @ (800097c <HAL_I2C_SlaveRxCpltCallback+0x8c>)
8000902: 2201 movs r2, #1
8000904: 701a strb r2, [r3, #0]
}
if (has_received_data) {
8000906: 4b1e ldr r3, [pc, #120] @ (8000980 <HAL_I2C_SlaveRxCpltCallback+0x90>)
8000908: 781b ldrb r3, [r3, #0]
800090a: 2b00 cmp r3, #0
800090c: d02d beq.n 800096a <HAL_I2C_SlaveRxCpltCallback+0x7a>
has_received_data = false;
800090e: 4b1c ldr r3, [pc, #112] @ (8000980 <HAL_I2C_SlaveRxCpltCallback+0x90>)
8000910: 2200 movs r2, #0
8000912: 701a strb r2, [r3, #0]
// reconstruct anything that needs to be reconstructed
switch (i2c_register) {
8000914: 4b18 ldr r3, [pc, #96] @ (8000978 <HAL_I2C_SlaveRxCpltCallback+0x88>)
8000916: 781b ldrb r3, [r3, #0]
8000918: 2b07 cmp r3, #7
800091a: d002 beq.n 8000922 <HAL_I2C_SlaveRxCpltCallback+0x32>
800091c: 2b08 cmp r3, #8
800091e: d012 beq.n 8000946 <HAL_I2C_SlaveRxCpltCallback+0x56>
case I2C_REGISTER_STRIKE_RELAY_LEN:
strike_relay_len = recv_data[0];
strike_relay_len |= ((uint16_t) recv_data[1]) << 8;
break;
default:
break;
8000920: e026 b.n 8000970 <HAL_I2C_SlaveRxCpltCallback+0x80>
strike_buzz_len = recv_data[0];
8000922: 4b18 ldr r3, [pc, #96] @ (8000984 <HAL_I2C_SlaveRxCpltCallback+0x94>)
8000924: 781b ldrb r3, [r3, #0]
8000926: 001a movs r2, r3
8000928: 4b17 ldr r3, [pc, #92] @ (8000988 <HAL_I2C_SlaveRxCpltCallback+0x98>)
800092a: 801a strh r2, [r3, #0]
strike_buzz_len |= ((uint16_t) recv_data[1]) << 8;
800092c: 4b15 ldr r3, [pc, #84] @ (8000984 <HAL_I2C_SlaveRxCpltCallback+0x94>)
800092e: 785b ldrb r3, [r3, #1]
8000930: 021b lsls r3, r3, #8
8000932: b21a sxth r2, r3
8000934: 4b14 ldr r3, [pc, #80] @ (8000988 <HAL_I2C_SlaveRxCpltCallback+0x98>)
8000936: 881b ldrh r3, [r3, #0]
8000938: b21b sxth r3, r3
800093a: 4313 orrs r3, r2
800093c: b21b sxth r3, r3
800093e: b29a uxth r2, r3
8000940: 4b11 ldr r3, [pc, #68] @ (8000988 <HAL_I2C_SlaveRxCpltCallback+0x98>)
8000942: 801a strh r2, [r3, #0]
break;
8000944: e014 b.n 8000970 <HAL_I2C_SlaveRxCpltCallback+0x80>
strike_relay_len = recv_data[0];
8000946: 4b0f ldr r3, [pc, #60] @ (8000984 <HAL_I2C_SlaveRxCpltCallback+0x94>)
8000948: 781b ldrb r3, [r3, #0]
800094a: 001a movs r2, r3
800094c: 4b0f ldr r3, [pc, #60] @ (800098c <HAL_I2C_SlaveRxCpltCallback+0x9c>)
800094e: 801a strh r2, [r3, #0]
strike_relay_len |= ((uint16_t) recv_data[1]) << 8;
8000950: 4b0c ldr r3, [pc, #48] @ (8000984 <HAL_I2C_SlaveRxCpltCallback+0x94>)
8000952: 785b ldrb r3, [r3, #1]
8000954: 021b lsls r3, r3, #8
8000956: b21a sxth r2, r3
8000958: 4b0c ldr r3, [pc, #48] @ (800098c <HAL_I2C_SlaveRxCpltCallback+0x9c>)
800095a: 881b ldrh r3, [r3, #0]
800095c: b21b sxth r3, r3
800095e: 4313 orrs r3, r2
8000960: b21b sxth r3, r3
8000962: b29a uxth r2, r3
8000964: 4b09 ldr r3, [pc, #36] @ (800098c <HAL_I2C_SlaveRxCpltCallback+0x9c>)
8000966: 801a strh r2, [r3, #0]
break;
8000968: e002 b.n 8000970 <HAL_I2C_SlaveRxCpltCallback+0x80>
}
} else {
recv_register();
800096a: f7ff ff7f bl 800086c <recv_register>
}
}
800096e: 46c0 nop @ (mov r8, r8)
8000970: 46c0 nop @ (mov r8, r8)
8000972: 46bd mov sp, r7
8000974: b002 add sp, #8
8000976: bd80 pop {r7, pc}
8000978: 2000002c .word 0x2000002c
800097c: 20000122 .word 0x20000122
8000980: 20000128 .word 0x20000128
8000984: 20000130 .word 0x20000130
8000988: 20000000 .word 0x20000000
800098c: 20000002 .word 0x20000002
08000990 <HAL_I2C_SlaveTxCpltCallback>:
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8000990: b580 push {r7, lr}
8000992: b082 sub sp, #8
8000994: af00 add r7, sp, #0
8000996: 6078 str r0, [r7, #4]
}
8000998: 46c0 nop @ (mov r8, r8)
800099a: 46bd mov sp, r7
800099c: b002 add sp, #8
800099e: bd80 pop {r7, pc}
080009a0 <scan_wires>:
void scan_wires(void)
{
80009a0: b580 push {r7, lr}
80009a2: b082 sub sp, #8
80009a4: af00 add r7, sp, #0
old_wires = wires;
80009a6: 4b58 ldr r3, [pc, #352] @ (8000b08 <scan_wires+0x168>)
80009a8: 781a ldrb r2, [r3, #0]
80009aa: 4b58 ldr r3, [pc, #352] @ (8000b0c <scan_wires+0x16c>)
80009ac: 701a strb r2, [r3, #0]
uint8_t new_wires = 0;
80009ae: 1dfb adds r3, r7, #7
80009b0: 2200 movs r2, #0
80009b2: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE1_GPIO_Port, WIRE1_Pin) == GPIO_PIN_RESET) << 0;
80009b4: 2380 movs r3, #128 @ 0x80
80009b6: 00db lsls r3, r3, #3
80009b8: 4a55 ldr r2, [pc, #340] @ (8000b10 <scan_wires+0x170>)
80009ba: 0019 movs r1, r3
80009bc: 0010 movs r0, r2
80009be: f000 fe85 bl 80016cc <HAL_GPIO_ReadPin>
80009c2: 0003 movs r3, r0
80009c4: 425a negs r2, r3
80009c6: 4153 adcs r3, r2
80009c8: b2db uxtb r3, r3
80009ca: b25a sxtb r2, r3
80009cc: 1dfb adds r3, r7, #7
80009ce: 781b ldrb r3, [r3, #0]
80009d0: b25b sxtb r3, r3
80009d2: 4313 orrs r3, r2
80009d4: b25a sxtb r2, r3
80009d6: 1dfb adds r3, r7, #7
80009d8: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE2_GPIO_Port, WIRE2_Pin) == GPIO_PIN_RESET) << 1;
80009da: 4b4d ldr r3, [pc, #308] @ (8000b10 <scan_wires+0x170>)
80009dc: 2104 movs r1, #4
80009de: 0018 movs r0, r3
80009e0: f000 fe74 bl 80016cc <HAL_GPIO_ReadPin>
80009e4: 1e03 subs r3, r0, #0
80009e6: d101 bne.n 80009ec <scan_wires+0x4c>
80009e8: 2302 movs r3, #2
80009ea: e000 b.n 80009ee <scan_wires+0x4e>
80009ec: 2300 movs r3, #0
80009ee: b25a sxtb r2, r3
80009f0: 1dfb adds r3, r7, #7
80009f2: 781b ldrb r3, [r3, #0]
80009f4: b25b sxtb r3, r3
80009f6: 4313 orrs r3, r2
80009f8: b25a sxtb r2, r3
80009fa: 1dfb adds r3, r7, #7
80009fc: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE3_GPIO_Port, WIRE3_Pin) == GPIO_PIN_RESET) << 2;
80009fe: 4b44 ldr r3, [pc, #272] @ (8000b10 <scan_wires+0x170>)
8000a00: 2102 movs r1, #2
8000a02: 0018 movs r0, r3
8000a04: f000 fe62 bl 80016cc <HAL_GPIO_ReadPin>
8000a08: 1e03 subs r3, r0, #0
8000a0a: d101 bne.n 8000a10 <scan_wires+0x70>
8000a0c: 2304 movs r3, #4
8000a0e: e000 b.n 8000a12 <scan_wires+0x72>
8000a10: 2300 movs r3, #0
8000a12: b25a sxtb r2, r3
8000a14: 1dfb adds r3, r7, #7
8000a16: 781b ldrb r3, [r3, #0]
8000a18: b25b sxtb r3, r3
8000a1a: 4313 orrs r3, r2
8000a1c: b25a sxtb r2, r3
8000a1e: 1dfb adds r3, r7, #7
8000a20: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE4_GPIO_Port, WIRE4_Pin) == GPIO_PIN_RESET) << 3;
8000a22: 4b3b ldr r3, [pc, #236] @ (8000b10 <scan_wires+0x170>)
8000a24: 2101 movs r1, #1
8000a26: 0018 movs r0, r3
8000a28: f000 fe50 bl 80016cc <HAL_GPIO_ReadPin>
8000a2c: 1e03 subs r3, r0, #0
8000a2e: d101 bne.n 8000a34 <scan_wires+0x94>
8000a30: 2308 movs r3, #8
8000a32: e000 b.n 8000a36 <scan_wires+0x96>
8000a34: 2300 movs r3, #0
8000a36: b25a sxtb r2, r3
8000a38: 1dfb adds r3, r7, #7
8000a3a: 781b ldrb r3, [r3, #0]
8000a3c: b25b sxtb r3, r3
8000a3e: 4313 orrs r3, r2
8000a40: b25a sxtb r2, r3
8000a42: 1dfb adds r3, r7, #7
8000a44: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE5_GPIO_Port, WIRE5_Pin) == GPIO_PIN_RESET) << 4;
8000a46: 23a0 movs r3, #160 @ 0xa0
8000a48: 05db lsls r3, r3, #23
8000a4a: 2180 movs r1, #128 @ 0x80
8000a4c: 0018 movs r0, r3
8000a4e: f000 fe3d bl 80016cc <HAL_GPIO_ReadPin>
8000a52: 1e03 subs r3, r0, #0
8000a54: d101 bne.n 8000a5a <scan_wires+0xba>
8000a56: 2310 movs r3, #16
8000a58: e000 b.n 8000a5c <scan_wires+0xbc>
8000a5a: 2300 movs r3, #0
8000a5c: b25a sxtb r2, r3
8000a5e: 1dfb adds r3, r7, #7
8000a60: 781b ldrb r3, [r3, #0]
8000a62: b25b sxtb r3, r3
8000a64: 4313 orrs r3, r2
8000a66: b25a sxtb r2, r3
8000a68: 1dfb adds r3, r7, #7
8000a6a: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE6_GPIO_Port, WIRE6_Pin) == GPIO_PIN_RESET) << 5;
8000a6c: 23a0 movs r3, #160 @ 0xa0
8000a6e: 05db lsls r3, r3, #23
8000a70: 2140 movs r1, #64 @ 0x40
8000a72: 0018 movs r0, r3
8000a74: f000 fe2a bl 80016cc <HAL_GPIO_ReadPin>
8000a78: 1e03 subs r3, r0, #0
8000a7a: d101 bne.n 8000a80 <scan_wires+0xe0>
8000a7c: 2320 movs r3, #32
8000a7e: e000 b.n 8000a82 <scan_wires+0xe2>
8000a80: 2300 movs r3, #0
8000a82: b25a sxtb r2, r3
8000a84: 1dfb adds r3, r7, #7
8000a86: 781b ldrb r3, [r3, #0]
8000a88: b25b sxtb r3, r3
8000a8a: 4313 orrs r3, r2
8000a8c: b25a sxtb r2, r3
8000a8e: 1dfb adds r3, r7, #7
8000a90: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE7_GPIO_Port, WIRE7_Pin) == GPIO_PIN_RESET) << 6;
8000a92: 23a0 movs r3, #160 @ 0xa0
8000a94: 05db lsls r3, r3, #23
8000a96: 2120 movs r1, #32
8000a98: 0018 movs r0, r3
8000a9a: f000 fe17 bl 80016cc <HAL_GPIO_ReadPin>
8000a9e: 1e03 subs r3, r0, #0
8000aa0: d101 bne.n 8000aa6 <scan_wires+0x106>
8000aa2: 2340 movs r3, #64 @ 0x40
8000aa4: e000 b.n 8000aa8 <scan_wires+0x108>
8000aa6: 2300 movs r3, #0
8000aa8: b25a sxtb r2, r3
8000aaa: 1dfb adds r3, r7, #7
8000aac: 781b ldrb r3, [r3, #0]
8000aae: b25b sxtb r3, r3
8000ab0: 4313 orrs r3, r2
8000ab2: b25a sxtb r2, r3
8000ab4: 1dfb adds r3, r7, #7
8000ab6: 701a strb r2, [r3, #0]
new_wires |= (HAL_GPIO_ReadPin(WIRE8_GPIO_Port, WIRE8_Pin) == GPIO_PIN_RESET) << 7;
8000ab8: 23a0 movs r3, #160 @ 0xa0
8000aba: 05db lsls r3, r3, #23
8000abc: 2110 movs r1, #16
8000abe: 0018 movs r0, r3
8000ac0: f000 fe04 bl 80016cc <HAL_GPIO_ReadPin>
8000ac4: 1e03 subs r3, r0, #0
8000ac6: d101 bne.n 8000acc <scan_wires+0x12c>
8000ac8: 2380 movs r3, #128 @ 0x80
8000aca: e000 b.n 8000ace <scan_wires+0x12e>
8000acc: 2300 movs r3, #0
8000ace: b25a sxtb r2, r3
8000ad0: 1dfb adds r3, r7, #7
8000ad2: 781b ldrb r3, [r3, #0]
8000ad4: b25b sxtb r3, r3
8000ad6: 4313 orrs r3, r2
8000ad8: b25a sxtb r2, r3
8000ada: 1dfb adds r3, r7, #7
8000adc: 701a strb r2, [r3, #0]
wires = new_wires;
8000ade: 4b0a ldr r3, [pc, #40] @ (8000b08 <scan_wires+0x168>)
8000ae0: 1dfa adds r2, r7, #7
8000ae2: 7812 ldrb r2, [r2, #0]
8000ae4: 701a strb r2, [r3, #0]
if (wires != old_wires) {
8000ae6: 4b08 ldr r3, [pc, #32] @ (8000b08 <scan_wires+0x168>)
8000ae8: 781a ldrb r2, [r3, #0]
8000aea: 4b08 ldr r3, [pc, #32] @ (8000b0c <scan_wires+0x16c>)
8000aec: 781b ldrb r3, [r3, #0]
8000aee: 429a cmp r2, r3
8000af0: d006 beq.n 8000b00 <scan_wires+0x160>
delta |= 1 << DELTA_BIT_WIRES;
8000af2: 4b08 ldr r3, [pc, #32] @ (8000b14 <scan_wires+0x174>)
8000af4: 781b ldrb r3, [r3, #0]
8000af6: 2201 movs r2, #1
8000af8: 4313 orrs r3, r2
8000afa: b2da uxtb r2, r3
8000afc: 4b05 ldr r3, [pc, #20] @ (8000b14 <scan_wires+0x174>)
8000afe: 701a strb r2, [r3, #0]
}
}
8000b00: 46c0 nop @ (mov r8, r8)
8000b02: 46bd mov sp, r7
8000b04: b002 add sp, #8
8000b06: bd80 pop {r7, pc}
8000b08: 2000011b .word 0x2000011b
8000b0c: 2000011a .word 0x2000011a
8000b10: 50000400 .word 0x50000400
8000b14: 20000119 .word 0x20000119
08000b18 <scan_button>:
void scan_button(void)
{
8000b18: b580 push {r7, lr}
8000b1a: af00 add r7, sp, #0
old_button = button;
8000b1c: 4b11 ldr r3, [pc, #68] @ (8000b64 <scan_button+0x4c>)
8000b1e: 781a ldrb r2, [r3, #0]
8000b20: 4b11 ldr r3, [pc, #68] @ (8000b68 <scan_button+0x50>)
8000b22: 701a strb r2, [r3, #0]
button = HAL_GPIO_ReadPin(HELP_BTN_GPIO_Port, HELP_BTN_Pin) == GPIO_PIN_RESET;
8000b24: 2380 movs r3, #128 @ 0x80
8000b26: 005a lsls r2, r3, #1
8000b28: 23a0 movs r3, #160 @ 0xa0
8000b2a: 05db lsls r3, r3, #23
8000b2c: 0011 movs r1, r2
8000b2e: 0018 movs r0, r3
8000b30: f000 fdcc bl 80016cc <HAL_GPIO_ReadPin>
8000b34: 0003 movs r3, r0
8000b36: 425a negs r2, r3
8000b38: 4153 adcs r3, r2
8000b3a: b2db uxtb r3, r3
8000b3c: 001a movs r2, r3
8000b3e: 4b09 ldr r3, [pc, #36] @ (8000b64 <scan_button+0x4c>)
8000b40: 701a strb r2, [r3, #0]
if (button != old_button) {
8000b42: 4b08 ldr r3, [pc, #32] @ (8000b64 <scan_button+0x4c>)
8000b44: 781a ldrb r2, [r3, #0]
8000b46: 4b08 ldr r3, [pc, #32] @ (8000b68 <scan_button+0x50>)
8000b48: 781b ldrb r3, [r3, #0]
8000b4a: 429a cmp r2, r3
8000b4c: d006 beq.n 8000b5c <scan_button+0x44>
delta |= 1 << DELTA_BIT_BUTTON;
8000b4e: 4b07 ldr r3, [pc, #28] @ (8000b6c <scan_button+0x54>)
8000b50: 781b ldrb r3, [r3, #0]
8000b52: 2202 movs r2, #2
8000b54: 4313 orrs r3, r2
8000b56: b2da uxtb r2, r3
8000b58: 4b04 ldr r3, [pc, #16] @ (8000b6c <scan_button+0x54>)
8000b5a: 701a strb r2, [r3, #0]
}
}
8000b5c: 46c0 nop @ (mov r8, r8)
8000b5e: 46bd mov sp, r7
8000b60: bd80 pop {r7, pc}
8000b62: 46c0 nop @ (mov r8, r8)
8000b64: 2000011d .word 0x2000011d
8000b68: 2000011c .word 0x2000011c
8000b6c: 20000119 .word 0x20000119
08000b70 <set_relay_buzz>:
void set_relay_buzz(void)
{
8000b70: b580 push {r7, lr}
8000b72: af00 add r7, sp, #0
if (relay_buzz != old_relay_buzz) {
8000b74: 4b12 ldr r3, [pc, #72] @ (8000bc0 <set_relay_buzz+0x50>)
8000b76: 781a ldrb r2, [r3, #0]
8000b78: 4b12 ldr r3, [pc, #72] @ (8000bc4 <set_relay_buzz+0x54>)
8000b7a: 781b ldrb r3, [r3, #0]
8000b7c: 429a cmp r2, r3
8000b7e: d01b beq.n 8000bb8 <set_relay_buzz+0x48>
old_relay_buzz = relay_buzz;
8000b80: 4b0f ldr r3, [pc, #60] @ (8000bc0 <set_relay_buzz+0x50>)
8000b82: 781a ldrb r2, [r3, #0]
8000b84: 4b0f ldr r3, [pc, #60] @ (8000bc4 <set_relay_buzz+0x54>)
8000b86: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(BUZZ_GPIO_Port, BUZZ_Pin, (relay_buzz >> BUZZ_BIT_IDX) & 1);
8000b88: 4b0d ldr r3, [pc, #52] @ (8000bc0 <set_relay_buzz+0x50>)
8000b8a: 781b ldrb r3, [r3, #0]
8000b8c: 2201 movs r2, #1
8000b8e: 4013 ands r3, r2
8000b90: b2da uxtb r2, r3
8000b92: 2380 movs r3, #128 @ 0x80
8000b94: 019b lsls r3, r3, #6
8000b96: 480c ldr r0, [pc, #48] @ (8000bc8 <set_relay_buzz+0x58>)
8000b98: 0019 movs r1, r3
8000b9a: f000 fdb4 bl 8001706 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(RELAY_GPIO_Port, RELAY_Pin, (relay_buzz >> RELAY_BIT_IDX) & 1);
8000b9e: 4b08 ldr r3, [pc, #32] @ (8000bc0 <set_relay_buzz+0x50>)
8000ba0: 781b ldrb r3, [r3, #0]
8000ba2: 085b lsrs r3, r3, #1
8000ba4: b2db uxtb r3, r3
8000ba6: 2201 movs r2, #1
8000ba8: 4013 ands r3, r2
8000baa: b2da uxtb r2, r3
8000bac: 2380 movs r3, #128 @ 0x80
8000bae: 021b lsls r3, r3, #8
8000bb0: 4805 ldr r0, [pc, #20] @ (8000bc8 <set_relay_buzz+0x58>)
8000bb2: 0019 movs r1, r3
8000bb4: f000 fda7 bl 8001706 <HAL_GPIO_WritePin>
}
}
8000bb8: 46c0 nop @ (mov r8, r8)
8000bba: 46bd mov sp, r7
8000bbc: bd80 pop {r7, pc}
8000bbe: 46c0 nop @ (mov r8, r8)
8000bc0: 2000011f .word 0x2000011f
8000bc4: 2000011e .word 0x2000011e
8000bc8: 50000400 .word 0x50000400
08000bcc <set_leds>:
void set_leds(void)
{
8000bcc: b580 push {r7, lr}
8000bce: af00 add r7, sp, #0
if (leds != old_leds) {
8000bd0: 4b1f ldr r3, [pc, #124] @ (8000c50 <set_leds+0x84>)
8000bd2: 781a ldrb r2, [r3, #0]
8000bd4: 4b1f ldr r3, [pc, #124] @ (8000c54 <set_leds+0x88>)
8000bd6: 781b ldrb r3, [r3, #0]
8000bd8: 429a cmp r2, r3
8000bda: d035 beq.n 8000c48 <set_leds+0x7c>
old_leds = leds;
8000bdc: 4b1c ldr r3, [pc, #112] @ (8000c50 <set_leds+0x84>)
8000bde: 781a ldrb r2, [r3, #0]
8000be0: 4b1c ldr r3, [pc, #112] @ (8000c54 <set_leds+0x88>)
8000be2: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, (leds >> 0) & 1);
8000be4: 4b1a ldr r3, [pc, #104] @ (8000c50 <set_leds+0x84>)
8000be6: 781b ldrb r3, [r3, #0]
8000be8: 2201 movs r2, #1
8000bea: 4013 ands r3, r2
8000bec: b2da uxtb r2, r3
8000bee: 2380 movs r3, #128 @ 0x80
8000bf0: 005b lsls r3, r3, #1
8000bf2: 4819 ldr r0, [pc, #100] @ (8000c58 <set_leds+0x8c>)
8000bf4: 0019 movs r1, r3
8000bf6: f000 fd86 bl 8001706 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED2_GPIO_Port, LED2_Pin, (leds >> 1) & 1);
8000bfa: 4b15 ldr r3, [pc, #84] @ (8000c50 <set_leds+0x84>)
8000bfc: 781b ldrb r3, [r3, #0]
8000bfe: 085b lsrs r3, r3, #1
8000c00: b2db uxtb r3, r3
8000c02: 2201 movs r2, #1
8000c04: 4013 ands r3, r2
8000c06: b2da uxtb r2, r3
8000c08: 2380 movs r3, #128 @ 0x80
8000c0a: 009b lsls r3, r3, #2
8000c0c: 4812 ldr r0, [pc, #72] @ (8000c58 <set_leds+0x8c>)
8000c0e: 0019 movs r1, r3
8000c10: f000 fd79 bl 8001706 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED3_GPIO_Port, LED3_Pin, (leds >> 2) & 1);
8000c14: 4b0e ldr r3, [pc, #56] @ (8000c50 <set_leds+0x84>)
8000c16: 781b ldrb r3, [r3, #0]
8000c18: 089b lsrs r3, r3, #2
8000c1a: b2db uxtb r3, r3
8000c1c: 2201 movs r2, #1
8000c1e: 4013 ands r3, r2
8000c20: b2da uxtb r2, r3
8000c22: 23a0 movs r3, #160 @ 0xa0
8000c24: 05db lsls r3, r3, #23
8000c26: 2101 movs r1, #1
8000c28: 0018 movs r0, r3
8000c2a: f000 fd6c bl 8001706 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED4_GPIO_Port, LED4_Pin, (leds >> 3) & 1);
8000c2e: 4b08 ldr r3, [pc, #32] @ (8000c50 <set_leds+0x84>)
8000c30: 781b ldrb r3, [r3, #0]
8000c32: 08db lsrs r3, r3, #3
8000c34: b2db uxtb r3, r3
8000c36: 2201 movs r2, #1
8000c38: 4013 ands r3, r2
8000c3a: b2da uxtb r2, r3
8000c3c: 2380 movs r3, #128 @ 0x80
8000c3e: 01db lsls r3, r3, #7
8000c40: 4805 ldr r0, [pc, #20] @ (8000c58 <set_leds+0x8c>)
8000c42: 0019 movs r1, r3
8000c44: f000 fd5f bl 8001706 <HAL_GPIO_WritePin>
}
}
8000c48: 46c0 nop @ (mov r8, r8)
8000c4a: 46bd mov sp, r7
8000c4c: bd80 pop {r7, pc}
8000c4e: 46c0 nop @ (mov r8, r8)
8000c50: 20000121 .word 0x20000121
8000c54: 20000120 .word 0x20000120
8000c58: 50000400 .word 0x50000400
08000c5c <send_interupt>:
void send_interupt(void)
{
8000c5c: b580 push {r7, lr}
8000c5e: af00 add r7, sp, #0
if (delta != old_delta) {
8000c60: 4b0c ldr r3, [pc, #48] @ (8000c94 <send_interupt+0x38>)
8000c62: 781a ldrb r2, [r3, #0]
8000c64: 4b0c ldr r3, [pc, #48] @ (8000c98 <send_interupt+0x3c>)
8000c66: 781b ldrb r3, [r3, #0]
8000c68: 429a cmp r2, r3
8000c6a: d010 beq.n 8000c8e <send_interupt+0x32>
old_delta = delta;
8000c6c: 4b09 ldr r3, [pc, #36] @ (8000c94 <send_interupt+0x38>)
8000c6e: 781a ldrb r2, [r3, #0]
8000c70: 4b09 ldr r3, [pc, #36] @ (8000c98 <send_interupt+0x3c>)
8000c72: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(INT_GPIO_Port, INT_Pin, delta == 0);
8000c74: 4b07 ldr r3, [pc, #28] @ (8000c94 <send_interupt+0x38>)
8000c76: 781b ldrb r3, [r3, #0]
8000c78: 425a negs r2, r3
8000c7a: 4153 adcs r3, r2
8000c7c: b2db uxtb r3, r3
8000c7e: 001a movs r2, r3
8000c80: 2380 movs r3, #128 @ 0x80
8000c82: 00d9 lsls r1, r3, #3
8000c84: 23a0 movs r3, #160 @ 0xa0
8000c86: 05db lsls r3, r3, #23
8000c88: 0018 movs r0, r3
8000c8a: f000 fd3c bl 8001706 <HAL_GPIO_WritePin>
}
}
8000c8e: 46c0 nop @ (mov r8, r8)
8000c90: 46bd mov sp, r7
8000c92: bd80 pop {r7, pc}
8000c94: 20000119 .word 0x20000119
8000c98: 20000118 .word 0x20000118
08000c9c <handle_strike>:
uint32_t old_tick;
void handle_strike(void) {
8000c9c: b580 push {r7, lr}
8000c9e: b084 sub sp, #16
8000ca0: af00 add r7, sp, #0
if (strike_issued && (strike_at == 0)) {
8000ca2: 4b2c ldr r3, [pc, #176] @ (8000d54 <handle_strike+0xb8>)
8000ca4: 781b ldrb r3, [r3, #0]
8000ca6: 2b00 cmp r3, #0
8000ca8: d019 beq.n 8000cde <handle_strike+0x42>
8000caa: 4b2b ldr r3, [pc, #172] @ (8000d58 <handle_strike+0xbc>)
8000cac: 681b ldr r3, [r3, #0]
8000cae: 2b00 cmp r3, #0
8000cb0: d115 bne.n 8000cde <handle_strike+0x42>
strike_issued = false;
8000cb2: 4b28 ldr r3, [pc, #160] @ (8000d54 <handle_strike+0xb8>)
8000cb4: 2200 movs r2, #0
8000cb6: 701a strb r2, [r3, #0]
strike_at = HAL_GetTick();
8000cb8: f000 fa30 bl 800111c <HAL_GetTick>
8000cbc: 0002 movs r2, r0
8000cbe: 4b26 ldr r3, [pc, #152] @ (8000d58 <handle_strike+0xbc>)
8000cc0: 601a str r2, [r3, #0]
// start the buzzer and set the led
relay_buzz |= 1 << BUZZ_BIT_IDX;
8000cc2: 4b26 ldr r3, [pc, #152] @ (8000d5c <handle_strike+0xc0>)
8000cc4: 781b ldrb r3, [r3, #0]
8000cc6: 2201 movs r2, #1
8000cc8: 4313 orrs r3, r2
8000cca: b2da uxtb r2, r3
8000ccc: 4b23 ldr r3, [pc, #140] @ (8000d5c <handle_strike+0xc0>)
8000cce: 701a strb r2, [r3, #0]
leds |= 1 << 3;
8000cd0: 4b23 ldr r3, [pc, #140] @ (8000d60 <handle_strike+0xc4>)
8000cd2: 781b ldrb r3, [r3, #0]
8000cd4: 2208 movs r2, #8
8000cd6: 4313 orrs r3, r2
8000cd8: b2da uxtb r2, r3
8000cda: 4b21 ldr r3, [pc, #132] @ (8000d60 <handle_strike+0xc4>)
8000cdc: 701a strb r2, [r3, #0]
}
if (strike_at == 0) {
8000cde: 4b1e ldr r3, [pc, #120] @ (8000d58 <handle_strike+0xbc>)
8000ce0: 681b ldr r3, [r3, #0]
8000ce2: 2b00 cmp r3, #0
8000ce4: d031 beq.n 8000d4a <handle_strike+0xae>
return;
}
uint32_t now = HAL_GetTick();
8000ce6: f000 fa19 bl 800111c <HAL_GetTick>
8000cea: 0003 movs r3, r0
8000cec: 60fb str r3, [r7, #12]
uint32_t buzz_threshold = strike_at + strike_buzz_len;
8000cee: 4b1d ldr r3, [pc, #116] @ (8000d64 <handle_strike+0xc8>)
8000cf0: 881b ldrh r3, [r3, #0]
8000cf2: 001a movs r2, r3
8000cf4: 4b18 ldr r3, [pc, #96] @ (8000d58 <handle_strike+0xbc>)
8000cf6: 681b ldr r3, [r3, #0]
8000cf8: 18d3 adds r3, r2, r3
8000cfa: 60bb str r3, [r7, #8]
if (now > buzz_threshold && old_tick <= buzz_threshold) {
8000cfc: 68fa ldr r2, [r7, #12]
8000cfe: 68bb ldr r3, [r7, #8]
8000d00: 429a cmp r2, r3
8000d02: d907 bls.n 8000d14 <handle_strike+0x78>
8000d04: 4b18 ldr r3, [pc, #96] @ (8000d68 <handle_strike+0xcc>)
8000d06: 681b ldr r3, [r3, #0]
8000d08: 68ba ldr r2, [r7, #8]
8000d0a: 429a cmp r2, r3
8000d0c: d302 bcc.n 8000d14 <handle_strike+0x78>
// stop buzzing, start the relay
relay_buzz = (1 << RELAY_BIT_IDX);
8000d0e: 4b13 ldr r3, [pc, #76] @ (8000d5c <handle_strike+0xc0>)
8000d10: 2202 movs r2, #2
8000d12: 701a strb r2, [r3, #0]
}
uint32_t relay_threshold = buzz_threshold + strike_relay_len;
8000d14: 4b15 ldr r3, [pc, #84] @ (8000d6c <handle_strike+0xd0>)
8000d16: 881b ldrh r3, [r3, #0]
8000d18: 001a movs r2, r3
8000d1a: 68bb ldr r3, [r7, #8]
8000d1c: 189b adds r3, r3, r2
8000d1e: 607b str r3, [r7, #4]
if (now > relay_threshold) {
8000d20: 68fa ldr r2, [r7, #12]
8000d22: 687b ldr r3, [r7, #4]
8000d24: 429a cmp r2, r3
8000d26: d90c bls.n 8000d42 <handle_strike+0xa6>
// stop the strike
strike_at = 0;
8000d28: 4b0b ldr r3, [pc, #44] @ (8000d58 <handle_strike+0xbc>)
8000d2a: 2200 movs r2, #0
8000d2c: 601a str r2, [r3, #0]
relay_buzz = 0;
8000d2e: 4b0b ldr r3, [pc, #44] @ (8000d5c <handle_strike+0xc0>)
8000d30: 2200 movs r2, #0
8000d32: 701a strb r2, [r3, #0]
leds &= ~(1 << 3);
8000d34: 4b0a ldr r3, [pc, #40] @ (8000d60 <handle_strike+0xc4>)
8000d36: 781b ldrb r3, [r3, #0]
8000d38: 2208 movs r2, #8
8000d3a: 4393 bics r3, r2
8000d3c: b2da uxtb r2, r3
8000d3e: 4b08 ldr r3, [pc, #32] @ (8000d60 <handle_strike+0xc4>)
8000d40: 701a strb r2, [r3, #0]
}
old_tick = now;
8000d42: 4b09 ldr r3, [pc, #36] @ (8000d68 <handle_strike+0xcc>)
8000d44: 68fa ldr r2, [r7, #12]
8000d46: 601a str r2, [r3, #0]
8000d48: e000 b.n 8000d4c <handle_strike+0xb0>
return;
8000d4a: 46c0 nop @ (mov r8, r8)
}
8000d4c: 46bd mov sp, r7
8000d4e: b004 add sp, #16
8000d50: bd80 pop {r7, pc}
8000d52: 46c0 nop @ (mov r8, r8)
8000d54: 20000122 .word 0x20000122
8000d58: 20000124 .word 0x20000124
8000d5c: 2000011f .word 0x2000011f
8000d60: 20000121 .word 0x20000121
8000d64: 20000000 .word 0x20000000
8000d68: 20000134 .word 0x20000134
8000d6c: 20000002 .word 0x20000002
08000d70 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000d70: b580 push {r7, lr}
8000d72: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000d74: b672 cpsid i
}
8000d76: 46c0 nop @ (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000d78: 46c0 nop @ (mov r8, r8)
8000d7a: e7fd b.n 8000d78 <Error_Handler+0x8>
08000d7c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000d7c: b580 push {r7, lr}
8000d7e: b082 sub sp, #8
8000d80: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000d82: 4b11 ldr r3, [pc, #68] @ (8000dc8 <HAL_MspInit+0x4c>)
8000d84: 6c1a ldr r2, [r3, #64] @ 0x40
8000d86: 4b10 ldr r3, [pc, #64] @ (8000dc8 <HAL_MspInit+0x4c>)
8000d88: 2101 movs r1, #1
8000d8a: 430a orrs r2, r1
8000d8c: 641a str r2, [r3, #64] @ 0x40
8000d8e: 4b0e ldr r3, [pc, #56] @ (8000dc8 <HAL_MspInit+0x4c>)
8000d90: 6c1b ldr r3, [r3, #64] @ 0x40
8000d92: 2201 movs r2, #1
8000d94: 4013 ands r3, r2
8000d96: 607b str r3, [r7, #4]
8000d98: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000d9a: 4b0b ldr r3, [pc, #44] @ (8000dc8 <HAL_MspInit+0x4c>)
8000d9c: 6bda ldr r2, [r3, #60] @ 0x3c
8000d9e: 4b0a ldr r3, [pc, #40] @ (8000dc8 <HAL_MspInit+0x4c>)
8000da0: 2180 movs r1, #128 @ 0x80
8000da2: 0549 lsls r1, r1, #21
8000da4: 430a orrs r2, r1
8000da6: 63da str r2, [r3, #60] @ 0x3c
8000da8: 4b07 ldr r3, [pc, #28] @ (8000dc8 <HAL_MspInit+0x4c>)
8000daa: 6bda ldr r2, [r3, #60] @ 0x3c
8000dac: 2380 movs r3, #128 @ 0x80
8000dae: 055b lsls r3, r3, #21
8000db0: 4013 ands r3, r2
8000db2: 603b str r3, [r7, #0]
8000db4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
8000db6: 23c0 movs r3, #192 @ 0xc0
8000db8: 00db lsls r3, r3, #3
8000dba: 0018 movs r0, r3
8000dbc: f000 f9b8 bl 8001130 <HAL_SYSCFG_StrobeDBattpinsConfig>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000dc0: 46c0 nop @ (mov r8, r8)
8000dc2: 46bd mov sp, r7
8000dc4: b002 add sp, #8
8000dc6: bd80 pop {r7, pc}
8000dc8: 40021000 .word 0x40021000
08000dcc <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8000dcc: b590 push {r4, r7, lr}
8000dce: b091 sub sp, #68 @ 0x44
8000dd0: af00 add r7, sp, #0
8000dd2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000dd4: 232c movs r3, #44 @ 0x2c
8000dd6: 18fb adds r3, r7, r3
8000dd8: 0018 movs r0, r3
8000dda: 2314 movs r3, #20
8000ddc: 001a movs r2, r3
8000dde: 2100 movs r1, #0
8000de0: f003 fe52 bl 8004a88 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000de4: 2410 movs r4, #16
8000de6: 193b adds r3, r7, r4
8000de8: 0018 movs r0, r3
8000dea: 231c movs r3, #28
8000dec: 001a movs r2, r3
8000dee: 2100 movs r1, #0
8000df0: f003 fe4a bl 8004a88 <memset>
if(hi2c->Instance==I2C1)
8000df4: 687b ldr r3, [r7, #4]
8000df6: 681b ldr r3, [r3, #0]
8000df8: 4a26 ldr r2, [pc, #152] @ (8000e94 <HAL_I2C_MspInit+0xc8>)
8000dfa: 4293 cmp r3, r2
8000dfc: d145 bne.n 8000e8a <HAL_I2C_MspInit+0xbe>
/* USER CODE END I2C1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
8000dfe: 193b adds r3, r7, r4
8000e00: 2220 movs r2, #32
8000e02: 601a str r2, [r3, #0]
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
8000e04: 193b adds r3, r7, r4
8000e06: 2200 movs r2, #0
8000e08: 60da str r2, [r3, #12]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000e0a: 193b adds r3, r7, r4
8000e0c: 0018 movs r0, r3
8000e0e: f002 ffbf bl 8003d90 <HAL_RCCEx_PeriphCLKConfig>
8000e12: 1e03 subs r3, r0, #0
8000e14: d001 beq.n 8000e1a <HAL_I2C_MspInit+0x4e>
{
Error_Handler();
8000e16: f7ff ffab bl 8000d70 <Error_Handler>
}
__HAL_RCC_GPIOB_CLK_ENABLE();
8000e1a: 4b1f ldr r3, [pc, #124] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e1c: 6b5a ldr r2, [r3, #52] @ 0x34
8000e1e: 4b1e ldr r3, [pc, #120] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e20: 2102 movs r1, #2
8000e22: 430a orrs r2, r1
8000e24: 635a str r2, [r3, #52] @ 0x34
8000e26: 4b1c ldr r3, [pc, #112] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e28: 6b5b ldr r3, [r3, #52] @ 0x34
8000e2a: 2202 movs r2, #2
8000e2c: 4013 ands r3, r2
8000e2e: 60fb str r3, [r7, #12]
8000e30: 68fb ldr r3, [r7, #12]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8000e32: 212c movs r1, #44 @ 0x2c
8000e34: 187b adds r3, r7, r1
8000e36: 22c0 movs r2, #192 @ 0xc0
8000e38: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000e3a: 187b adds r3, r7, r1
8000e3c: 2212 movs r2, #18
8000e3e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000e40: 187b adds r3, r7, r1
8000e42: 2200 movs r2, #0
8000e44: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e46: 187b adds r3, r7, r1
8000e48: 2200 movs r2, #0
8000e4a: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF6_I2C1;
8000e4c: 187b adds r3, r7, r1
8000e4e: 2206 movs r2, #6
8000e50: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000e52: 187b adds r3, r7, r1
8000e54: 4a11 ldr r2, [pc, #68] @ (8000e9c <HAL_I2C_MspInit+0xd0>)
8000e56: 0019 movs r1, r3
8000e58: 0010 movs r0, r2
8000e5a: f000 fad3 bl 8001404 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8000e5e: 4b0e ldr r3, [pc, #56] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e60: 6bda ldr r2, [r3, #60] @ 0x3c
8000e62: 4b0d ldr r3, [pc, #52] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e64: 2180 movs r1, #128 @ 0x80
8000e66: 0389 lsls r1, r1, #14
8000e68: 430a orrs r2, r1
8000e6a: 63da str r2, [r3, #60] @ 0x3c
8000e6c: 4b0a ldr r3, [pc, #40] @ (8000e98 <HAL_I2C_MspInit+0xcc>)
8000e6e: 6bda ldr r2, [r3, #60] @ 0x3c
8000e70: 2380 movs r3, #128 @ 0x80
8000e72: 039b lsls r3, r3, #14
8000e74: 4013 ands r3, r2
8000e76: 60bb str r3, [r7, #8]
8000e78: 68bb ldr r3, [r7, #8]
/* I2C1 interrupt Init */
HAL_NVIC_SetPriority(I2C1_IRQn, 0, 0);
8000e7a: 2200 movs r2, #0
8000e7c: 2100 movs r1, #0
8000e7e: 2017 movs r0, #23
8000e80: f000 fa18 bl 80012b4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(I2C1_IRQn);
8000e84: 2017 movs r0, #23
8000e86: f000 fa2a bl 80012de <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
8000e8a: 46c0 nop @ (mov r8, r8)
8000e8c: 46bd mov sp, r7
8000e8e: b011 add sp, #68 @ 0x44
8000e90: bd90 pop {r4, r7, pc}
8000e92: 46c0 nop @ (mov r8, r8)
8000e94: 40005400 .word 0x40005400
8000e98: 40021000 .word 0x40021000
8000e9c: 50000400 .word 0x50000400
08000ea0 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000ea0: b590 push {r4, r7, lr}
8000ea2: b091 sub sp, #68 @ 0x44
8000ea4: af00 add r7, sp, #0
8000ea6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ea8: 232c movs r3, #44 @ 0x2c
8000eaa: 18fb adds r3, r7, r3
8000eac: 0018 movs r0, r3
8000eae: 2314 movs r3, #20
8000eb0: 001a movs r2, r3
8000eb2: 2100 movs r1, #0
8000eb4: f003 fde8 bl 8004a88 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000eb8: 2410 movs r4, #16
8000eba: 193b adds r3, r7, r4
8000ebc: 0018 movs r0, r3
8000ebe: 231c movs r3, #28
8000ec0: 001a movs r2, r3
8000ec2: 2100 movs r1, #0
8000ec4: f003 fde0 bl 8004a88 <memset>
if(huart->Instance==USART2)
8000ec8: 687b ldr r3, [r7, #4]
8000eca: 681b ldr r3, [r3, #0]
8000ecc: 4a22 ldr r2, [pc, #136] @ (8000f58 <HAL_UART_MspInit+0xb8>)
8000ece: 4293 cmp r3, r2
8000ed0: d13e bne.n 8000f50 <HAL_UART_MspInit+0xb0>
/* USER CODE END USART2_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
8000ed2: 193b adds r3, r7, r4
8000ed4: 2202 movs r2, #2
8000ed6: 601a str r2, [r3, #0]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
8000ed8: 193b adds r3, r7, r4
8000eda: 2200 movs r2, #0
8000edc: 609a str r2, [r3, #8]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8000ede: 193b adds r3, r7, r4
8000ee0: 0018 movs r0, r3
8000ee2: f002 ff55 bl 8003d90 <HAL_RCCEx_PeriphCLKConfig>
8000ee6: 1e03 subs r3, r0, #0
8000ee8: d001 beq.n 8000eee <HAL_UART_MspInit+0x4e>
{
Error_Handler();
8000eea: f7ff ff41 bl 8000d70 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
8000eee: 4b1b ldr r3, [pc, #108] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000ef0: 6bda ldr r2, [r3, #60] @ 0x3c
8000ef2: 4b1a ldr r3, [pc, #104] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000ef4: 2180 movs r1, #128 @ 0x80
8000ef6: 0289 lsls r1, r1, #10
8000ef8: 430a orrs r2, r1
8000efa: 63da str r2, [r3, #60] @ 0x3c
8000efc: 4b17 ldr r3, [pc, #92] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000efe: 6bda ldr r2, [r3, #60] @ 0x3c
8000f00: 2380 movs r3, #128 @ 0x80
8000f02: 029b lsls r3, r3, #10
8000f04: 4013 ands r3, r2
8000f06: 60fb str r3, [r7, #12]
8000f08: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000f0a: 4b14 ldr r3, [pc, #80] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000f0c: 6b5a ldr r2, [r3, #52] @ 0x34
8000f0e: 4b13 ldr r3, [pc, #76] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000f10: 2101 movs r1, #1
8000f12: 430a orrs r2, r1
8000f14: 635a str r2, [r3, #52] @ 0x34
8000f16: 4b11 ldr r3, [pc, #68] @ (8000f5c <HAL_UART_MspInit+0xbc>)
8000f18: 6b5b ldr r3, [r3, #52] @ 0x34
8000f1a: 2201 movs r2, #1
8000f1c: 4013 ands r3, r2
8000f1e: 60bb str r3, [r7, #8]
8000f20: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = TX_Pin|RX_Pin;
8000f22: 212c movs r1, #44 @ 0x2c
8000f24: 187b adds r3, r7, r1
8000f26: 220c movs r2, #12
8000f28: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000f2a: 187b adds r3, r7, r1
8000f2c: 2202 movs r2, #2
8000f2e: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000f30: 187b adds r3, r7, r1
8000f32: 2200 movs r2, #0
8000f34: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000f36: 187b adds r3, r7, r1
8000f38: 2200 movs r2, #0
8000f3a: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
8000f3c: 187b adds r3, r7, r1
8000f3e: 2201 movs r2, #1
8000f40: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000f42: 187a adds r2, r7, r1
8000f44: 23a0 movs r3, #160 @ 0xa0
8000f46: 05db lsls r3, r3, #23
8000f48: 0011 movs r1, r2
8000f4a: 0018 movs r0, r3
8000f4c: f000 fa5a bl 8001404 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000f50: 46c0 nop @ (mov r8, r8)
8000f52: 46bd mov sp, r7
8000f54: b011 add sp, #68 @ 0x44
8000f56: bd90 pop {r4, r7, pc}
8000f58: 40004400 .word 0x40004400
8000f5c: 40021000 .word 0x40021000
08000f60 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000f60: b580 push {r7, lr}
8000f62: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000f64: 46c0 nop @ (mov r8, r8)
8000f66: e7fd b.n 8000f64 <NMI_Handler+0x4>
08000f68 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000f68: b580 push {r7, lr}
8000f6a: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000f6c: 46c0 nop @ (mov r8, r8)
8000f6e: e7fd b.n 8000f6c <HardFault_Handler+0x4>
08000f70 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000f70: b580 push {r7, lr}
8000f72: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
8000f74: 46c0 nop @ (mov r8, r8)
8000f76: 46bd mov sp, r7
8000f78: bd80 pop {r7, pc}
08000f7a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000f7a: b580 push {r7, lr}
8000f7c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000f7e: 46c0 nop @ (mov r8, r8)
8000f80: 46bd mov sp, r7
8000f82: bd80 pop {r7, pc}
08000f84 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000f84: b580 push {r7, lr}
8000f86: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000f88: f000 f8b6 bl 80010f8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000f8c: 46c0 nop @ (mov r8, r8)
8000f8e: 46bd mov sp, r7
8000f90: bd80 pop {r7, pc}
...
08000f94 <I2C1_IRQHandler>:
/**
* @brief This function handles I2C1 event global interrupt / I2C1 wake-up interrupt through EXTI line 23.
*/
void I2C1_IRQHandler(void)
{
8000f94: b580 push {r7, lr}
8000f96: af00 add r7, sp, #0
/* USER CODE BEGIN I2C1_IRQn 0 */
/* USER CODE END I2C1_IRQn 0 */
if (hi2c1.Instance->ISR & (I2C_FLAG_BERR | I2C_FLAG_ARLO | I2C_FLAG_OVR)) {
8000f98: 4b09 ldr r3, [pc, #36] @ (8000fc0 <I2C1_IRQHandler+0x2c>)
8000f9a: 681b ldr r3, [r3, #0]
8000f9c: 699a ldr r2, [r3, #24]
8000f9e: 23e0 movs r3, #224 @ 0xe0
8000fa0: 00db lsls r3, r3, #3
8000fa2: 4013 ands r3, r2
8000fa4: d004 beq.n 8000fb0 <I2C1_IRQHandler+0x1c>
HAL_I2C_ER_IRQHandler(&hi2c1);
8000fa6: 4b06 ldr r3, [pc, #24] @ (8000fc0 <I2C1_IRQHandler+0x2c>)
8000fa8: 0018 movs r0, r3
8000faa: f000 fe2d bl 8001c08 <HAL_I2C_ER_IRQHandler>
HAL_I2C_EV_IRQHandler(&hi2c1);
}
/* USER CODE BEGIN I2C1_IRQn 1 */
/* USER CODE END I2C1_IRQn 1 */
}
8000fae: e003 b.n 8000fb8 <I2C1_IRQHandler+0x24>
HAL_I2C_EV_IRQHandler(&hi2c1);
8000fb0: 4b03 ldr r3, [pc, #12] @ (8000fc0 <I2C1_IRQHandler+0x2c>)
8000fb2: 0018 movs r0, r3
8000fb4: f000 fe0e bl 8001bd4 <HAL_I2C_EV_IRQHandler>
}
8000fb8: 46c0 nop @ (mov r8, r8)
8000fba: 46bd mov sp, r7
8000fbc: bd80 pop {r7, pc}
8000fbe: 46c0 nop @ (mov r8, r8)
8000fc0: 20000030 .word 0x20000030
08000fc4 <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000fc4: b580 push {r7, lr}
8000fc6: af00 add r7, sp, #0
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000fc8: 46c0 nop @ (mov r8, r8)
8000fca: 46bd mov sp, r7
8000fcc: bd80 pop {r7, pc}
...
08000fd0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
8000fd0: 480d ldr r0, [pc, #52] @ (8001008 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
8000fd2: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8000fd4: f7ff fff6 bl 8000fc4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000fd8: 480c ldr r0, [pc, #48] @ (800100c <LoopForever+0x6>)
ldr r1, =_edata
8000fda: 490d ldr r1, [pc, #52] @ (8001010 <LoopForever+0xa>)
ldr r2, =_sidata
8000fdc: 4a0d ldr r2, [pc, #52] @ (8001014 <LoopForever+0xe>)
movs r3, #0
8000fde: 2300 movs r3, #0
b LoopCopyDataInit
8000fe0: e002 b.n 8000fe8 <LoopCopyDataInit>
08000fe2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000fe2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000fe4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000fe6: 3304 adds r3, #4
08000fe8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000fe8: 18c4 adds r4, r0, r3
cmp r4, r1
8000fea: 428c cmp r4, r1
bcc CopyDataInit
8000fec: d3f9 bcc.n 8000fe2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000fee: 4a0a ldr r2, [pc, #40] @ (8001018 <LoopForever+0x12>)
ldr r4, =_ebss
8000ff0: 4c0a ldr r4, [pc, #40] @ (800101c <LoopForever+0x16>)
movs r3, #0
8000ff2: 2300 movs r3, #0
b LoopFillZerobss
8000ff4: e001 b.n 8000ffa <LoopFillZerobss>
08000ff6 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000ff6: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000ff8: 3204 adds r2, #4
08000ffa <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000ffa: 42a2 cmp r2, r4
bcc FillZerobss
8000ffc: d3fb bcc.n 8000ff6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8000ffe: f003 fd4b bl 8004a98 <__libc_init_array>
/* Call the application s entry point.*/
bl main
8001002: f7ff f9f3 bl 80003ec <main>
08001006 <LoopForever>:
LoopForever:
b LoopForever
8001006: e7fe b.n 8001006 <LoopForever>
ldr r0, =_estack
8001008: 20009000 .word 0x20009000
ldr r0, =_sdata
800100c: 20000000 .word 0x20000000
ldr r1, =_edata
8001010: 20000010 .word 0x20000010
ldr r2, =_sidata
8001014: 08004bac .word 0x08004bac
ldr r2, =_sbss
8001018: 20000010 .word 0x20000010
ldr r4, =_ebss
800101c: 2000013c .word 0x2000013c
08001020 <ADC1_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001020: e7fe b.n 8001020 <ADC1_IRQHandler>
...
08001024 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001024: b580 push {r7, lr}
8001026: b082 sub sp, #8
8001028: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
800102a: 1dfb adds r3, r7, #7
800102c: 2200 movs r2, #0
800102e: 701a strb r2, [r3, #0]
#if (INSTRUCTION_CACHE_ENABLE == 0U)
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001030: 4b0b ldr r3, [pc, #44] @ (8001060 <HAL_Init+0x3c>)
8001032: 681a ldr r2, [r3, #0]
8001034: 4b0a ldr r3, [pc, #40] @ (8001060 <HAL_Init+0x3c>)
8001036: 2180 movs r1, #128 @ 0x80
8001038: 0049 lsls r1, r1, #1
800103a: 430a orrs r2, r1
800103c: 601a str r2, [r3, #0]
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
800103e: 2003 movs r0, #3
8001040: f000 f810 bl 8001064 <HAL_InitTick>
8001044: 1e03 subs r3, r0, #0
8001046: d003 beq.n 8001050 <HAL_Init+0x2c>
{
status = HAL_ERROR;
8001048: 1dfb adds r3, r7, #7
800104a: 2201 movs r2, #1
800104c: 701a strb r2, [r3, #0]
800104e: e001 b.n 8001054 <HAL_Init+0x30>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001050: f7ff fe94 bl 8000d7c <HAL_MspInit>
}
/* Return function status */
return status;
8001054: 1dfb adds r3, r7, #7
8001056: 781b ldrb r3, [r3, #0]
}
8001058: 0018 movs r0, r3
800105a: 46bd mov sp, r7
800105c: b002 add sp, #8
800105e: bd80 pop {r7, pc}
8001060: 40022000 .word 0x40022000
08001064 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001064: b590 push {r4, r7, lr}
8001066: b085 sub sp, #20
8001068: af00 add r7, sp, #0
800106a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800106c: 230f movs r3, #15
800106e: 18fb adds r3, r7, r3
8001070: 2200 movs r2, #0
8001072: 701a strb r2, [r3, #0]
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
if ((uint32_t)uwTickFreq != 0U)
8001074: 4b1d ldr r3, [pc, #116] @ (80010ec <HAL_InitTick+0x88>)
8001076: 781b ldrb r3, [r3, #0]
8001078: 2b00 cmp r3, #0
800107a: d02b beq.n 80010d4 <HAL_InitTick+0x70>
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U)
800107c: 4b1c ldr r3, [pc, #112] @ (80010f0 <HAL_InitTick+0x8c>)
800107e: 681c ldr r4, [r3, #0]
8001080: 4b1a ldr r3, [pc, #104] @ (80010ec <HAL_InitTick+0x88>)
8001082: 781b ldrb r3, [r3, #0]
8001084: 0019 movs r1, r3
8001086: 23fa movs r3, #250 @ 0xfa
8001088: 0098 lsls r0, r3, #2
800108a: f7ff f839 bl 8000100 <__udivsi3>
800108e: 0003 movs r3, r0
8001090: 0019 movs r1, r3
8001092: 0020 movs r0, r4
8001094: f7ff f834 bl 8000100 <__udivsi3>
8001098: 0003 movs r3, r0
800109a: 0018 movs r0, r3
800109c: f000 f92f bl 80012fe <HAL_SYSTICK_Config>
80010a0: 1e03 subs r3, r0, #0
80010a2: d112 bne.n 80010ca <HAL_InitTick+0x66>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80010a4: 687b ldr r3, [r7, #4]
80010a6: 2b03 cmp r3, #3
80010a8: d80a bhi.n 80010c0 <HAL_InitTick+0x5c>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80010aa: 6879 ldr r1, [r7, #4]
80010ac: 2301 movs r3, #1
80010ae: 425b negs r3, r3
80010b0: 2200 movs r2, #0
80010b2: 0018 movs r0, r3
80010b4: f000 f8fe bl 80012b4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80010b8: 4b0e ldr r3, [pc, #56] @ (80010f4 <HAL_InitTick+0x90>)
80010ba: 687a ldr r2, [r7, #4]
80010bc: 601a str r2, [r3, #0]
80010be: e00d b.n 80010dc <HAL_InitTick+0x78>
}
else
{
status = HAL_ERROR;
80010c0: 230f movs r3, #15
80010c2: 18fb adds r3, r7, r3
80010c4: 2201 movs r2, #1
80010c6: 701a strb r2, [r3, #0]
80010c8: e008 b.n 80010dc <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
80010ca: 230f movs r3, #15
80010cc: 18fb adds r3, r7, r3
80010ce: 2201 movs r2, #1
80010d0: 701a strb r2, [r3, #0]
80010d2: e003 b.n 80010dc <HAL_InitTick+0x78>
}
}
else
{
status = HAL_ERROR;
80010d4: 230f movs r3, #15
80010d6: 18fb adds r3, r7, r3
80010d8: 2201 movs r2, #1
80010da: 701a strb r2, [r3, #0]
}
/* Return function status */
return status;
80010dc: 230f movs r3, #15
80010de: 18fb adds r3, r7, r3
80010e0: 781b ldrb r3, [r3, #0]
}
80010e2: 0018 movs r0, r3
80010e4: 46bd mov sp, r7
80010e6: b005 add sp, #20
80010e8: bd90 pop {r4, r7, pc}
80010ea: 46c0 nop @ (mov r8, r8)
80010ec: 2000000c .word 0x2000000c
80010f0: 20000004 .word 0x20000004
80010f4: 20000008 .word 0x20000008
080010f8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80010f8: b580 push {r7, lr}
80010fa: af00 add r7, sp, #0
uwTick += (uint32_t)uwTickFreq;
80010fc: 4b05 ldr r3, [pc, #20] @ (8001114 <HAL_IncTick+0x1c>)
80010fe: 781b ldrb r3, [r3, #0]
8001100: 001a movs r2, r3
8001102: 4b05 ldr r3, [pc, #20] @ (8001118 <HAL_IncTick+0x20>)
8001104: 681b ldr r3, [r3, #0]
8001106: 18d2 adds r2, r2, r3
8001108: 4b03 ldr r3, [pc, #12] @ (8001118 <HAL_IncTick+0x20>)
800110a: 601a str r2, [r3, #0]
}
800110c: 46c0 nop @ (mov r8, r8)
800110e: 46bd mov sp, r7
8001110: bd80 pop {r7, pc}
8001112: 46c0 nop @ (mov r8, r8)
8001114: 2000000c .word 0x2000000c
8001118: 20000138 .word 0x20000138
0800111c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800111c: b580 push {r7, lr}
800111e: af00 add r7, sp, #0
return uwTick;
8001120: 4b02 ldr r3, [pc, #8] @ (800112c <HAL_GetTick+0x10>)
8001122: 681b ldr r3, [r3, #0]
}
8001124: 0018 movs r0, r3
8001126: 46bd mov sp, r7
8001128: bd80 pop {r7, pc}
800112a: 46c0 nop @ (mov r8, r8)
800112c: 20000138 .word 0x20000138
08001130 <HAL_SYSCFG_StrobeDBattpinsConfig>:
* @arg @ref SYSCFG_UCPD1_STROBE
* @arg @ref SYSCFG_UCPD2_STROBE
* @retval None
*/
void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery)
{
8001130: b580 push {r7, lr}
8001132: b082 sub sp, #8
8001134: af00 add r7, sp, #0
8001136: 6078 str r0, [r7, #4]
assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery));
/* Change strobe configuration of GPIO depending on UCPDx dead battery settings */
MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery);
8001138: 4b06 ldr r3, [pc, #24] @ (8001154 <HAL_SYSCFG_StrobeDBattpinsConfig+0x24>)
800113a: 681b ldr r3, [r3, #0]
800113c: 4a06 ldr r2, [pc, #24] @ (8001158 <HAL_SYSCFG_StrobeDBattpinsConfig+0x28>)
800113e: 4013 ands r3, r2
8001140: 0019 movs r1, r3
8001142: 4b04 ldr r3, [pc, #16] @ (8001154 <HAL_SYSCFG_StrobeDBattpinsConfig+0x24>)
8001144: 687a ldr r2, [r7, #4]
8001146: 430a orrs r2, r1
8001148: 601a str r2, [r3, #0]
}
800114a: 46c0 nop @ (mov r8, r8)
800114c: 46bd mov sp, r7
800114e: b002 add sp, #8
8001150: bd80 pop {r7, pc}
8001152: 46c0 nop @ (mov r8, r8)
8001154: 40010000 .word 0x40010000
8001158: fffff9ff .word 0xfffff9ff
0800115c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
800115c: b580 push {r7, lr}
800115e: b082 sub sp, #8
8001160: af00 add r7, sp, #0
8001162: 0002 movs r2, r0
8001164: 1dfb adds r3, r7, #7
8001166: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
8001168: 1dfb adds r3, r7, #7
800116a: 781b ldrb r3, [r3, #0]
800116c: 2b7f cmp r3, #127 @ 0x7f
800116e: d809 bhi.n 8001184 <__NVIC_EnableIRQ+0x28>
{
__COMPILER_BARRIER();
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8001170: 1dfb adds r3, r7, #7
8001172: 781b ldrb r3, [r3, #0]
8001174: 001a movs r2, r3
8001176: 231f movs r3, #31
8001178: 401a ands r2, r3
800117a: 4b04 ldr r3, [pc, #16] @ (800118c <__NVIC_EnableIRQ+0x30>)
800117c: 2101 movs r1, #1
800117e: 4091 lsls r1, r2
8001180: 000a movs r2, r1
8001182: 601a str r2, [r3, #0]
__COMPILER_BARRIER();
}
}
8001184: 46c0 nop @ (mov r8, r8)
8001186: 46bd mov sp, r7
8001188: b002 add sp, #8
800118a: bd80 pop {r7, pc}
800118c: e000e100 .word 0xe000e100
08001190 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001190: b590 push {r4, r7, lr}
8001192: b083 sub sp, #12
8001194: af00 add r7, sp, #0
8001196: 0002 movs r2, r0
8001198: 6039 str r1, [r7, #0]
800119a: 1dfb adds r3, r7, #7
800119c: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
800119e: 1dfb adds r3, r7, #7
80011a0: 781b ldrb r3, [r3, #0]
80011a2: 2b7f cmp r3, #127 @ 0x7f
80011a4: d828 bhi.n 80011f8 <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80011a6: 4a2f ldr r2, [pc, #188] @ (8001264 <__NVIC_SetPriority+0xd4>)
80011a8: 1dfb adds r3, r7, #7
80011aa: 781b ldrb r3, [r3, #0]
80011ac: b25b sxtb r3, r3
80011ae: 089b lsrs r3, r3, #2
80011b0: 33c0 adds r3, #192 @ 0xc0
80011b2: 009b lsls r3, r3, #2
80011b4: 589b ldr r3, [r3, r2]
80011b6: 1dfa adds r2, r7, #7
80011b8: 7812 ldrb r2, [r2, #0]
80011ba: 0011 movs r1, r2
80011bc: 2203 movs r2, #3
80011be: 400a ands r2, r1
80011c0: 00d2 lsls r2, r2, #3
80011c2: 21ff movs r1, #255 @ 0xff
80011c4: 4091 lsls r1, r2
80011c6: 000a movs r2, r1
80011c8: 43d2 mvns r2, r2
80011ca: 401a ands r2, r3
80011cc: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
80011ce: 683b ldr r3, [r7, #0]
80011d0: 019b lsls r3, r3, #6
80011d2: 22ff movs r2, #255 @ 0xff
80011d4: 401a ands r2, r3
80011d6: 1dfb adds r3, r7, #7
80011d8: 781b ldrb r3, [r3, #0]
80011da: 0018 movs r0, r3
80011dc: 2303 movs r3, #3
80011de: 4003 ands r3, r0
80011e0: 00db lsls r3, r3, #3
80011e2: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80011e4: 481f ldr r0, [pc, #124] @ (8001264 <__NVIC_SetPriority+0xd4>)
80011e6: 1dfb adds r3, r7, #7
80011e8: 781b ldrb r3, [r3, #0]
80011ea: b25b sxtb r3, r3
80011ec: 089b lsrs r3, r3, #2
80011ee: 430a orrs r2, r1
80011f0: 33c0 adds r3, #192 @ 0xc0
80011f2: 009b lsls r3, r3, #2
80011f4: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
80011f6: e031 b.n 800125c <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
80011f8: 4a1b ldr r2, [pc, #108] @ (8001268 <__NVIC_SetPriority+0xd8>)
80011fa: 1dfb adds r3, r7, #7
80011fc: 781b ldrb r3, [r3, #0]
80011fe: 0019 movs r1, r3
8001200: 230f movs r3, #15
8001202: 400b ands r3, r1
8001204: 3b08 subs r3, #8
8001206: 089b lsrs r3, r3, #2
8001208: 3306 adds r3, #6
800120a: 009b lsls r3, r3, #2
800120c: 18d3 adds r3, r2, r3
800120e: 3304 adds r3, #4
8001210: 681b ldr r3, [r3, #0]
8001212: 1dfa adds r2, r7, #7
8001214: 7812 ldrb r2, [r2, #0]
8001216: 0011 movs r1, r2
8001218: 2203 movs r2, #3
800121a: 400a ands r2, r1
800121c: 00d2 lsls r2, r2, #3
800121e: 21ff movs r1, #255 @ 0xff
8001220: 4091 lsls r1, r2
8001222: 000a movs r2, r1
8001224: 43d2 mvns r2, r2
8001226: 401a ands r2, r3
8001228: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
800122a: 683b ldr r3, [r7, #0]
800122c: 019b lsls r3, r3, #6
800122e: 22ff movs r2, #255 @ 0xff
8001230: 401a ands r2, r3
8001232: 1dfb adds r3, r7, #7
8001234: 781b ldrb r3, [r3, #0]
8001236: 0018 movs r0, r3
8001238: 2303 movs r3, #3
800123a: 4003 ands r3, r0
800123c: 00db lsls r3, r3, #3
800123e: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8001240: 4809 ldr r0, [pc, #36] @ (8001268 <__NVIC_SetPriority+0xd8>)
8001242: 1dfb adds r3, r7, #7
8001244: 781b ldrb r3, [r3, #0]
8001246: 001c movs r4, r3
8001248: 230f movs r3, #15
800124a: 4023 ands r3, r4
800124c: 3b08 subs r3, #8
800124e: 089b lsrs r3, r3, #2
8001250: 430a orrs r2, r1
8001252: 3306 adds r3, #6
8001254: 009b lsls r3, r3, #2
8001256: 18c3 adds r3, r0, r3
8001258: 3304 adds r3, #4
800125a: 601a str r2, [r3, #0]
}
800125c: 46c0 nop @ (mov r8, r8)
800125e: 46bd mov sp, r7
8001260: b003 add sp, #12
8001262: bd90 pop {r4, r7, pc}
8001264: e000e100 .word 0xe000e100
8001268: e000ed00 .word 0xe000ed00
0800126c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
800126c: b580 push {r7, lr}
800126e: b082 sub sp, #8
8001270: af00 add r7, sp, #0
8001272: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001274: 687b ldr r3, [r7, #4]
8001276: 1e5a subs r2, r3, #1
8001278: 2380 movs r3, #128 @ 0x80
800127a: 045b lsls r3, r3, #17
800127c: 429a cmp r2, r3
800127e: d301 bcc.n 8001284 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
8001280: 2301 movs r3, #1
8001282: e010 b.n 80012a6 <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001284: 4b0a ldr r3, [pc, #40] @ (80012b0 <SysTick_Config+0x44>)
8001286: 687a ldr r2, [r7, #4]
8001288: 3a01 subs r2, #1
800128a: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
800128c: 2301 movs r3, #1
800128e: 425b negs r3, r3
8001290: 2103 movs r1, #3
8001292: 0018 movs r0, r3
8001294: f7ff ff7c bl 8001190 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8001298: 4b05 ldr r3, [pc, #20] @ (80012b0 <SysTick_Config+0x44>)
800129a: 2200 movs r2, #0
800129c: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
800129e: 4b04 ldr r3, [pc, #16] @ (80012b0 <SysTick_Config+0x44>)
80012a0: 2207 movs r2, #7
80012a2: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80012a4: 2300 movs r3, #0
}
80012a6: 0018 movs r0, r3
80012a8: 46bd mov sp, r7
80012aa: b002 add sp, #8
80012ac: bd80 pop {r7, pc}
80012ae: 46c0 nop @ (mov r8, r8)
80012b0: e000e010 .word 0xe000e010
080012b4 <HAL_NVIC_SetPriority>:
* with stm32g0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80012b4: b580 push {r7, lr}
80012b6: b084 sub sp, #16
80012b8: af00 add r7, sp, #0
80012ba: 60b9 str r1, [r7, #8]
80012bc: 607a str r2, [r7, #4]
80012be: 210f movs r1, #15
80012c0: 187b adds r3, r7, r1
80012c2: 1c02 adds r2, r0, #0
80012c4: 701a strb r2, [r3, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
80012c6: 68ba ldr r2, [r7, #8]
80012c8: 187b adds r3, r7, r1
80012ca: 781b ldrb r3, [r3, #0]
80012cc: b25b sxtb r3, r3
80012ce: 0011 movs r1, r2
80012d0: 0018 movs r0, r3
80012d2: f7ff ff5d bl 8001190 <__NVIC_SetPriority>
}
80012d6: 46c0 nop @ (mov r8, r8)
80012d8: 46bd mov sp, r7
80012da: b004 add sp, #16
80012dc: bd80 pop {r7, pc}
080012de <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
80012de: b580 push {r7, lr}
80012e0: b082 sub sp, #8
80012e2: af00 add r7, sp, #0
80012e4: 0002 movs r2, r0
80012e6: 1dfb adds r3, r7, #7
80012e8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
80012ea: 1dfb adds r3, r7, #7
80012ec: 781b ldrb r3, [r3, #0]
80012ee: b25b sxtb r3, r3
80012f0: 0018 movs r0, r3
80012f2: f7ff ff33 bl 800115c <__NVIC_EnableIRQ>
}
80012f6: 46c0 nop @ (mov r8, r8)
80012f8: 46bd mov sp, r7
80012fa: b002 add sp, #8
80012fc: bd80 pop {r7, pc}
080012fe <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
80012fe: b580 push {r7, lr}
8001300: b082 sub sp, #8
8001302: af00 add r7, sp, #0
8001304: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001306: 687b ldr r3, [r7, #4]
8001308: 0018 movs r0, r3
800130a: f7ff ffaf bl 800126c <SysTick_Config>
800130e: 0003 movs r3, r0
}
8001310: 0018 movs r0, r3
8001312: 46bd mov sp, r7
8001314: b002 add sp, #8
8001316: bd80 pop {r7, pc}
08001318 <HAL_DMA_Abort_IT>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8001318: b580 push {r7, lr}
800131a: b084 sub sp, #16
800131c: af00 add r7, sp, #0
800131e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001320: 210f movs r1, #15
8001322: 187b adds r3, r7, r1
8001324: 2200 movs r2, #0
8001326: 701a strb r2, [r3, #0]
if (hdma->State != HAL_DMA_STATE_BUSY)
8001328: 687b ldr r3, [r7, #4]
800132a: 2225 movs r2, #37 @ 0x25
800132c: 5c9b ldrb r3, [r3, r2]
800132e: b2db uxtb r3, r3
8001330: 2b02 cmp r3, #2
8001332: d006 beq.n 8001342 <HAL_DMA_Abort_IT+0x2a>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001334: 687b ldr r3, [r7, #4]
8001336: 2204 movs r2, #4
8001338: 63da str r2, [r3, #60] @ 0x3c
status = HAL_ERROR;
800133a: 187b adds r3, r7, r1
800133c: 2201 movs r2, #1
800133e: 701a strb r2, [r3, #0]
8001340: e049 b.n 80013d6 <HAL_DMA_Abort_IT+0xbe>
}
else
{
/* Disable DMA IT */
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8001342: 687b ldr r3, [r7, #4]
8001344: 681b ldr r3, [r3, #0]
8001346: 681a ldr r2, [r3, #0]
8001348: 687b ldr r3, [r7, #4]
800134a: 681b ldr r3, [r3, #0]
800134c: 210e movs r1, #14
800134e: 438a bics r2, r1
8001350: 601a str r2, [r3, #0]
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
8001352: 687b ldr r3, [r7, #4]
8001354: 681b ldr r3, [r3, #0]
8001356: 681a ldr r2, [r3, #0]
8001358: 687b ldr r3, [r7, #4]
800135a: 681b ldr r3, [r3, #0]
800135c: 2101 movs r1, #1
800135e: 438a bics r2, r1
8001360: 601a str r2, [r3, #0]
/* disable the DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8001362: 687b ldr r3, [r7, #4]
8001364: 6c5b ldr r3, [r3, #68] @ 0x44
8001366: 681a ldr r2, [r3, #0]
8001368: 687b ldr r3, [r7, #4]
800136a: 6c5b ldr r3, [r3, #68] @ 0x44
800136c: 491d ldr r1, [pc, #116] @ (80013e4 <HAL_DMA_Abort_IT+0xcc>)
800136e: 400a ands r2, r1
8001370: 601a str r2, [r3, #0]
/* Clear all flags */
#if defined(DMA2)
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
#else
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
8001372: 4b1d ldr r3, [pc, #116] @ (80013e8 <HAL_DMA_Abort_IT+0xd0>)
8001374: 6859 ldr r1, [r3, #4]
8001376: 687b ldr r3, [r7, #4]
8001378: 6c1b ldr r3, [r3, #64] @ 0x40
800137a: 221c movs r2, #28
800137c: 4013 ands r3, r2
800137e: 2201 movs r2, #1
8001380: 409a lsls r2, r3
8001382: 4b19 ldr r3, [pc, #100] @ (80013e8 <HAL_DMA_Abort_IT+0xd0>)
8001384: 430a orrs r2, r1
8001386: 605a str r2, [r3, #4]
#endif /* DMA2 */
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8001388: 687b ldr r3, [r7, #4]
800138a: 6c9b ldr r3, [r3, #72] @ 0x48
800138c: 687a ldr r2, [r7, #4]
800138e: 6cd2 ldr r2, [r2, #76] @ 0x4c
8001390: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8001392: 687b ldr r3, [r7, #4]
8001394: 6d1b ldr r3, [r3, #80] @ 0x50
8001396: 2b00 cmp r3, #0
8001398: d00c beq.n 80013b4 <HAL_DMA_Abort_IT+0x9c>
{
/* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
/* disable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
800139a: 687b ldr r3, [r7, #4]
800139c: 6d1b ldr r3, [r3, #80] @ 0x50
800139e: 681a ldr r2, [r3, #0]
80013a0: 687b ldr r3, [r7, #4]
80013a2: 6d1b ldr r3, [r3, #80] @ 0x50
80013a4: 490f ldr r1, [pc, #60] @ (80013e4 <HAL_DMA_Abort_IT+0xcc>)
80013a6: 400a ands r2, r1
80013a8: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80013aa: 687b ldr r3, [r7, #4]
80013ac: 6d5b ldr r3, [r3, #84] @ 0x54
80013ae: 687a ldr r2, [r7, #4]
80013b0: 6d92 ldr r2, [r2, #88] @ 0x58
80013b2: 605a str r2, [r3, #4]
}
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
80013b4: 687b ldr r3, [r7, #4]
80013b6: 2225 movs r2, #37 @ 0x25
80013b8: 2101 movs r1, #1
80013ba: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80013bc: 687b ldr r3, [r7, #4]
80013be: 2224 movs r2, #36 @ 0x24
80013c0: 2100 movs r1, #0
80013c2: 5499 strb r1, [r3, r2]
/* Call User Abort callback */
if (hdma->XferAbortCallback != NULL)
80013c4: 687b ldr r3, [r7, #4]
80013c6: 6b9b ldr r3, [r3, #56] @ 0x38
80013c8: 2b00 cmp r3, #0
80013ca: d004 beq.n 80013d6 <HAL_DMA_Abort_IT+0xbe>
{
hdma->XferAbortCallback(hdma);
80013cc: 687b ldr r3, [r7, #4]
80013ce: 6b9b ldr r3, [r3, #56] @ 0x38
80013d0: 687a ldr r2, [r7, #4]
80013d2: 0010 movs r0, r2
80013d4: 4798 blx r3
}
}
return status;
80013d6: 230f movs r3, #15
80013d8: 18fb adds r3, r7, r3
80013da: 781b ldrb r3, [r3, #0]
}
80013dc: 0018 movs r0, r3
80013de: 46bd mov sp, r7
80013e0: b004 add sp, #16
80013e2: bd80 pop {r7, pc}
80013e4: fffffeff .word 0xfffffeff
80013e8: 40020000 .word 0x40020000
080013ec <HAL_DMA_GetState>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
80013ec: b580 push {r7, lr}
80013ee: b082 sub sp, #8
80013f0: af00 add r7, sp, #0
80013f2: 6078 str r0, [r7, #4]
/* Return DMA handle state */
return hdma->State;
80013f4: 687b ldr r3, [r7, #4]
80013f6: 2225 movs r2, #37 @ 0x25
80013f8: 5c9b ldrb r3, [r3, r2]
80013fa: b2db uxtb r3, r3
}
80013fc: 0018 movs r0, r3
80013fe: 46bd mov sp, r7
8001400: b002 add sp, #8
8001402: bd80 pop {r7, pc}
08001404 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001404: b580 push {r7, lr}
8001406: b086 sub sp, #24
8001408: af00 add r7, sp, #0
800140a: 6078 str r0, [r7, #4]
800140c: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800140e: 2300 movs r3, #0
8001410: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001412: e147 b.n 80016a4 <HAL_GPIO_Init+0x2a0>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001414: 683b ldr r3, [r7, #0]
8001416: 681b ldr r3, [r3, #0]
8001418: 2101 movs r1, #1
800141a: 697a ldr r2, [r7, #20]
800141c: 4091 lsls r1, r2
800141e: 000a movs r2, r1
8001420: 4013 ands r3, r2
8001422: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001424: 68fb ldr r3, [r7, #12]
8001426: 2b00 cmp r3, #0
8001428: d100 bne.n 800142c <HAL_GPIO_Init+0x28>
800142a: e138 b.n 800169e <HAL_GPIO_Init+0x29a>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
800142c: 683b ldr r3, [r7, #0]
800142e: 685b ldr r3, [r3, #4]
8001430: 2203 movs r2, #3
8001432: 4013 ands r3, r2
8001434: 2b01 cmp r3, #1
8001436: d005 beq.n 8001444 <HAL_GPIO_Init+0x40>
8001438: 683b ldr r3, [r7, #0]
800143a: 685b ldr r3, [r3, #4]
800143c: 2203 movs r2, #3
800143e: 4013 ands r3, r2
8001440: 2b02 cmp r3, #2
8001442: d130 bne.n 80014a6 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001444: 687b ldr r3, [r7, #4]
8001446: 689b ldr r3, [r3, #8]
8001448: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
800144a: 697b ldr r3, [r7, #20]
800144c: 005b lsls r3, r3, #1
800144e: 2203 movs r2, #3
8001450: 409a lsls r2, r3
8001452: 0013 movs r3, r2
8001454: 43da mvns r2, r3
8001456: 693b ldr r3, [r7, #16]
8001458: 4013 ands r3, r2
800145a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
800145c: 683b ldr r3, [r7, #0]
800145e: 68da ldr r2, [r3, #12]
8001460: 697b ldr r3, [r7, #20]
8001462: 005b lsls r3, r3, #1
8001464: 409a lsls r2, r3
8001466: 0013 movs r3, r2
8001468: 693a ldr r2, [r7, #16]
800146a: 4313 orrs r3, r2
800146c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800146e: 687b ldr r3, [r7, #4]
8001470: 693a ldr r2, [r7, #16]
8001472: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001474: 687b ldr r3, [r7, #4]
8001476: 685b ldr r3, [r3, #4]
8001478: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
800147a: 2201 movs r2, #1
800147c: 697b ldr r3, [r7, #20]
800147e: 409a lsls r2, r3
8001480: 0013 movs r3, r2
8001482: 43da mvns r2, r3
8001484: 693b ldr r3, [r7, #16]
8001486: 4013 ands r3, r2
8001488: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800148a: 683b ldr r3, [r7, #0]
800148c: 685b ldr r3, [r3, #4]
800148e: 091b lsrs r3, r3, #4
8001490: 2201 movs r2, #1
8001492: 401a ands r2, r3
8001494: 697b ldr r3, [r7, #20]
8001496: 409a lsls r2, r3
8001498: 0013 movs r3, r2
800149a: 693a ldr r2, [r7, #16]
800149c: 4313 orrs r3, r2
800149e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80014a0: 687b ldr r3, [r7, #4]
80014a2: 693a ldr r2, [r7, #16]
80014a4: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80014a6: 683b ldr r3, [r7, #0]
80014a8: 685b ldr r3, [r3, #4]
80014aa: 2203 movs r2, #3
80014ac: 4013 ands r3, r2
80014ae: 2b03 cmp r3, #3
80014b0: d017 beq.n 80014e2 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80014b2: 687b ldr r3, [r7, #4]
80014b4: 68db ldr r3, [r3, #12]
80014b6: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
80014b8: 697b ldr r3, [r7, #20]
80014ba: 005b lsls r3, r3, #1
80014bc: 2203 movs r2, #3
80014be: 409a lsls r2, r3
80014c0: 0013 movs r3, r2
80014c2: 43da mvns r2, r3
80014c4: 693b ldr r3, [r7, #16]
80014c6: 4013 ands r3, r2
80014c8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
80014ca: 683b ldr r3, [r7, #0]
80014cc: 689a ldr r2, [r3, #8]
80014ce: 697b ldr r3, [r7, #20]
80014d0: 005b lsls r3, r3, #1
80014d2: 409a lsls r2, r3
80014d4: 0013 movs r3, r2
80014d6: 693a ldr r2, [r7, #16]
80014d8: 4313 orrs r3, r2
80014da: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
80014dc: 687b ldr r3, [r7, #4]
80014de: 693a ldr r2, [r7, #16]
80014e0: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80014e2: 683b ldr r3, [r7, #0]
80014e4: 685b ldr r3, [r3, #4]
80014e6: 2203 movs r2, #3
80014e8: 4013 ands r3, r2
80014ea: 2b02 cmp r3, #2
80014ec: d123 bne.n 8001536 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
80014ee: 697b ldr r3, [r7, #20]
80014f0: 08da lsrs r2, r3, #3
80014f2: 687b ldr r3, [r7, #4]
80014f4: 3208 adds r2, #8
80014f6: 0092 lsls r2, r2, #2
80014f8: 58d3 ldr r3, [r2, r3]
80014fa: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
80014fc: 697b ldr r3, [r7, #20]
80014fe: 2207 movs r2, #7
8001500: 4013 ands r3, r2
8001502: 009b lsls r3, r3, #2
8001504: 220f movs r2, #15
8001506: 409a lsls r2, r3
8001508: 0013 movs r3, r2
800150a: 43da mvns r2, r3
800150c: 693b ldr r3, [r7, #16]
800150e: 4013 ands r3, r2
8001510: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001512: 683b ldr r3, [r7, #0]
8001514: 691a ldr r2, [r3, #16]
8001516: 697b ldr r3, [r7, #20]
8001518: 2107 movs r1, #7
800151a: 400b ands r3, r1
800151c: 009b lsls r3, r3, #2
800151e: 409a lsls r2, r3
8001520: 0013 movs r3, r2
8001522: 693a ldr r2, [r7, #16]
8001524: 4313 orrs r3, r2
8001526: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001528: 697b ldr r3, [r7, #20]
800152a: 08da lsrs r2, r3, #3
800152c: 687b ldr r3, [r7, #4]
800152e: 3208 adds r2, #8
8001530: 0092 lsls r2, r2, #2
8001532: 6939 ldr r1, [r7, #16]
8001534: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001536: 687b ldr r3, [r7, #4]
8001538: 681b ldr r3, [r3, #0]
800153a: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
800153c: 697b ldr r3, [r7, #20]
800153e: 005b lsls r3, r3, #1
8001540: 2203 movs r2, #3
8001542: 409a lsls r2, r3
8001544: 0013 movs r3, r2
8001546: 43da mvns r2, r3
8001548: 693b ldr r3, [r7, #16]
800154a: 4013 ands r3, r2
800154c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
800154e: 683b ldr r3, [r7, #0]
8001550: 685b ldr r3, [r3, #4]
8001552: 2203 movs r2, #3
8001554: 401a ands r2, r3
8001556: 697b ldr r3, [r7, #20]
8001558: 005b lsls r3, r3, #1
800155a: 409a lsls r2, r3
800155c: 0013 movs r3, r2
800155e: 693a ldr r2, [r7, #16]
8001560: 4313 orrs r3, r2
8001562: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001564: 687b ldr r3, [r7, #4]
8001566: 693a ldr r2, [r7, #16]
8001568: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
800156a: 683b ldr r3, [r7, #0]
800156c: 685a ldr r2, [r3, #4]
800156e: 23c0 movs r3, #192 @ 0xc0
8001570: 029b lsls r3, r3, #10
8001572: 4013 ands r3, r2
8001574: d100 bne.n 8001578 <HAL_GPIO_Init+0x174>
8001576: e092 b.n 800169e <HAL_GPIO_Init+0x29a>
{
temp = EXTI->EXTICR[position >> 2u];
8001578: 4a50 ldr r2, [pc, #320] @ (80016bc <HAL_GPIO_Init+0x2b8>)
800157a: 697b ldr r3, [r7, #20]
800157c: 089b lsrs r3, r3, #2
800157e: 3318 adds r3, #24
8001580: 009b lsls r3, r3, #2
8001582: 589b ldr r3, [r3, r2]
8001584: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (8u * (position & 0x03u)));
8001586: 697b ldr r3, [r7, #20]
8001588: 2203 movs r2, #3
800158a: 4013 ands r3, r2
800158c: 00db lsls r3, r3, #3
800158e: 220f movs r2, #15
8001590: 409a lsls r2, r3
8001592: 0013 movs r3, r2
8001594: 43da mvns r2, r3
8001596: 693b ldr r3, [r7, #16]
8001598: 4013 ands r3, r2
800159a: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)));
800159c: 687a ldr r2, [r7, #4]
800159e: 23a0 movs r3, #160 @ 0xa0
80015a0: 05db lsls r3, r3, #23
80015a2: 429a cmp r2, r3
80015a4: d013 beq.n 80015ce <HAL_GPIO_Init+0x1ca>
80015a6: 687b ldr r3, [r7, #4]
80015a8: 4a45 ldr r2, [pc, #276] @ (80016c0 <HAL_GPIO_Init+0x2bc>)
80015aa: 4293 cmp r3, r2
80015ac: d00d beq.n 80015ca <HAL_GPIO_Init+0x1c6>
80015ae: 687b ldr r3, [r7, #4]
80015b0: 4a44 ldr r2, [pc, #272] @ (80016c4 <HAL_GPIO_Init+0x2c0>)
80015b2: 4293 cmp r3, r2
80015b4: d007 beq.n 80015c6 <HAL_GPIO_Init+0x1c2>
80015b6: 687b ldr r3, [r7, #4]
80015b8: 4a43 ldr r2, [pc, #268] @ (80016c8 <HAL_GPIO_Init+0x2c4>)
80015ba: 4293 cmp r3, r2
80015bc: d101 bne.n 80015c2 <HAL_GPIO_Init+0x1be>
80015be: 2303 movs r3, #3
80015c0: e006 b.n 80015d0 <HAL_GPIO_Init+0x1cc>
80015c2: 2305 movs r3, #5
80015c4: e004 b.n 80015d0 <HAL_GPIO_Init+0x1cc>
80015c6: 2302 movs r3, #2
80015c8: e002 b.n 80015d0 <HAL_GPIO_Init+0x1cc>
80015ca: 2301 movs r3, #1
80015cc: e000 b.n 80015d0 <HAL_GPIO_Init+0x1cc>
80015ce: 2300 movs r3, #0
80015d0: 697a ldr r2, [r7, #20]
80015d2: 2103 movs r1, #3
80015d4: 400a ands r2, r1
80015d6: 00d2 lsls r2, r2, #3
80015d8: 4093 lsls r3, r2
80015da: 693a ldr r2, [r7, #16]
80015dc: 4313 orrs r3, r2
80015de: 613b str r3, [r7, #16]
EXTI->EXTICR[position >> 2u] = temp;
80015e0: 4936 ldr r1, [pc, #216] @ (80016bc <HAL_GPIO_Init+0x2b8>)
80015e2: 697b ldr r3, [r7, #20]
80015e4: 089b lsrs r3, r3, #2
80015e6: 3318 adds r3, #24
80015e8: 009b lsls r3, r3, #2
80015ea: 693a ldr r2, [r7, #16]
80015ec: 505a str r2, [r3, r1]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
80015ee: 4b33 ldr r3, [pc, #204] @ (80016bc <HAL_GPIO_Init+0x2b8>)
80015f0: 681b ldr r3, [r3, #0]
80015f2: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
80015f4: 68fb ldr r3, [r7, #12]
80015f6: 43da mvns r2, r3
80015f8: 693b ldr r3, [r7, #16]
80015fa: 4013 ands r3, r2
80015fc: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
80015fe: 683b ldr r3, [r7, #0]
8001600: 685a ldr r2, [r3, #4]
8001602: 2380 movs r3, #128 @ 0x80
8001604: 035b lsls r3, r3, #13
8001606: 4013 ands r3, r2
8001608: d003 beq.n 8001612 <HAL_GPIO_Init+0x20e>
{
temp |= iocurrent;
800160a: 693a ldr r2, [r7, #16]
800160c: 68fb ldr r3, [r7, #12]
800160e: 4313 orrs r3, r2
8001610: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8001612: 4b2a ldr r3, [pc, #168] @ (80016bc <HAL_GPIO_Init+0x2b8>)
8001614: 693a ldr r2, [r7, #16]
8001616: 601a str r2, [r3, #0]
temp = EXTI->FTSR1;
8001618: 4b28 ldr r3, [pc, #160] @ (80016bc <HAL_GPIO_Init+0x2b8>)
800161a: 685b ldr r3, [r3, #4]
800161c: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800161e: 68fb ldr r3, [r7, #12]
8001620: 43da mvns r2, r3
8001622: 693b ldr r3, [r7, #16]
8001624: 4013 ands r3, r2
8001626: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001628: 683b ldr r3, [r7, #0]
800162a: 685a ldr r2, [r3, #4]
800162c: 2380 movs r3, #128 @ 0x80
800162e: 039b lsls r3, r3, #14
8001630: 4013 ands r3, r2
8001632: d003 beq.n 800163c <HAL_GPIO_Init+0x238>
{
temp |= iocurrent;
8001634: 693a ldr r2, [r7, #16]
8001636: 68fb ldr r3, [r7, #12]
8001638: 4313 orrs r3, r2
800163a: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
800163c: 4b1f ldr r3, [pc, #124] @ (80016bc <HAL_GPIO_Init+0x2b8>)
800163e: 693a ldr r2, [r7, #16]
8001640: 605a str r2, [r3, #4]
/* Clear EXTI line configuration */
temp = EXTI->EMR1;
8001642: 4a1e ldr r2, [pc, #120] @ (80016bc <HAL_GPIO_Init+0x2b8>)
8001644: 2384 movs r3, #132 @ 0x84
8001646: 58d3 ldr r3, [r2, r3]
8001648: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
800164a: 68fb ldr r3, [r7, #12]
800164c: 43da mvns r2, r3
800164e: 693b ldr r3, [r7, #16]
8001650: 4013 ands r3, r2
8001652: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001654: 683b ldr r3, [r7, #0]
8001656: 685a ldr r2, [r3, #4]
8001658: 2380 movs r3, #128 @ 0x80
800165a: 029b lsls r3, r3, #10
800165c: 4013 ands r3, r2
800165e: d003 beq.n 8001668 <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
8001660: 693a ldr r2, [r7, #16]
8001662: 68fb ldr r3, [r7, #12]
8001664: 4313 orrs r3, r2
8001666: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8001668: 4914 ldr r1, [pc, #80] @ (80016bc <HAL_GPIO_Init+0x2b8>)
800166a: 2284 movs r2, #132 @ 0x84
800166c: 693b ldr r3, [r7, #16]
800166e: 508b str r3, [r1, r2]
temp = EXTI->IMR1;
8001670: 4a12 ldr r2, [pc, #72] @ (80016bc <HAL_GPIO_Init+0x2b8>)
8001672: 2380 movs r3, #128 @ 0x80
8001674: 58d3 ldr r3, [r2, r3]
8001676: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001678: 68fb ldr r3, [r7, #12]
800167a: 43da mvns r2, r3
800167c: 693b ldr r3, [r7, #16]
800167e: 4013 ands r3, r2
8001680: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001682: 683b ldr r3, [r7, #0]
8001684: 685a ldr r2, [r3, #4]
8001686: 2380 movs r3, #128 @ 0x80
8001688: 025b lsls r3, r3, #9
800168a: 4013 ands r3, r2
800168c: d003 beq.n 8001696 <HAL_GPIO_Init+0x292>
{
temp |= iocurrent;
800168e: 693a ldr r2, [r7, #16]
8001690: 68fb ldr r3, [r7, #12]
8001692: 4313 orrs r3, r2
8001694: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8001696: 4909 ldr r1, [pc, #36] @ (80016bc <HAL_GPIO_Init+0x2b8>)
8001698: 2280 movs r2, #128 @ 0x80
800169a: 693b ldr r3, [r7, #16]
800169c: 508b str r3, [r1, r2]
}
}
position++;
800169e: 697b ldr r3, [r7, #20]
80016a0: 3301 adds r3, #1
80016a2: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
80016a4: 683b ldr r3, [r7, #0]
80016a6: 681a ldr r2, [r3, #0]
80016a8: 697b ldr r3, [r7, #20]
80016aa: 40da lsrs r2, r3
80016ac: 1e13 subs r3, r2, #0
80016ae: d000 beq.n 80016b2 <HAL_GPIO_Init+0x2ae>
80016b0: e6b0 b.n 8001414 <HAL_GPIO_Init+0x10>
}
}
80016b2: 46c0 nop @ (mov r8, r8)
80016b4: 46c0 nop @ (mov r8, r8)
80016b6: 46bd mov sp, r7
80016b8: b006 add sp, #24
80016ba: bd80 pop {r7, pc}
80016bc: 40021800 .word 0x40021800
80016c0: 50000400 .word 0x50000400
80016c4: 50000800 .word 0x50000800
80016c8: 50000c00 .word 0x50000c00
080016cc <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
80016cc: b580 push {r7, lr}
80016ce: b084 sub sp, #16
80016d0: af00 add r7, sp, #0
80016d2: 6078 str r0, [r7, #4]
80016d4: 000a movs r2, r1
80016d6: 1cbb adds r3, r7, #2
80016d8: 801a strh r2, [r3, #0]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
80016da: 687b ldr r3, [r7, #4]
80016dc: 691b ldr r3, [r3, #16]
80016de: 1cba adds r2, r7, #2
80016e0: 8812 ldrh r2, [r2, #0]
80016e2: 4013 ands r3, r2
80016e4: d004 beq.n 80016f0 <HAL_GPIO_ReadPin+0x24>
{
bitstatus = GPIO_PIN_SET;
80016e6: 230f movs r3, #15
80016e8: 18fb adds r3, r7, r3
80016ea: 2201 movs r2, #1
80016ec: 701a strb r2, [r3, #0]
80016ee: e003 b.n 80016f8 <HAL_GPIO_ReadPin+0x2c>
}
else
{
bitstatus = GPIO_PIN_RESET;
80016f0: 230f movs r3, #15
80016f2: 18fb adds r3, r7, r3
80016f4: 2200 movs r2, #0
80016f6: 701a strb r2, [r3, #0]
}
return bitstatus;
80016f8: 230f movs r3, #15
80016fa: 18fb adds r3, r7, r3
80016fc: 781b ldrb r3, [r3, #0]
}
80016fe: 0018 movs r0, r3
8001700: 46bd mov sp, r7
8001702: b004 add sp, #16
8001704: bd80 pop {r7, pc}
08001706 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001706: b580 push {r7, lr}
8001708: b082 sub sp, #8
800170a: af00 add r7, sp, #0
800170c: 6078 str r0, [r7, #4]
800170e: 0008 movs r0, r1
8001710: 0011 movs r1, r2
8001712: 1cbb adds r3, r7, #2
8001714: 1c02 adds r2, r0, #0
8001716: 801a strh r2, [r3, #0]
8001718: 1c7b adds r3, r7, #1
800171a: 1c0a adds r2, r1, #0
800171c: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
800171e: 1c7b adds r3, r7, #1
8001720: 781b ldrb r3, [r3, #0]
8001722: 2b00 cmp r3, #0
8001724: d004 beq.n 8001730 <HAL_GPIO_WritePin+0x2a>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001726: 1cbb adds r3, r7, #2
8001728: 881a ldrh r2, [r3, #0]
800172a: 687b ldr r3, [r7, #4]
800172c: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800172e: e003 b.n 8001738 <HAL_GPIO_WritePin+0x32>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001730: 1cbb adds r3, r7, #2
8001732: 881a ldrh r2, [r3, #0]
8001734: 687b ldr r3, [r7, #4]
8001736: 629a str r2, [r3, #40] @ 0x28
}
8001738: 46c0 nop @ (mov r8, r8)
800173a: 46bd mov sp, r7
800173c: b002 add sp, #8
800173e: bd80 pop {r7, pc}
08001740 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8001740: b580 push {r7, lr}
8001742: b082 sub sp, #8
8001744: af00 add r7, sp, #0
8001746: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
8001748: 687b ldr r3, [r7, #4]
800174a: 2b00 cmp r3, #0
800174c: d101 bne.n 8001752 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800174e: 2301 movs r3, #1
8001750: e08f b.n 8001872 <HAL_I2C_Init+0x132>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8001752: 687b ldr r3, [r7, #4]
8001754: 2241 movs r2, #65 @ 0x41
8001756: 5c9b ldrb r3, [r3, r2]
8001758: b2db uxtb r3, r3
800175a: 2b00 cmp r3, #0
800175c: d107 bne.n 800176e <HAL_I2C_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
800175e: 687b ldr r3, [r7, #4]
8001760: 2240 movs r2, #64 @ 0x40
8001762: 2100 movs r1, #0
8001764: 5499 strb r1, [r3, r2]
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
8001766: 687b ldr r3, [r7, #4]
8001768: 0018 movs r0, r3
800176a: f7ff fb2f bl 8000dcc <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
800176e: 687b ldr r3, [r7, #4]
8001770: 2241 movs r2, #65 @ 0x41
8001772: 2124 movs r1, #36 @ 0x24
8001774: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8001776: 687b ldr r3, [r7, #4]
8001778: 681b ldr r3, [r3, #0]
800177a: 681a ldr r2, [r3, #0]
800177c: 687b ldr r3, [r7, #4]
800177e: 681b ldr r3, [r3, #0]
8001780: 2101 movs r1, #1
8001782: 438a bics r2, r1
8001784: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
8001786: 687b ldr r3, [r7, #4]
8001788: 685a ldr r2, [r3, #4]
800178a: 687b ldr r3, [r7, #4]
800178c: 681b ldr r3, [r3, #0]
800178e: 493b ldr r1, [pc, #236] @ (800187c <HAL_I2C_Init+0x13c>)
8001790: 400a ands r2, r1
8001792: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
8001794: 687b ldr r3, [r7, #4]
8001796: 681b ldr r3, [r3, #0]
8001798: 689a ldr r2, [r3, #8]
800179a: 687b ldr r3, [r7, #4]
800179c: 681b ldr r3, [r3, #0]
800179e: 4938 ldr r1, [pc, #224] @ (8001880 <HAL_I2C_Init+0x140>)
80017a0: 400a ands r2, r1
80017a2: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
80017a4: 687b ldr r3, [r7, #4]
80017a6: 68db ldr r3, [r3, #12]
80017a8: 2b01 cmp r3, #1
80017aa: d108 bne.n 80017be <HAL_I2C_Init+0x7e>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
80017ac: 687b ldr r3, [r7, #4]
80017ae: 689a ldr r2, [r3, #8]
80017b0: 687b ldr r3, [r7, #4]
80017b2: 681b ldr r3, [r3, #0]
80017b4: 2180 movs r1, #128 @ 0x80
80017b6: 0209 lsls r1, r1, #8
80017b8: 430a orrs r2, r1
80017ba: 609a str r2, [r3, #8]
80017bc: e007 b.n 80017ce <HAL_I2C_Init+0x8e>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
80017be: 687b ldr r3, [r7, #4]
80017c0: 689a ldr r2, [r3, #8]
80017c2: 687b ldr r3, [r7, #4]
80017c4: 681b ldr r3, [r3, #0]
80017c6: 2184 movs r1, #132 @ 0x84
80017c8: 0209 lsls r1, r1, #8
80017ca: 430a orrs r2, r1
80017cc: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
80017ce: 687b ldr r3, [r7, #4]
80017d0: 68db ldr r3, [r3, #12]
80017d2: 2b02 cmp r3, #2
80017d4: d109 bne.n 80017ea <HAL_I2C_Init+0xaa>
{
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
80017d6: 687b ldr r3, [r7, #4]
80017d8: 681b ldr r3, [r3, #0]
80017da: 685a ldr r2, [r3, #4]
80017dc: 687b ldr r3, [r7, #4]
80017de: 681b ldr r3, [r3, #0]
80017e0: 2180 movs r1, #128 @ 0x80
80017e2: 0109 lsls r1, r1, #4
80017e4: 430a orrs r2, r1
80017e6: 605a str r2, [r3, #4]
80017e8: e007 b.n 80017fa <HAL_I2C_Init+0xba>
}
else
{
/* Clear the I2C ADD10 bit */
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
80017ea: 687b ldr r3, [r7, #4]
80017ec: 681b ldr r3, [r3, #0]
80017ee: 685a ldr r2, [r3, #4]
80017f0: 687b ldr r3, [r7, #4]
80017f2: 681b ldr r3, [r3, #0]
80017f4: 4923 ldr r1, [pc, #140] @ (8001884 <HAL_I2C_Init+0x144>)
80017f6: 400a ands r2, r1
80017f8: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
80017fa: 687b ldr r3, [r7, #4]
80017fc: 681b ldr r3, [r3, #0]
80017fe: 685a ldr r2, [r3, #4]
8001800: 687b ldr r3, [r7, #4]
8001802: 681b ldr r3, [r3, #0]
8001804: 4920 ldr r1, [pc, #128] @ (8001888 <HAL_I2C_Init+0x148>)
8001806: 430a orrs r2, r1
8001808: 605a str r2, [r3, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
800180a: 687b ldr r3, [r7, #4]
800180c: 681b ldr r3, [r3, #0]
800180e: 68da ldr r2, [r3, #12]
8001810: 687b ldr r3, [r7, #4]
8001812: 681b ldr r3, [r3, #0]
8001814: 491a ldr r1, [pc, #104] @ (8001880 <HAL_I2C_Init+0x140>)
8001816: 400a ands r2, r1
8001818: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
800181a: 687b ldr r3, [r7, #4]
800181c: 691a ldr r2, [r3, #16]
800181e: 687b ldr r3, [r7, #4]
8001820: 695b ldr r3, [r3, #20]
8001822: 431a orrs r2, r3
8001824: 0011 movs r1, r2
(hi2c->Init.OwnAddress2Masks << 8));
8001826: 687b ldr r3, [r7, #4]
8001828: 699b ldr r3, [r3, #24]
800182a: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
800182c: 687b ldr r3, [r7, #4]
800182e: 681b ldr r3, [r3, #0]
8001830: 430a orrs r2, r1
8001832: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
8001834: 687b ldr r3, [r7, #4]
8001836: 69d9 ldr r1, [r3, #28]
8001838: 687b ldr r3, [r7, #4]
800183a: 6a1a ldr r2, [r3, #32]
800183c: 687b ldr r3, [r7, #4]
800183e: 681b ldr r3, [r3, #0]
8001840: 430a orrs r2, r1
8001842: 601a str r2, [r3, #0]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8001844: 687b ldr r3, [r7, #4]
8001846: 681b ldr r3, [r3, #0]
8001848: 681a ldr r2, [r3, #0]
800184a: 687b ldr r3, [r7, #4]
800184c: 681b ldr r3, [r3, #0]
800184e: 2101 movs r1, #1
8001850: 430a orrs r2, r1
8001852: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001854: 687b ldr r3, [r7, #4]
8001856: 2200 movs r2, #0
8001858: 645a str r2, [r3, #68] @ 0x44
hi2c->State = HAL_I2C_STATE_READY;
800185a: 687b ldr r3, [r7, #4]
800185c: 2241 movs r2, #65 @ 0x41
800185e: 2120 movs r1, #32
8001860: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8001862: 687b ldr r3, [r7, #4]
8001864: 2200 movs r2, #0
8001866: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8001868: 687b ldr r3, [r7, #4]
800186a: 2242 movs r2, #66 @ 0x42
800186c: 2100 movs r1, #0
800186e: 5499 strb r1, [r3, r2]
return HAL_OK;
8001870: 2300 movs r3, #0
}
8001872: 0018 movs r0, r3
8001874: 46bd mov sp, r7
8001876: b002 add sp, #8
8001878: bd80 pop {r7, pc}
800187a: 46c0 nop @ (mov r8, r8)
800187c: f0ffffff .word 0xf0ffffff
8001880: ffff7fff .word 0xffff7fff
8001884: fffff7ff .word 0xfffff7ff
8001888: 02008000 .word 0x02008000
0800188c <HAL_I2C_Slave_Seq_Transmit_IT>:
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
800188c: b580 push {r7, lr}
800188e: b086 sub sp, #24
8001890: af00 add r7, sp, #0
8001892: 60f8 str r0, [r7, #12]
8001894: 60b9 str r1, [r7, #8]
8001896: 603b str r3, [r7, #0]
8001898: 1dbb adds r3, r7, #6
800189a: 801a strh r2, [r3, #0]
FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
800189c: 68fb ldr r3, [r7, #12]
800189e: 2241 movs r2, #65 @ 0x41
80018a0: 5c9b ldrb r3, [r3, r2]
80018a2: b2db uxtb r3, r3
80018a4: 001a movs r2, r3
80018a6: 2328 movs r3, #40 @ 0x28
80018a8: 4013 ands r3, r2
80018aa: 2b28 cmp r3, #40 @ 0x28
80018ac: d000 beq.n 80018b0 <HAL_I2C_Slave_Seq_Transmit_IT+0x24>
80018ae: e09f b.n 80019f0 <HAL_I2C_Slave_Seq_Transmit_IT+0x164>
{
if ((pData == NULL) || (Size == 0U))
80018b0: 68bb ldr r3, [r7, #8]
80018b2: 2b00 cmp r3, #0
80018b4: d003 beq.n 80018be <HAL_I2C_Slave_Seq_Transmit_IT+0x32>
80018b6: 1dbb adds r3, r7, #6
80018b8: 881b ldrh r3, [r3, #0]
80018ba: 2b00 cmp r3, #0
80018bc: d105 bne.n 80018ca <HAL_I2C_Slave_Seq_Transmit_IT+0x3e>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
80018be: 68fb ldr r3, [r7, #12]
80018c0: 2280 movs r2, #128 @ 0x80
80018c2: 0092 lsls r2, r2, #2
80018c4: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
80018c6: 2301 movs r3, #1
80018c8: e093 b.n 80019f2 <HAL_I2C_Slave_Seq_Transmit_IT+0x166>
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
80018ca: 4a4c ldr r2, [pc, #304] @ (80019fc <HAL_I2C_Slave_Seq_Transmit_IT+0x170>)
80018cc: 68fb ldr r3, [r7, #12]
80018ce: 0011 movs r1, r2
80018d0: 0018 movs r0, r3
80018d2: f001 fc5b bl 800318c <I2C_Disable_IRQ>
/* Process Locked */
__HAL_LOCK(hi2c);
80018d6: 68fb ldr r3, [r7, #12]
80018d8: 2240 movs r2, #64 @ 0x40
80018da: 5c9b ldrb r3, [r3, r2]
80018dc: 2b01 cmp r3, #1
80018de: d101 bne.n 80018e4 <HAL_I2C_Slave_Seq_Transmit_IT+0x58>
80018e0: 2302 movs r3, #2
80018e2: e086 b.n 80019f2 <HAL_I2C_Slave_Seq_Transmit_IT+0x166>
80018e4: 68fb ldr r3, [r7, #12]
80018e6: 2240 movs r2, #64 @ 0x40
80018e8: 2101 movs r1, #1
80018ea: 5499 strb r1, [r3, r2]
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
80018ec: 68fb ldr r3, [r7, #12]
80018ee: 2241 movs r2, #65 @ 0x41
80018f0: 5c9b ldrb r3, [r3, r2]
80018f2: b2db uxtb r3, r3
80018f4: 2b2a cmp r3, #42 @ 0x2a
80018f6: d12c bne.n 8001952 <HAL_I2C_Slave_Seq_Transmit_IT+0xc6>
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
80018f8: 68fb ldr r3, [r7, #12]
80018fa: 2102 movs r1, #2
80018fc: 0018 movs r0, r3
80018fe: f001 fc45 bl 800318c <I2C_Disable_IRQ>
/* Abort DMA Xfer if any */
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
8001902: 68fb ldr r3, [r7, #12]
8001904: 681b ldr r3, [r3, #0]
8001906: 681a ldr r2, [r3, #0]
8001908: 2380 movs r3, #128 @ 0x80
800190a: 021b lsls r3, r3, #8
800190c: 401a ands r2, r3
800190e: 2380 movs r3, #128 @ 0x80
8001910: 021b lsls r3, r3, #8
8001912: 429a cmp r2, r3
8001914: d11d bne.n 8001952 <HAL_I2C_Slave_Seq_Transmit_IT+0xc6>
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8001916: 68fb ldr r3, [r7, #12]
8001918: 681b ldr r3, [r3, #0]
800191a: 681a ldr r2, [r3, #0]
800191c: 68fb ldr r3, [r7, #12]
800191e: 681b ldr r3, [r3, #0]
8001920: 4937 ldr r1, [pc, #220] @ (8001a00 <HAL_I2C_Slave_Seq_Transmit_IT+0x174>)
8001922: 400a ands r2, r1
8001924: 601a str r2, [r3, #0]
if (hi2c->hdmarx != NULL)
8001926: 68fb ldr r3, [r7, #12]
8001928: 6bdb ldr r3, [r3, #60] @ 0x3c
800192a: 2b00 cmp r3, #0
800192c: d011 beq.n 8001952 <HAL_I2C_Slave_Seq_Transmit_IT+0xc6>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
800192e: 68fb ldr r3, [r7, #12]
8001930: 6bdb ldr r3, [r3, #60] @ 0x3c
8001932: 4a34 ldr r2, [pc, #208] @ (8001a04 <HAL_I2C_Slave_Seq_Transmit_IT+0x178>)
8001934: 639a str r2, [r3, #56] @ 0x38
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
8001936: 68fb ldr r3, [r7, #12]
8001938: 6bdb ldr r3, [r3, #60] @ 0x3c
800193a: 0018 movs r0, r3
800193c: f7ff fcec bl 8001318 <HAL_DMA_Abort_IT>
8001940: 1e03 subs r3, r0, #0
8001942: d006 beq.n 8001952 <HAL_I2C_Slave_Seq_Transmit_IT+0xc6>
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
8001944: 68fb ldr r3, [r7, #12]
8001946: 6bdb ldr r3, [r3, #60] @ 0x3c
8001948: 6b9a ldr r2, [r3, #56] @ 0x38
800194a: 68fb ldr r3, [r7, #12]
800194c: 6bdb ldr r3, [r3, #60] @ 0x3c
800194e: 0018 movs r0, r3
8001950: 4790 blx r2
}
}
}
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
8001952: 68fb ldr r3, [r7, #12]
8001954: 2241 movs r2, #65 @ 0x41
8001956: 2129 movs r1, #41 @ 0x29
8001958: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_SLAVE;
800195a: 68fb ldr r3, [r7, #12]
800195c: 2242 movs r2, #66 @ 0x42
800195e: 2120 movs r1, #32
8001960: 5499 strb r1, [r3, r2]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001962: 68fb ldr r3, [r7, #12]
8001964: 2200 movs r2, #0
8001966: 645a str r2, [r3, #68] @ 0x44
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
8001968: 68fb ldr r3, [r7, #12]
800196a: 681b ldr r3, [r3, #0]
800196c: 685a ldr r2, [r3, #4]
800196e: 68fb ldr r3, [r7, #12]
8001970: 681b ldr r3, [r3, #0]
8001972: 4923 ldr r1, [pc, #140] @ (8001a00 <HAL_I2C_Slave_Seq_Transmit_IT+0x174>)
8001974: 400a ands r2, r1
8001976: 605a str r2, [r3, #4]
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8001978: 68fb ldr r3, [r7, #12]
800197a: 68ba ldr r2, [r7, #8]
800197c: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
800197e: 68fb ldr r3, [r7, #12]
8001980: 1dba adds r2, r7, #6
8001982: 8812 ldrh r2, [r2, #0]
8001984: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8001986: 68fb ldr r3, [r7, #12]
8001988: 8d5b ldrh r3, [r3, #42] @ 0x2a
800198a: b29a uxth r2, r3
800198c: 68fb ldr r3, [r7, #12]
800198e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = XferOptions;
8001990: 68fb ldr r3, [r7, #12]
8001992: 683a ldr r2, [r7, #0]
8001994: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferISR = I2C_Slave_ISR_IT;
8001996: 68fb ldr r3, [r7, #12]
8001998: 4a1b ldr r2, [pc, #108] @ (8001a08 <HAL_I2C_Slave_Seq_Transmit_IT+0x17c>)
800199a: 635a str r2, [r3, #52] @ 0x34
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
800199c: 68fb ldr r3, [r7, #12]
800199e: 681b ldr r3, [r3, #0]
80019a0: 699b ldr r3, [r3, #24]
80019a2: 2208 movs r2, #8
80019a4: 4013 ands r3, r2
80019a6: 3b08 subs r3, #8
80019a8: 425a negs r2, r3
80019aa: 4153 adcs r3, r2
80019ac: b2da uxtb r2, r3
80019ae: 2117 movs r1, #23
80019b0: 187b adds r3, r7, r1
80019b2: 701a strb r2, [r3, #0]
if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
80019b4: 68fb ldr r3, [r7, #12]
80019b6: 681b ldr r3, [r3, #0]
80019b8: 699b ldr r3, [r3, #24]
80019ba: 0c1b lsrs r3, r3, #16
80019bc: b2db uxtb r3, r3
80019be: 2201 movs r2, #1
80019c0: 4013 ands r3, r2
80019c2: b2db uxtb r3, r3
80019c4: 2b01 cmp r3, #1
80019c6: d107 bne.n 80019d8 <HAL_I2C_Slave_Seq_Transmit_IT+0x14c>
80019c8: 187b adds r3, r7, r1
80019ca: 781b ldrb r3, [r3, #0]
80019cc: 2b00 cmp r3, #0
80019ce: d003 beq.n 80019d8 <HAL_I2C_Slave_Seq_Transmit_IT+0x14c>
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
80019d0: 68fb ldr r3, [r7, #12]
80019d2: 681b ldr r3, [r3, #0]
80019d4: 2208 movs r2, #8
80019d6: 61da str r2, [r3, #28]
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80019d8: 68fb ldr r3, [r7, #12]
80019da: 2240 movs r2, #64 @ 0x40
80019dc: 2100 movs r1, #0
80019de: 5499 strb r1, [r3, r2]
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
80019e0: 4a06 ldr r2, [pc, #24] @ (80019fc <HAL_I2C_Slave_Seq_Transmit_IT+0x170>)
80019e2: 68fb ldr r3, [r7, #12]
80019e4: 0011 movs r1, r2
80019e6: 0018 movs r0, r3
80019e8: f001 fb46 bl 8003078 <I2C_Enable_IRQ>
return HAL_OK;
80019ec: 2300 movs r3, #0
80019ee: e000 b.n 80019f2 <HAL_I2C_Slave_Seq_Transmit_IT+0x166>
}
else
{
return HAL_ERROR;
80019f0: 2301 movs r3, #1
}
}
80019f2: 0018 movs r0, r3
80019f4: 46bd mov sp, r7
80019f6: b006 add sp, #24
80019f8: bd80 pop {r7, pc}
80019fa: 46c0 nop @ (mov r8, r8)
80019fc: 00008001 .word 0x00008001
8001a00: ffff7fff .word 0xffff7fff
8001a04: 08002fc7 .word 0x08002fc7
8001a08: 08001d1d .word 0x08001d1d
08001a0c <HAL_I2C_Slave_Seq_Receive_IT>:
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions)
{
8001a0c: b580 push {r7, lr}
8001a0e: b086 sub sp, #24
8001a10: af00 add r7, sp, #0
8001a12: 60f8 str r0, [r7, #12]
8001a14: 60b9 str r1, [r7, #8]
8001a16: 603b str r3, [r7, #0]
8001a18: 1dbb adds r3, r7, #6
8001a1a: 801a strh r2, [r3, #0]
FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
8001a1c: 68fb ldr r3, [r7, #12]
8001a1e: 2241 movs r2, #65 @ 0x41
8001a20: 5c9b ldrb r3, [r3, r2]
8001a22: b2db uxtb r3, r3
8001a24: 001a movs r2, r3
8001a26: 2328 movs r3, #40 @ 0x28
8001a28: 4013 ands r3, r2
8001a2a: 2b28 cmp r3, #40 @ 0x28
8001a2c: d000 beq.n 8001a30 <HAL_I2C_Slave_Seq_Receive_IT+0x24>
8001a2e: e09f b.n 8001b70 <HAL_I2C_Slave_Seq_Receive_IT+0x164>
{
if ((pData == NULL) || (Size == 0U))
8001a30: 68bb ldr r3, [r7, #8]
8001a32: 2b00 cmp r3, #0
8001a34: d003 beq.n 8001a3e <HAL_I2C_Slave_Seq_Receive_IT+0x32>
8001a36: 1dbb adds r3, r7, #6
8001a38: 881b ldrh r3, [r3, #0]
8001a3a: 2b00 cmp r3, #0
8001a3c: d105 bne.n 8001a4a <HAL_I2C_Slave_Seq_Receive_IT+0x3e>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
8001a3e: 68fb ldr r3, [r7, #12]
8001a40: 2280 movs r2, #128 @ 0x80
8001a42: 0092 lsls r2, r2, #2
8001a44: 645a str r2, [r3, #68] @ 0x44
return HAL_ERROR;
8001a46: 2301 movs r3, #1
8001a48: e093 b.n 8001b72 <HAL_I2C_Slave_Seq_Receive_IT+0x166>
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
8001a4a: 4a4c ldr r2, [pc, #304] @ (8001b7c <HAL_I2C_Slave_Seq_Receive_IT+0x170>)
8001a4c: 68fb ldr r3, [r7, #12]
8001a4e: 0011 movs r1, r2
8001a50: 0018 movs r0, r3
8001a52: f001 fb9b bl 800318c <I2C_Disable_IRQ>
/* Process Locked */
__HAL_LOCK(hi2c);
8001a56: 68fb ldr r3, [r7, #12]
8001a58: 2240 movs r2, #64 @ 0x40
8001a5a: 5c9b ldrb r3, [r3, r2]
8001a5c: 2b01 cmp r3, #1
8001a5e: d101 bne.n 8001a64 <HAL_I2C_Slave_Seq_Receive_IT+0x58>
8001a60: 2302 movs r3, #2
8001a62: e086 b.n 8001b72 <HAL_I2C_Slave_Seq_Receive_IT+0x166>
8001a64: 68fb ldr r3, [r7, #12]
8001a66: 2240 movs r2, #64 @ 0x40
8001a68: 2101 movs r1, #1
8001a6a: 5499 strb r1, [r3, r2]
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
8001a6c: 68fb ldr r3, [r7, #12]
8001a6e: 2241 movs r2, #65 @ 0x41
8001a70: 5c9b ldrb r3, [r3, r2]
8001a72: b2db uxtb r3, r3
8001a74: 2b29 cmp r3, #41 @ 0x29
8001a76: d12c bne.n 8001ad2 <HAL_I2C_Slave_Seq_Receive_IT+0xc6>
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8001a78: 68fb ldr r3, [r7, #12]
8001a7a: 2101 movs r1, #1
8001a7c: 0018 movs r0, r3
8001a7e: f001 fb85 bl 800318c <I2C_Disable_IRQ>
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
8001a82: 68fb ldr r3, [r7, #12]
8001a84: 681b ldr r3, [r3, #0]
8001a86: 681a ldr r2, [r3, #0]
8001a88: 2380 movs r3, #128 @ 0x80
8001a8a: 01db lsls r3, r3, #7
8001a8c: 401a ands r2, r3
8001a8e: 2380 movs r3, #128 @ 0x80
8001a90: 01db lsls r3, r3, #7
8001a92: 429a cmp r2, r3
8001a94: d11d bne.n 8001ad2 <HAL_I2C_Slave_Seq_Receive_IT+0xc6>
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8001a96: 68fb ldr r3, [r7, #12]
8001a98: 681b ldr r3, [r3, #0]
8001a9a: 681a ldr r2, [r3, #0]
8001a9c: 68fb ldr r3, [r7, #12]
8001a9e: 681b ldr r3, [r3, #0]
8001aa0: 4937 ldr r1, [pc, #220] @ (8001b80 <HAL_I2C_Slave_Seq_Receive_IT+0x174>)
8001aa2: 400a ands r2, r1
8001aa4: 601a str r2, [r3, #0]
/* Abort DMA Xfer if any */
if (hi2c->hdmatx != NULL)
8001aa6: 68fb ldr r3, [r7, #12]
8001aa8: 6b9b ldr r3, [r3, #56] @ 0x38
8001aaa: 2b00 cmp r3, #0
8001aac: d011 beq.n 8001ad2 <HAL_I2C_Slave_Seq_Receive_IT+0xc6>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
8001aae: 68fb ldr r3, [r7, #12]
8001ab0: 6b9b ldr r3, [r3, #56] @ 0x38
8001ab2: 4a34 ldr r2, [pc, #208] @ (8001b84 <HAL_I2C_Slave_Seq_Receive_IT+0x178>)
8001ab4: 639a str r2, [r3, #56] @ 0x38
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
8001ab6: 68fb ldr r3, [r7, #12]
8001ab8: 6b9b ldr r3, [r3, #56] @ 0x38
8001aba: 0018 movs r0, r3
8001abc: f7ff fc2c bl 8001318 <HAL_DMA_Abort_IT>
8001ac0: 1e03 subs r3, r0, #0
8001ac2: d006 beq.n 8001ad2 <HAL_I2C_Slave_Seq_Receive_IT+0xc6>
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
8001ac4: 68fb ldr r3, [r7, #12]
8001ac6: 6b9b ldr r3, [r3, #56] @ 0x38
8001ac8: 6b9a ldr r2, [r3, #56] @ 0x38
8001aca: 68fb ldr r3, [r7, #12]
8001acc: 6b9b ldr r3, [r3, #56] @ 0x38
8001ace: 0018 movs r0, r3
8001ad0: 4790 blx r2
}
}
}
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
8001ad2: 68fb ldr r3, [r7, #12]
8001ad4: 2241 movs r2, #65 @ 0x41
8001ad6: 212a movs r1, #42 @ 0x2a
8001ad8: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_SLAVE;
8001ada: 68fb ldr r3, [r7, #12]
8001adc: 2242 movs r2, #66 @ 0x42
8001ade: 2120 movs r1, #32
8001ae0: 5499 strb r1, [r3, r2]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001ae2: 68fb ldr r3, [r7, #12]
8001ae4: 2200 movs r2, #0
8001ae6: 645a str r2, [r3, #68] @ 0x44
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
8001ae8: 68fb ldr r3, [r7, #12]
8001aea: 681b ldr r3, [r3, #0]
8001aec: 685a ldr r2, [r3, #4]
8001aee: 68fb ldr r3, [r7, #12]
8001af0: 681b ldr r3, [r3, #0]
8001af2: 4925 ldr r1, [pc, #148] @ (8001b88 <HAL_I2C_Slave_Seq_Receive_IT+0x17c>)
8001af4: 400a ands r2, r1
8001af6: 605a str r2, [r3, #4]
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
8001af8: 68fb ldr r3, [r7, #12]
8001afa: 68ba ldr r2, [r7, #8]
8001afc: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount = Size;
8001afe: 68fb ldr r3, [r7, #12]
8001b00: 1dba adds r2, r7, #6
8001b02: 8812 ldrh r2, [r2, #0]
8001b04: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize = hi2c->XferCount;
8001b06: 68fb ldr r3, [r7, #12]
8001b08: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001b0a: b29a uxth r2, r3
8001b0c: 68fb ldr r3, [r7, #12]
8001b0e: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferOptions = XferOptions;
8001b10: 68fb ldr r3, [r7, #12]
8001b12: 683a ldr r2, [r7, #0]
8001b14: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferISR = I2C_Slave_ISR_IT;
8001b16: 68fb ldr r3, [r7, #12]
8001b18: 4a1c ldr r2, [pc, #112] @ (8001b8c <HAL_I2C_Slave_Seq_Receive_IT+0x180>)
8001b1a: 635a str r2, [r3, #52] @ 0x34
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
8001b1c: 68fb ldr r3, [r7, #12]
8001b1e: 681b ldr r3, [r3, #0]
8001b20: 699b ldr r3, [r3, #24]
8001b22: 2208 movs r2, #8
8001b24: 4013 ands r3, r2
8001b26: 3b08 subs r3, #8
8001b28: 425a negs r2, r3
8001b2a: 4153 adcs r3, r2
8001b2c: b2da uxtb r2, r3
8001b2e: 2117 movs r1, #23
8001b30: 187b adds r3, r7, r1
8001b32: 701a strb r2, [r3, #0]
if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
8001b34: 68fb ldr r3, [r7, #12]
8001b36: 681b ldr r3, [r3, #0]
8001b38: 699b ldr r3, [r3, #24]
8001b3a: 0c1b lsrs r3, r3, #16
8001b3c: b2db uxtb r3, r3
8001b3e: 2201 movs r2, #1
8001b40: 4013 ands r3, r2
8001b42: b2db uxtb r3, r3
8001b44: 2b00 cmp r3, #0
8001b46: d107 bne.n 8001b58 <HAL_I2C_Slave_Seq_Receive_IT+0x14c>
8001b48: 187b adds r3, r7, r1
8001b4a: 781b ldrb r3, [r3, #0]
8001b4c: 2b00 cmp r3, #0
8001b4e: d003 beq.n 8001b58 <HAL_I2C_Slave_Seq_Receive_IT+0x14c>
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
8001b50: 68fb ldr r3, [r7, #12]
8001b52: 681b ldr r3, [r3, #0]
8001b54: 2208 movs r2, #8
8001b56: 61da str r2, [r3, #28]
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001b58: 68fb ldr r3, [r7, #12]
8001b5a: 2240 movs r2, #64 @ 0x40
8001b5c: 2100 movs r1, #0
8001b5e: 5499 strb r1, [r3, r2]
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
8001b60: 4a06 ldr r2, [pc, #24] @ (8001b7c <HAL_I2C_Slave_Seq_Receive_IT+0x170>)
8001b62: 68fb ldr r3, [r7, #12]
8001b64: 0011 movs r1, r2
8001b66: 0018 movs r0, r3
8001b68: f001 fa86 bl 8003078 <I2C_Enable_IRQ>
return HAL_OK;
8001b6c: 2300 movs r3, #0
8001b6e: e000 b.n 8001b72 <HAL_I2C_Slave_Seq_Receive_IT+0x166>
}
else
{
return HAL_ERROR;
8001b70: 2301 movs r3, #1
}
}
8001b72: 0018 movs r0, r3
8001b74: 46bd mov sp, r7
8001b76: b006 add sp, #24
8001b78: bd80 pop {r7, pc}
8001b7a: 46c0 nop @ (mov r8, r8)
8001b7c: 00008002 .word 0x00008002
8001b80: ffffbfff .word 0xffffbfff
8001b84: 08002fc7 .word 0x08002fc7
8001b88: ffff7fff .word 0xffff7fff
8001b8c: 08001d1d .word 0x08001d1d
08001b90 <HAL_I2C_EnableListen_IT>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
{
8001b90: b580 push {r7, lr}
8001b92: b082 sub sp, #8
8001b94: af00 add r7, sp, #0
8001b96: 6078 str r0, [r7, #4]
if (hi2c->State == HAL_I2C_STATE_READY)
8001b98: 687b ldr r3, [r7, #4]
8001b9a: 2241 movs r2, #65 @ 0x41
8001b9c: 5c9b ldrb r3, [r3, r2]
8001b9e: b2db uxtb r3, r3
8001ba0: 2b20 cmp r3, #32
8001ba2: d10f bne.n 8001bc4 <HAL_I2C_EnableListen_IT+0x34>
{
hi2c->State = HAL_I2C_STATE_LISTEN;
8001ba4: 687b ldr r3, [r7, #4]
8001ba6: 2241 movs r2, #65 @ 0x41
8001ba8: 2128 movs r1, #40 @ 0x28
8001baa: 5499 strb r1, [r3, r2]
hi2c->XferISR = I2C_Slave_ISR_IT;
8001bac: 687b ldr r3, [r7, #4]
8001bae: 4a08 ldr r2, [pc, #32] @ (8001bd0 <HAL_I2C_EnableListen_IT+0x40>)
8001bb0: 635a str r2, [r3, #52] @ 0x34
/* Enable the Address Match interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
8001bb2: 2380 movs r3, #128 @ 0x80
8001bb4: 021a lsls r2, r3, #8
8001bb6: 687b ldr r3, [r7, #4]
8001bb8: 0011 movs r1, r2
8001bba: 0018 movs r0, r3
8001bbc: f001 fa5c bl 8003078 <I2C_Enable_IRQ>
return HAL_OK;
8001bc0: 2300 movs r3, #0
8001bc2: e000 b.n 8001bc6 <HAL_I2C_EnableListen_IT+0x36>
}
else
{
return HAL_BUSY;
8001bc4: 2302 movs r3, #2
}
}
8001bc6: 0018 movs r0, r3
8001bc8: 46bd mov sp, r7
8001bca: b002 add sp, #8
8001bcc: bd80 pop {r7, pc}
8001bce: 46c0 nop @ (mov r8, r8)
8001bd0: 08001d1d .word 0x08001d1d
08001bd4 <HAL_I2C_EV_IRQHandler>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
8001bd4: b580 push {r7, lr}
8001bd6: b084 sub sp, #16
8001bd8: af00 add r7, sp, #0
8001bda: 6078 str r0, [r7, #4]
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
8001bdc: 687b ldr r3, [r7, #4]
8001bde: 681b ldr r3, [r3, #0]
8001be0: 699b ldr r3, [r3, #24]
8001be2: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
8001be4: 687b ldr r3, [r7, #4]
8001be6: 681b ldr r3, [r3, #0]
8001be8: 681b ldr r3, [r3, #0]
8001bea: 60bb str r3, [r7, #8]
/* I2C events treatment -------------------------------------*/
if (hi2c->XferISR != NULL)
8001bec: 687b ldr r3, [r7, #4]
8001bee: 6b5b ldr r3, [r3, #52] @ 0x34
8001bf0: 2b00 cmp r3, #0
8001bf2: d005 beq.n 8001c00 <HAL_I2C_EV_IRQHandler+0x2c>
{
hi2c->XferISR(hi2c, itflags, itsources);
8001bf4: 687b ldr r3, [r7, #4]
8001bf6: 6b5b ldr r3, [r3, #52] @ 0x34
8001bf8: 68ba ldr r2, [r7, #8]
8001bfa: 68f9 ldr r1, [r7, #12]
8001bfc: 6878 ldr r0, [r7, #4]
8001bfe: 4798 blx r3
}
}
8001c00: 46c0 nop @ (mov r8, r8)
8001c02: 46bd mov sp, r7
8001c04: b004 add sp, #16
8001c06: bd80 pop {r7, pc}
08001c08 <HAL_I2C_ER_IRQHandler>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
8001c08: b580 push {r7, lr}
8001c0a: b086 sub sp, #24
8001c0c: af00 add r7, sp, #0
8001c0e: 6078 str r0, [r7, #4]
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
8001c10: 687b ldr r3, [r7, #4]
8001c12: 681b ldr r3, [r3, #0]
8001c14: 699b ldr r3, [r3, #24]
8001c16: 617b str r3, [r7, #20]
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
8001c18: 687b ldr r3, [r7, #4]
8001c1a: 681b ldr r3, [r3, #0]
8001c1c: 681b ldr r3, [r3, #0]
8001c1e: 613b str r3, [r7, #16]
uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
8001c20: 697a ldr r2, [r7, #20]
8001c22: 2380 movs r3, #128 @ 0x80
8001c24: 005b lsls r3, r3, #1
8001c26: 4013 ands r3, r2
8001c28: d00e beq.n 8001c48 <HAL_I2C_ER_IRQHandler+0x40>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
8001c2a: 693b ldr r3, [r7, #16]
8001c2c: 2280 movs r2, #128 @ 0x80
8001c2e: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
8001c30: d00a beq.n 8001c48 <HAL_I2C_ER_IRQHandler+0x40>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
8001c32: 687b ldr r3, [r7, #4]
8001c34: 6c5b ldr r3, [r3, #68] @ 0x44
8001c36: 2201 movs r2, #1
8001c38: 431a orrs r2, r3
8001c3a: 687b ldr r3, [r7, #4]
8001c3c: 645a str r2, [r3, #68] @ 0x44
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 681b ldr r3, [r3, #0]
8001c42: 2280 movs r2, #128 @ 0x80
8001c44: 0052 lsls r2, r2, #1
8001c46: 61da str r2, [r3, #28]
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
8001c48: 697a ldr r2, [r7, #20]
8001c4a: 2380 movs r3, #128 @ 0x80
8001c4c: 00db lsls r3, r3, #3
8001c4e: 4013 ands r3, r2
8001c50: d00e beq.n 8001c70 <HAL_I2C_ER_IRQHandler+0x68>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
8001c52: 693b ldr r3, [r7, #16]
8001c54: 2280 movs r2, #128 @ 0x80
8001c56: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
8001c58: d00a beq.n 8001c70 <HAL_I2C_ER_IRQHandler+0x68>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
8001c5a: 687b ldr r3, [r7, #4]
8001c5c: 6c5b ldr r3, [r3, #68] @ 0x44
8001c5e: 2208 movs r2, #8
8001c60: 431a orrs r2, r3
8001c62: 687b ldr r3, [r7, #4]
8001c64: 645a str r2, [r3, #68] @ 0x44
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
8001c66: 687b ldr r3, [r7, #4]
8001c68: 681b ldr r3, [r3, #0]
8001c6a: 2280 movs r2, #128 @ 0x80
8001c6c: 00d2 lsls r2, r2, #3
8001c6e: 61da str r2, [r3, #28]
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
8001c70: 697a ldr r2, [r7, #20]
8001c72: 2380 movs r3, #128 @ 0x80
8001c74: 009b lsls r3, r3, #2
8001c76: 4013 ands r3, r2
8001c78: d00e beq.n 8001c98 <HAL_I2C_ER_IRQHandler+0x90>
(I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
8001c7a: 693b ldr r3, [r7, #16]
8001c7c: 2280 movs r2, #128 @ 0x80
8001c7e: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
8001c80: d00a beq.n 8001c98 <HAL_I2C_ER_IRQHandler+0x90>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
8001c82: 687b ldr r3, [r7, #4]
8001c84: 6c5b ldr r3, [r3, #68] @ 0x44
8001c86: 2202 movs r2, #2
8001c88: 431a orrs r2, r3
8001c8a: 687b ldr r3, [r7, #4]
8001c8c: 645a str r2, [r3, #68] @ 0x44
/* Clear ARLO flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
8001c8e: 687b ldr r3, [r7, #4]
8001c90: 681b ldr r3, [r3, #0]
8001c92: 2280 movs r2, #128 @ 0x80
8001c94: 0092 lsls r2, r2, #2
8001c96: 61da str r2, [r3, #28]
}
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
8001c98: 687b ldr r3, [r7, #4]
8001c9a: 6c5b ldr r3, [r3, #68] @ 0x44
8001c9c: 60fb str r3, [r7, #12]
/* Call the Error Callback in case of Error detected */
if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
8001c9e: 68fb ldr r3, [r7, #12]
8001ca0: 220b movs r2, #11
8001ca2: 4013 ands r3, r2
8001ca4: d005 beq.n 8001cb2 <HAL_I2C_ER_IRQHandler+0xaa>
{
I2C_ITError(hi2c, tmperror);
8001ca6: 68fa ldr r2, [r7, #12]
8001ca8: 687b ldr r3, [r7, #4]
8001caa: 0011 movs r1, r2
8001cac: 0018 movs r0, r3
8001cae: f001 f83d bl 8002d2c <I2C_ITError>
}
}
8001cb2: 46c0 nop @ (mov r8, r8)
8001cb4: 46bd mov sp, r7
8001cb6: b006 add sp, #24
8001cb8: bd80 pop {r7, pc}
08001cba <HAL_I2C_MasterTxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8001cba: b580 push {r7, lr}
8001cbc: b082 sub sp, #8
8001cbe: af00 add r7, sp, #0
8001cc0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
*/
}
8001cc2: 46c0 nop @ (mov r8, r8)
8001cc4: 46bd mov sp, r7
8001cc6: b002 add sp, #8
8001cc8: bd80 pop {r7, pc}
08001cca <HAL_I2C_MasterRxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8001cca: b580 push {r7, lr}
8001ccc: b082 sub sp, #8
8001cce: af00 add r7, sp, #0
8001cd0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
*/
}
8001cd2: 46c0 nop @ (mov r8, r8)
8001cd4: 46bd mov sp, r7
8001cd6: b002 add sp, #8
8001cd8: bd80 pop {r7, pc}
08001cda <HAL_I2C_MemTxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8001cda: b580 push {r7, lr}
8001cdc: b082 sub sp, #8
8001cde: af00 add r7, sp, #0
8001ce0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemTxCpltCallback could be implemented in the user file
*/
}
8001ce2: 46c0 nop @ (mov r8, r8)
8001ce4: 46bd mov sp, r7
8001ce6: b002 add sp, #8
8001ce8: bd80 pop {r7, pc}
08001cea <HAL_I2C_MemRxCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
{
8001cea: b580 push {r7, lr}
8001cec: b082 sub sp, #8
8001cee: af00 add r7, sp, #0
8001cf0: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_MemRxCpltCallback could be implemented in the user file
*/
}
8001cf2: 46c0 nop @ (mov r8, r8)
8001cf4: 46bd mov sp, r7
8001cf6: b002 add sp, #8
8001cf8: bd80 pop {r7, pc}
08001cfa <HAL_I2C_ErrorCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
8001cfa: b580 push {r7, lr}
8001cfc: b082 sub sp, #8
8001cfe: af00 add r7, sp, #0
8001d00: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_ErrorCallback could be implemented in the user file
*/
}
8001d02: 46c0 nop @ (mov r8, r8)
8001d04: 46bd mov sp, r7
8001d06: b002 add sp, #8
8001d08: bd80 pop {r7, pc}
08001d0a <HAL_I2C_AbortCpltCallback>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval None
*/
__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
{
8001d0a: b580 push {r7, lr}
8001d0c: b082 sub sp, #8
8001d0e: af00 add r7, sp, #0
8001d10: 6078 str r0, [r7, #4]
UNUSED(hi2c);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2C_AbortCpltCallback could be implemented in the user file
*/
}
8001d12: 46c0 nop @ (mov r8, r8)
8001d14: 46bd mov sp, r7
8001d16: b002 add sp, #8
8001d18: bd80 pop {r7, pc}
...
08001d1c <I2C_Slave_ISR_IT>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
8001d1c: b580 push {r7, lr}
8001d1e: b086 sub sp, #24
8001d20: af00 add r7, sp, #0
8001d22: 60f8 str r0, [r7, #12]
8001d24: 60b9 str r1, [r7, #8]
8001d26: 607a str r2, [r7, #4]
uint32_t tmpoptions = hi2c->XferOptions;
8001d28: 68fb ldr r3, [r7, #12]
8001d2a: 6adb ldr r3, [r3, #44] @ 0x2c
8001d2c: 617b str r3, [r7, #20]
uint32_t tmpITFlags = ITFlags;
8001d2e: 68bb ldr r3, [r7, #8]
8001d30: 613b str r3, [r7, #16]
/* Process locked */
__HAL_LOCK(hi2c);
8001d32: 68fb ldr r3, [r7, #12]
8001d34: 2240 movs r2, #64 @ 0x40
8001d36: 5c9b ldrb r3, [r3, r2]
8001d38: 2b01 cmp r3, #1
8001d3a: d101 bne.n 8001d40 <I2C_Slave_ISR_IT+0x24>
8001d3c: 2302 movs r3, #2
8001d3e: e0e7 b.n 8001f10 <I2C_Slave_ISR_IT+0x1f4>
8001d40: 68fb ldr r3, [r7, #12]
8001d42: 2240 movs r2, #64 @ 0x40
8001d44: 2101 movs r1, #1
8001d46: 5499 strb r1, [r3, r2]
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
8001d48: 693b ldr r3, [r7, #16]
8001d4a: 2220 movs r2, #32
8001d4c: 4013 ands r3, r2
8001d4e: d00a beq.n 8001d66 <I2C_Slave_ISR_IT+0x4a>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
8001d50: 687b ldr r3, [r7, #4]
8001d52: 2220 movs r2, #32
8001d54: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
8001d56: d006 beq.n 8001d66 <I2C_Slave_ISR_IT+0x4a>
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
8001d58: 693a ldr r2, [r7, #16]
8001d5a: 68fb ldr r3, [r7, #12]
8001d5c: 0011 movs r1, r2
8001d5e: 0018 movs r0, r3
8001d60: f000 fe04 bl 800296c <I2C_ITSlaveCplt>
8001d64: e0cf b.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8001d66: 693b ldr r3, [r7, #16]
8001d68: 2210 movs r2, #16
8001d6a: 4013 ands r3, r2
8001d6c: d052 beq.n 8001e14 <I2C_Slave_ISR_IT+0xf8>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 2210 movs r2, #16
8001d72: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8001d74: d04e beq.n 8001e14 <I2C_Slave_ISR_IT+0xf8>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
8001d76: 68fb ldr r3, [r7, #12]
8001d78: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001d7a: b29b uxth r3, r3
8001d7c: 2b00 cmp r3, #0
8001d7e: d12d bne.n 8001ddc <I2C_Slave_ISR_IT+0xc0>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
8001d80: 68fb ldr r3, [r7, #12]
8001d82: 2241 movs r2, #65 @ 0x41
8001d84: 5c9b ldrb r3, [r3, r2]
8001d86: b2db uxtb r3, r3
8001d88: 2b28 cmp r3, #40 @ 0x28
8001d8a: d10b bne.n 8001da4 <I2C_Slave_ISR_IT+0x88>
8001d8c: 697a ldr r2, [r7, #20]
8001d8e: 2380 movs r3, #128 @ 0x80
8001d90: 049b lsls r3, r3, #18
8001d92: 429a cmp r2, r3
8001d94: d106 bne.n 8001da4 <I2C_Slave_ISR_IT+0x88>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
8001d96: 693a ldr r2, [r7, #16]
8001d98: 68fb ldr r3, [r7, #12]
8001d9a: 0011 movs r1, r2
8001d9c: 0018 movs r0, r3
8001d9e: f000 ff6d bl 8002c7c <I2C_ITListenCplt>
8001da2: e036 b.n 8001e12 <I2C_Slave_ISR_IT+0xf6>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
8001da4: 68fb ldr r3, [r7, #12]
8001da6: 2241 movs r2, #65 @ 0x41
8001da8: 5c9b ldrb r3, [r3, r2]
8001daa: b2db uxtb r3, r3
8001dac: 2b29 cmp r3, #41 @ 0x29
8001dae: d110 bne.n 8001dd2 <I2C_Slave_ISR_IT+0xb6>
8001db0: 697b ldr r3, [r7, #20]
8001db2: 4a59 ldr r2, [pc, #356] @ (8001f18 <I2C_Slave_ISR_IT+0x1fc>)
8001db4: 4293 cmp r3, r2
8001db6: d00c beq.n 8001dd2 <I2C_Slave_ISR_IT+0xb6>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001db8: 68fb ldr r3, [r7, #12]
8001dba: 681b ldr r3, [r3, #0]
8001dbc: 2210 movs r2, #16
8001dbe: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8001dc0: 68fb ldr r3, [r7, #12]
8001dc2: 0018 movs r0, r3
8001dc4: f001 f8dd bl 8002f82 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8001dc8: 68fb ldr r3, [r7, #12]
8001dca: 0018 movs r0, r3
8001dcc: f000 fc9c bl 8002708 <I2C_ITSlaveSeqCplt>
8001dd0: e01f b.n 8001e12 <I2C_Slave_ISR_IT+0xf6>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001dd2: 68fb ldr r3, [r7, #12]
8001dd4: 681b ldr r3, [r3, #0]
8001dd6: 2210 movs r2, #16
8001dd8: 61da str r2, [r3, #28]
if (hi2c->XferCount == 0U)
8001dda: e091 b.n 8001f00 <I2C_Slave_ISR_IT+0x1e4>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001ddc: 68fb ldr r3, [r7, #12]
8001dde: 681b ldr r3, [r3, #0]
8001de0: 2210 movs r2, #16
8001de2: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8001de4: 68fb ldr r3, [r7, #12]
8001de6: 6c5b ldr r3, [r3, #68] @ 0x44
8001de8: 2204 movs r2, #4
8001dea: 431a orrs r2, r3
8001dec: 68fb ldr r3, [r7, #12]
8001dee: 645a str r2, [r3, #68] @ 0x44
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
8001df0: 697b ldr r3, [r7, #20]
8001df2: 2b00 cmp r3, #0
8001df4: d005 beq.n 8001e02 <I2C_Slave_ISR_IT+0xe6>
8001df6: 697a ldr r2, [r7, #20]
8001df8: 2380 movs r3, #128 @ 0x80
8001dfa: 045b lsls r3, r3, #17
8001dfc: 429a cmp r2, r3
8001dfe: d000 beq.n 8001e02 <I2C_Slave_ISR_IT+0xe6>
8001e00: e07e b.n 8001f00 <I2C_Slave_ISR_IT+0x1e4>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
8001e02: 68fb ldr r3, [r7, #12]
8001e04: 6c5a ldr r2, [r3, #68] @ 0x44
8001e06: 68fb ldr r3, [r7, #12]
8001e08: 0011 movs r1, r2
8001e0a: 0018 movs r0, r3
8001e0c: f000 ff8e bl 8002d2c <I2C_ITError>
if (hi2c->XferCount == 0U)
8001e10: e076 b.n 8001f00 <I2C_Slave_ISR_IT+0x1e4>
8001e12: e075 b.n 8001f00 <I2C_Slave_ISR_IT+0x1e4>
}
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
8001e14: 693b ldr r3, [r7, #16]
8001e16: 2204 movs r2, #4
8001e18: 4013 ands r3, r2
8001e1a: d02f beq.n 8001e7c <I2C_Slave_ISR_IT+0x160>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
8001e1c: 687b ldr r3, [r7, #4]
8001e1e: 2204 movs r2, #4
8001e20: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
8001e22: d02b beq.n 8001e7c <I2C_Slave_ISR_IT+0x160>
{
if (hi2c->XferCount > 0U)
8001e24: 68fb ldr r3, [r7, #12]
8001e26: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001e28: b29b uxth r3, r3
8001e2a: 2b00 cmp r3, #0
8001e2c: d018 beq.n 8001e60 <I2C_Slave_ISR_IT+0x144>
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8001e2e: 68fb ldr r3, [r7, #12]
8001e30: 681b ldr r3, [r3, #0]
8001e32: 6a5a ldr r2, [r3, #36] @ 0x24
8001e34: 68fb ldr r3, [r7, #12]
8001e36: 6a5b ldr r3, [r3, #36] @ 0x24
8001e38: b2d2 uxtb r2, r2
8001e3a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8001e3c: 68fb ldr r3, [r7, #12]
8001e3e: 6a5b ldr r3, [r3, #36] @ 0x24
8001e40: 1c5a adds r2, r3, #1
8001e42: 68fb ldr r3, [r7, #12]
8001e44: 625a str r2, [r3, #36] @ 0x24
hi2c->XferSize--;
8001e46: 68fb ldr r3, [r7, #12]
8001e48: 8d1b ldrh r3, [r3, #40] @ 0x28
8001e4a: 3b01 subs r3, #1
8001e4c: b29a uxth r2, r3
8001e4e: 68fb ldr r3, [r7, #12]
8001e50: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8001e52: 68fb ldr r3, [r7, #12]
8001e54: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001e56: b29b uxth r3, r3
8001e58: 3b01 subs r3, #1
8001e5a: b29a uxth r2, r3
8001e5c: 68fb ldr r3, [r7, #12]
8001e5e: 855a strh r2, [r3, #42] @ 0x2a
}
if ((hi2c->XferCount == 0U) && \
8001e60: 68fb ldr r3, [r7, #12]
8001e62: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001e64: b29b uxth r3, r3
8001e66: 2b00 cmp r3, #0
8001e68: d14c bne.n 8001f04 <I2C_Slave_ISR_IT+0x1e8>
8001e6a: 697b ldr r3, [r7, #20]
8001e6c: 4a2a ldr r2, [pc, #168] @ (8001f18 <I2C_Slave_ISR_IT+0x1fc>)
8001e6e: 4293 cmp r3, r2
8001e70: d048 beq.n 8001f04 <I2C_Slave_ISR_IT+0x1e8>
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8001e72: 68fb ldr r3, [r7, #12]
8001e74: 0018 movs r0, r3
8001e76: f000 fc47 bl 8002708 <I2C_ITSlaveSeqCplt>
if ((hi2c->XferCount == 0U) && \
8001e7a: e043 b.n 8001f04 <I2C_Slave_ISR_IT+0x1e8>
}
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
8001e7c: 693b ldr r3, [r7, #16]
8001e7e: 2208 movs r2, #8
8001e80: 4013 ands r3, r2
8001e82: d00a beq.n 8001e9a <I2C_Slave_ISR_IT+0x17e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
8001e84: 687b ldr r3, [r7, #4]
8001e86: 2208 movs r2, #8
8001e88: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
8001e8a: d006 beq.n 8001e9a <I2C_Slave_ISR_IT+0x17e>
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
8001e8c: 693a ldr r2, [r7, #16]
8001e8e: 68fb ldr r3, [r7, #12]
8001e90: 0011 movs r1, r2
8001e92: 0018 movs r0, r3
8001e94: f000 fb52 bl 800253c <I2C_ITAddrCplt>
8001e98: e035 b.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
}
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
8001e9a: 693b ldr r3, [r7, #16]
8001e9c: 2202 movs r2, #2
8001e9e: 4013 ands r3, r2
8001ea0: d031 beq.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 2202 movs r2, #2
8001ea6: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
8001ea8: d02d beq.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
8001eaa: 68fb ldr r3, [r7, #12]
8001eac: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001eae: b29b uxth r3, r3
8001eb0: 2b00 cmp r3, #0
8001eb2: d018 beq.n 8001ee6 <I2C_Slave_ISR_IT+0x1ca>
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
8001eb4: 68fb ldr r3, [r7, #12]
8001eb6: 6a5b ldr r3, [r3, #36] @ 0x24
8001eb8: 781a ldrb r2, [r3, #0]
8001eba: 68fb ldr r3, [r7, #12]
8001ebc: 681b ldr r3, [r3, #0]
8001ebe: 629a str r2, [r3, #40] @ 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8001ec0: 68fb ldr r3, [r7, #12]
8001ec2: 6a5b ldr r3, [r3, #36] @ 0x24
8001ec4: 1c5a adds r2, r3, #1
8001ec6: 68fb ldr r3, [r7, #12]
8001ec8: 625a str r2, [r3, #36] @ 0x24
hi2c->XferCount--;
8001eca: 68fb ldr r3, [r7, #12]
8001ecc: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001ece: b29b uxth r3, r3
8001ed0: 3b01 subs r3, #1
8001ed2: b29a uxth r2, r3
8001ed4: 68fb ldr r3, [r7, #12]
8001ed6: 855a strh r2, [r3, #42] @ 0x2a
hi2c->XferSize--;
8001ed8: 68fb ldr r3, [r7, #12]
8001eda: 8d1b ldrh r3, [r3, #40] @ 0x28
8001edc: 3b01 subs r3, #1
8001ede: b29a uxth r2, r3
8001ee0: 68fb ldr r3, [r7, #12]
8001ee2: 851a strh r2, [r3, #40] @ 0x28
8001ee4: e00f b.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
}
else
{
if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
8001ee6: 697a ldr r2, [r7, #20]
8001ee8: 2380 movs r3, #128 @ 0x80
8001eea: 045b lsls r3, r3, #17
8001eec: 429a cmp r2, r3
8001eee: d002 beq.n 8001ef6 <I2C_Slave_ISR_IT+0x1da>
8001ef0: 697b ldr r3, [r7, #20]
8001ef2: 2b00 cmp r3, #0
8001ef4: d107 bne.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8001ef6: 68fb ldr r3, [r7, #12]
8001ef8: 0018 movs r0, r3
8001efa: f000 fc05 bl 8002708 <I2C_ITSlaveSeqCplt>
8001efe: e002 b.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
if (hi2c->XferCount == 0U)
8001f00: 46c0 nop @ (mov r8, r8)
8001f02: e000 b.n 8001f06 <I2C_Slave_ISR_IT+0x1ea>
if ((hi2c->XferCount == 0U) && \
8001f04: 46c0 nop @ (mov r8, r8)
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8001f06: 68fb ldr r3, [r7, #12]
8001f08: 2240 movs r2, #64 @ 0x40
8001f0a: 2100 movs r1, #0
8001f0c: 5499 strb r1, [r3, r2]
return HAL_OK;
8001f0e: 2300 movs r3, #0
}
8001f10: 0018 movs r0, r3
8001f12: 46bd mov sp, r7
8001f14: b006 add sp, #24
8001f16: bd80 pop {r7, pc}
8001f18: ffff0000 .word 0xffff0000
08001f1c <I2C_Master_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
8001f1c: b590 push {r4, r7, lr}
8001f1e: b089 sub sp, #36 @ 0x24
8001f20: af02 add r7, sp, #8
8001f22: 60f8 str r0, [r7, #12]
8001f24: 60b9 str r1, [r7, #8]
8001f26: 607a str r2, [r7, #4]
uint16_t devaddress;
uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hi2c);
8001f28: 68fb ldr r3, [r7, #12]
8001f2a: 2240 movs r2, #64 @ 0x40
8001f2c: 5c9b ldrb r3, [r3, r2]
8001f2e: 2b01 cmp r3, #1
8001f30: d101 bne.n 8001f36 <I2C_Master_ISR_DMA+0x1a>
8001f32: 2302 movs r3, #2
8001f34: e0e7 b.n 8002106 <I2C_Master_ISR_DMA+0x1ea>
8001f36: 68fb ldr r3, [r7, #12]
8001f38: 2240 movs r2, #64 @ 0x40
8001f3a: 2101 movs r1, #1
8001f3c: 5499 strb r1, [r3, r2]
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8001f3e: 68bb ldr r3, [r7, #8]
8001f40: 2210 movs r2, #16
8001f42: 4013 ands r3, r2
8001f44: d017 beq.n 8001f76 <I2C_Master_ISR_DMA+0x5a>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8001f46: 687b ldr r3, [r7, #4]
8001f48: 2210 movs r2, #16
8001f4a: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8001f4c: d013 beq.n 8001f76 <I2C_Master_ISR_DMA+0x5a>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8001f4e: 68fb ldr r3, [r7, #12]
8001f50: 681b ldr r3, [r3, #0]
8001f52: 2210 movs r2, #16
8001f54: 61da str r2, [r3, #28]
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8001f56: 68fb ldr r3, [r7, #12]
8001f58: 6c5b ldr r3, [r3, #68] @ 0x44
8001f5a: 2204 movs r2, #4
8001f5c: 431a orrs r2, r3
8001f5e: 68fb ldr r3, [r7, #12]
8001f60: 645a str r2, [r3, #68] @ 0x44
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
8001f62: 68fb ldr r3, [r7, #12]
8001f64: 2120 movs r1, #32
8001f66: 0018 movs r0, r3
8001f68: f001 f886 bl 8003078 <I2C_Enable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8001f6c: 68fb ldr r3, [r7, #12]
8001f6e: 0018 movs r0, r3
8001f70: f001 f807 bl 8002f82 <I2C_Flush_TXDR>
8001f74: e0c2 b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8001f76: 68bb ldr r3, [r7, #8]
8001f78: 2280 movs r2, #128 @ 0x80
8001f7a: 4013 ands r3, r2
8001f7c: d100 bne.n 8001f80 <I2C_Master_ISR_DMA+0x64>
8001f7e: e07c b.n 800207a <I2C_Master_ISR_DMA+0x15e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
8001f80: 687b ldr r3, [r7, #4]
8001f82: 2240 movs r2, #64 @ 0x40
8001f84: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8001f86: d100 bne.n 8001f8a <I2C_Master_ISR_DMA+0x6e>
8001f88: e077 b.n 800207a <I2C_Master_ISR_DMA+0x15e>
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
8001f8a: 68fb ldr r3, [r7, #12]
8001f8c: 681b ldr r3, [r3, #0]
8001f8e: 681a ldr r2, [r3, #0]
8001f90: 68fb ldr r3, [r7, #12]
8001f92: 681b ldr r3, [r3, #0]
8001f94: 2140 movs r1, #64 @ 0x40
8001f96: 438a bics r2, r1
8001f98: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8001f9a: 68fb ldr r3, [r7, #12]
8001f9c: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001f9e: b29b uxth r3, r3
8001fa0: 2b00 cmp r3, #0
8001fa2: d055 beq.n 8002050 <I2C_Master_ISR_DMA+0x134>
{
/* Recover Slave address */
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
8001fa4: 68fb ldr r3, [r7, #12]
8001fa6: 681b ldr r3, [r3, #0]
8001fa8: 685b ldr r3, [r3, #4]
8001faa: b29a uxth r2, r3
8001fac: 2312 movs r3, #18
8001fae: 18fb adds r3, r7, r3
8001fb0: 0592 lsls r2, r2, #22
8001fb2: 0d92 lsrs r2, r2, #22
8001fb4: 801a strh r2, [r3, #0]
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
8001fb6: 68fb ldr r3, [r7, #12]
8001fb8: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001fba: b29b uxth r3, r3
8001fbc: 2bff cmp r3, #255 @ 0xff
8001fbe: d906 bls.n 8001fce <I2C_Master_ISR_DMA+0xb2>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
8001fc0: 68fb ldr r3, [r7, #12]
8001fc2: 22ff movs r2, #255 @ 0xff
8001fc4: 851a strh r2, [r3, #40] @ 0x28
xfermode = I2C_RELOAD_MODE;
8001fc6: 2380 movs r3, #128 @ 0x80
8001fc8: 045b lsls r3, r3, #17
8001fca: 617b str r3, [r7, #20]
8001fcc: e010 b.n 8001ff0 <I2C_Master_ISR_DMA+0xd4>
}
else
{
hi2c->XferSize = hi2c->XferCount;
8001fce: 68fb ldr r3, [r7, #12]
8001fd0: 8d5b ldrh r3, [r3, #42] @ 0x2a
8001fd2: b29a uxth r2, r3
8001fd4: 68fb ldr r3, [r7, #12]
8001fd6: 851a strh r2, [r3, #40] @ 0x28
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
8001fd8: 68fb ldr r3, [r7, #12]
8001fda: 6adb ldr r3, [r3, #44] @ 0x2c
8001fdc: 4a4c ldr r2, [pc, #304] @ (8002110 <I2C_Master_ISR_DMA+0x1f4>)
8001fde: 4293 cmp r3, r2
8001fe0: d003 beq.n 8001fea <I2C_Master_ISR_DMA+0xce>
{
xfermode = hi2c->XferOptions;
8001fe2: 68fb ldr r3, [r7, #12]
8001fe4: 6adb ldr r3, [r3, #44] @ 0x2c
8001fe6: 617b str r3, [r7, #20]
8001fe8: e002 b.n 8001ff0 <I2C_Master_ISR_DMA+0xd4>
}
else
{
xfermode = I2C_AUTOEND_MODE;
8001fea: 2380 movs r3, #128 @ 0x80
8001fec: 049b lsls r3, r3, #18
8001fee: 617b str r3, [r7, #20]
}
}
/* Set the new XferSize in Nbytes register */
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
8001ff0: 68fb ldr r3, [r7, #12]
8001ff2: 8d1b ldrh r3, [r3, #40] @ 0x28
8001ff4: b2da uxtb r2, r3
8001ff6: 697c ldr r4, [r7, #20]
8001ff8: 2312 movs r3, #18
8001ffa: 18fb adds r3, r7, r3
8001ffc: 8819 ldrh r1, [r3, #0]
8001ffe: 68f8 ldr r0, [r7, #12]
8002000: 2300 movs r3, #0
8002002: 9300 str r3, [sp, #0]
8002004: 0023 movs r3, r4
8002006: f000 fffd bl 8003004 <I2C_TransferConfig>
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
800200a: 68fb ldr r3, [r7, #12]
800200c: 8d5b ldrh r3, [r3, #42] @ 0x2a
800200e: b29a uxth r2, r3
8002010: 68fb ldr r3, [r7, #12]
8002012: 8d1b ldrh r3, [r3, #40] @ 0x28
8002014: 1ad3 subs r3, r2, r3
8002016: b29a uxth r2, r3
8002018: 68fb ldr r3, [r7, #12]
800201a: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
800201c: 68fb ldr r3, [r7, #12]
800201e: 2241 movs r2, #65 @ 0x41
8002020: 5c9b ldrb r3, [r3, r2]
8002022: b2db uxtb r3, r3
8002024: 2b22 cmp r3, #34 @ 0x22
8002026: d109 bne.n 800203c <I2C_Master_ISR_DMA+0x120>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
8002028: 68fb ldr r3, [r7, #12]
800202a: 681b ldr r3, [r3, #0]
800202c: 681a ldr r2, [r3, #0]
800202e: 68fb ldr r3, [r7, #12]
8002030: 681b ldr r3, [r3, #0]
8002032: 2180 movs r1, #128 @ 0x80
8002034: 0209 lsls r1, r1, #8
8002036: 430a orrs r2, r1
8002038: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
800203a: e05f b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
800203c: 68fb ldr r3, [r7, #12]
800203e: 681b ldr r3, [r3, #0]
8002040: 681a ldr r2, [r3, #0]
8002042: 68fb ldr r3, [r7, #12]
8002044: 681b ldr r3, [r3, #0]
8002046: 2180 movs r1, #128 @ 0x80
8002048: 01c9 lsls r1, r1, #7
800204a: 430a orrs r2, r1
800204c: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
800204e: e055 b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
}
}
else
{
/* Call TxCpltCallback() if no stop mode is set */
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
8002050: 68fb ldr r3, [r7, #12]
8002052: 681b ldr r3, [r3, #0]
8002054: 685a ldr r2, [r3, #4]
8002056: 2380 movs r3, #128 @ 0x80
8002058: 049b lsls r3, r3, #18
800205a: 401a ands r2, r3
800205c: 2380 movs r3, #128 @ 0x80
800205e: 049b lsls r3, r3, #18
8002060: 429a cmp r2, r3
8002062: d004 beq.n 800206e <I2C_Master_ISR_DMA+0x152>
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
8002064: 68fb ldr r3, [r7, #12]
8002066: 0018 movs r0, r3
8002068: f000 fb0c bl 8002684 <I2C_ITMasterSeqCplt>
if (hi2c->XferCount != 0U)
800206c: e046 b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
800206e: 68fb ldr r3, [r7, #12]
8002070: 2140 movs r1, #64 @ 0x40
8002072: 0018 movs r0, r3
8002074: f000 fe5a bl 8002d2c <I2C_ITError>
if (hi2c->XferCount != 0U)
8002078: e040 b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
}
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
800207a: 68bb ldr r3, [r7, #8]
800207c: 2240 movs r2, #64 @ 0x40
800207e: 4013 ands r3, r2
8002080: d02c beq.n 80020dc <I2C_Master_ISR_DMA+0x1c0>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
8002082: 687b ldr r3, [r7, #4]
8002084: 2240 movs r2, #64 @ 0x40
8002086: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8002088: d028 beq.n 80020dc <I2C_Master_ISR_DMA+0x1c0>
{
if (hi2c->XferCount == 0U)
800208a: 68fb ldr r3, [r7, #12]
800208c: 8d5b ldrh r3, [r3, #42] @ 0x2a
800208e: b29b uxth r3, r3
8002090: 2b00 cmp r3, #0
8002092: d11d bne.n 80020d0 <I2C_Master_ISR_DMA+0x1b4>
{
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
8002094: 68fb ldr r3, [r7, #12]
8002096: 681b ldr r3, [r3, #0]
8002098: 685a ldr r2, [r3, #4]
800209a: 2380 movs r3, #128 @ 0x80
800209c: 049b lsls r3, r3, #18
800209e: 401a ands r2, r3
80020a0: 2380 movs r3, #128 @ 0x80
80020a2: 049b lsls r3, r3, #18
80020a4: 429a cmp r2, r3
80020a6: d028 beq.n 80020fa <I2C_Master_ISR_DMA+0x1de>
{
/* Generate a stop condition in case of no transfer option */
if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
80020a8: 68fb ldr r3, [r7, #12]
80020aa: 6adb ldr r3, [r3, #44] @ 0x2c
80020ac: 4a18 ldr r2, [pc, #96] @ (8002110 <I2C_Master_ISR_DMA+0x1f4>)
80020ae: 4293 cmp r3, r2
80020b0: d109 bne.n 80020c6 <I2C_Master_ISR_DMA+0x1aa>
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
80020b2: 68fb ldr r3, [r7, #12]
80020b4: 681b ldr r3, [r3, #0]
80020b6: 685a ldr r2, [r3, #4]
80020b8: 68fb ldr r3, [r7, #12]
80020ba: 681b ldr r3, [r3, #0]
80020bc: 2180 movs r1, #128 @ 0x80
80020be: 01c9 lsls r1, r1, #7
80020c0: 430a orrs r2, r1
80020c2: 605a str r2, [r3, #4]
if (hi2c->XferCount == 0U)
80020c4: e019 b.n 80020fa <I2C_Master_ISR_DMA+0x1de>
}
else
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSeqCplt(hi2c);
80020c6: 68fb ldr r3, [r7, #12]
80020c8: 0018 movs r0, r3
80020ca: f000 fadb bl 8002684 <I2C_ITMasterSeqCplt>
if (hi2c->XferCount == 0U)
80020ce: e014 b.n 80020fa <I2C_Master_ISR_DMA+0x1de>
}
else
{
/* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
80020d0: 68fb ldr r3, [r7, #12]
80020d2: 2140 movs r1, #64 @ 0x40
80020d4: 0018 movs r0, r3
80020d6: f000 fe29 bl 8002d2c <I2C_ITError>
if (hi2c->XferCount == 0U)
80020da: e00e b.n 80020fa <I2C_Master_ISR_DMA+0x1de>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
80020dc: 68bb ldr r3, [r7, #8]
80020de: 2220 movs r2, #32
80020e0: 4013 ands r3, r2
80020e2: d00b beq.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
80020e4: 687b ldr r3, [r7, #4]
80020e6: 2220 movs r2, #32
80020e8: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
80020ea: d007 beq.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
80020ec: 68ba ldr r2, [r7, #8]
80020ee: 68fb ldr r3, [r7, #12]
80020f0: 0011 movs r1, r2
80020f2: 0018 movs r0, r3
80020f4: f000 fb6c bl 80027d0 <I2C_ITMasterCplt>
80020f8: e000 b.n 80020fc <I2C_Master_ISR_DMA+0x1e0>
if (hi2c->XferCount == 0U)
80020fa: 46c0 nop @ (mov r8, r8)
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80020fc: 68fb ldr r3, [r7, #12]
80020fe: 2240 movs r2, #64 @ 0x40
8002100: 2100 movs r1, #0
8002102: 5499 strb r1, [r3, r2]
return HAL_OK;
8002104: 2300 movs r3, #0
}
8002106: 0018 movs r0, r3
8002108: 46bd mov sp, r7
800210a: b007 add sp, #28
800210c: bd90 pop {r4, r7, pc}
800210e: 46c0 nop @ (mov r8, r8)
8002110: ffff0000 .word 0xffff0000
08002114 <I2C_Mem_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
8002114: b590 push {r4, r7, lr}
8002116: b089 sub sp, #36 @ 0x24
8002118: af02 add r7, sp, #8
800211a: 60f8 str r0, [r7, #12]
800211c: 60b9 str r1, [r7, #8]
800211e: 607a str r2, [r7, #4]
uint32_t direction = I2C_GENERATE_START_WRITE;
8002120: 4b90 ldr r3, [pc, #576] @ (8002364 <I2C_Mem_ISR_DMA+0x250>)
8002122: 617b str r3, [r7, #20]
/* Process Locked */
__HAL_LOCK(hi2c);
8002124: 68fb ldr r3, [r7, #12]
8002126: 2240 movs r2, #64 @ 0x40
8002128: 5c9b ldrb r3, [r3, r2]
800212a: 2b01 cmp r3, #1
800212c: d101 bne.n 8002132 <I2C_Mem_ISR_DMA+0x1e>
800212e: 2302 movs r3, #2
8002130: e113 b.n 800235a <I2C_Mem_ISR_DMA+0x246>
8002132: 68fb ldr r3, [r7, #12]
8002134: 2240 movs r2, #64 @ 0x40
8002136: 2101 movs r1, #1
8002138: 5499 strb r1, [r3, r2]
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
800213a: 68bb ldr r3, [r7, #8]
800213c: 2210 movs r2, #16
800213e: 4013 ands r3, r2
8002140: d017 beq.n 8002172 <I2C_Mem_ISR_DMA+0x5e>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
8002142: 687b ldr r3, [r7, #4]
8002144: 2210 movs r2, #16
8002146: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
8002148: d013 beq.n 8002172 <I2C_Mem_ISR_DMA+0x5e>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800214a: 68fb ldr r3, [r7, #12]
800214c: 681b ldr r3, [r3, #0]
800214e: 2210 movs r2, #16
8002150: 61da str r2, [r3, #28]
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8002152: 68fb ldr r3, [r7, #12]
8002154: 6c5b ldr r3, [r3, #68] @ 0x44
8002156: 2204 movs r2, #4
8002158: 431a orrs r2, r3
800215a: 68fb ldr r3, [r7, #12]
800215c: 645a str r2, [r3, #68] @ 0x44
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
800215e: 68fb ldr r3, [r7, #12]
8002160: 2120 movs r1, #32
8002162: 0018 movs r0, r3
8002164: f000 ff88 bl 8003078 <I2C_Enable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8002168: 68fb ldr r3, [r7, #12]
800216a: 0018 movs r0, r3
800216c: f000 ff09 bl 8002f82 <I2C_Flush_TXDR>
8002170: e0ee b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
8002172: 68bb ldr r3, [r7, #8]
8002174: 2202 movs r2, #2
8002176: 4013 ands r3, r2
8002178: d00d beq.n 8002196 <I2C_Mem_ISR_DMA+0x82>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
800217a: 687b ldr r3, [r7, #4]
800217c: 2202 movs r2, #2
800217e: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
8002180: d009 beq.n 8002196 <I2C_Mem_ISR_DMA+0x82>
{
/* Write LSB part of Memory Address */
hi2c->Instance->TXDR = hi2c->Memaddress;
8002182: 68fb ldr r3, [r7, #12]
8002184: 681b ldr r3, [r3, #0]
8002186: 68fa ldr r2, [r7, #12]
8002188: 6d12 ldr r2, [r2, #80] @ 0x50
800218a: 629a str r2, [r3, #40] @ 0x28
/* Reset Memaddress content */
hi2c->Memaddress = 0xFFFFFFFFU;
800218c: 68fb ldr r3, [r7, #12]
800218e: 2201 movs r2, #1
8002190: 4252 negs r2, r2
8002192: 651a str r2, [r3, #80] @ 0x50
8002194: e0dc b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
8002196: 68bb ldr r3, [r7, #8]
8002198: 2280 movs r2, #128 @ 0x80
800219a: 4013 ands r3, r2
800219c: d063 beq.n 8002266 <I2C_Mem_ISR_DMA+0x152>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
800219e: 687b ldr r3, [r7, #4]
80021a0: 2240 movs r2, #64 @ 0x40
80021a2: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
80021a4: d05f beq.n 8002266 <I2C_Mem_ISR_DMA+0x152>
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
80021a6: 68fb ldr r3, [r7, #12]
80021a8: 2101 movs r1, #1
80021aa: 0018 movs r0, r3
80021ac: f000 ffee bl 800318c <I2C_Disable_IRQ>
/* Enable only Error interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
80021b0: 68fb ldr r3, [r7, #12]
80021b2: 2110 movs r1, #16
80021b4: 0018 movs r0, r3
80021b6: f000 ff5f bl 8003078 <I2C_Enable_IRQ>
if (hi2c->XferCount != 0U)
80021ba: 68fb ldr r3, [r7, #12]
80021bc: 8d5b ldrh r3, [r3, #42] @ 0x2a
80021be: b29b uxth r3, r3
80021c0: 2b00 cmp r3, #0
80021c2: d04a beq.n 800225a <I2C_Mem_ISR_DMA+0x146>
{
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
80021c4: 68fb ldr r3, [r7, #12]
80021c6: 8d5b ldrh r3, [r3, #42] @ 0x2a
80021c8: b29b uxth r3, r3
80021ca: 2bff cmp r3, #255 @ 0xff
80021cc: d910 bls.n 80021f0 <I2C_Mem_ISR_DMA+0xdc>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80021ce: 68fb ldr r3, [r7, #12]
80021d0: 22ff movs r2, #255 @ 0xff
80021d2: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
80021d4: 68fb ldr r3, [r7, #12]
80021d6: 6cdb ldr r3, [r3, #76] @ 0x4c
80021d8: b299 uxth r1, r3
80021da: 68fb ldr r3, [r7, #12]
80021dc: 8d1b ldrh r3, [r3, #40] @ 0x28
80021de: b2da uxtb r2, r3
80021e0: 2380 movs r3, #128 @ 0x80
80021e2: 045b lsls r3, r3, #17
80021e4: 68f8 ldr r0, [r7, #12]
80021e6: 2400 movs r4, #0
80021e8: 9400 str r4, [sp, #0]
80021ea: f000 ff0b bl 8003004 <I2C_TransferConfig>
80021ee: e011 b.n 8002214 <I2C_Mem_ISR_DMA+0x100>
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
80021f0: 68fb ldr r3, [r7, #12]
80021f2: 8d5b ldrh r3, [r3, #42] @ 0x2a
80021f4: b29a uxth r2, r3
80021f6: 68fb ldr r3, [r7, #12]
80021f8: 851a strh r2, [r3, #40] @ 0x28
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
80021fa: 68fb ldr r3, [r7, #12]
80021fc: 6cdb ldr r3, [r3, #76] @ 0x4c
80021fe: b299 uxth r1, r3
8002200: 68fb ldr r3, [r7, #12]
8002202: 8d1b ldrh r3, [r3, #40] @ 0x28
8002204: b2da uxtb r2, r3
8002206: 2380 movs r3, #128 @ 0x80
8002208: 049b lsls r3, r3, #18
800220a: 68f8 ldr r0, [r7, #12]
800220c: 2400 movs r4, #0
800220e: 9400 str r4, [sp, #0]
8002210: f000 fef8 bl 8003004 <I2C_TransferConfig>
I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
8002214: 68fb ldr r3, [r7, #12]
8002216: 8d5b ldrh r3, [r3, #42] @ 0x2a
8002218: b29a uxth r2, r3
800221a: 68fb ldr r3, [r7, #12]
800221c: 8d1b ldrh r3, [r3, #40] @ 0x28
800221e: 1ad3 subs r3, r2, r3
8002220: b29a uxth r2, r3
8002222: 68fb ldr r3, [r7, #12]
8002224: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002226: 68fb ldr r3, [r7, #12]
8002228: 2241 movs r2, #65 @ 0x41
800222a: 5c9b ldrb r3, [r3, r2]
800222c: b2db uxtb r3, r3
800222e: 2b22 cmp r3, #34 @ 0x22
8002230: d109 bne.n 8002246 <I2C_Mem_ISR_DMA+0x132>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
8002232: 68fb ldr r3, [r7, #12]
8002234: 681b ldr r3, [r3, #0]
8002236: 681a ldr r2, [r3, #0]
8002238: 68fb ldr r3, [r7, #12]
800223a: 681b ldr r3, [r3, #0]
800223c: 2180 movs r1, #128 @ 0x80
800223e: 0209 lsls r1, r1, #8
8002240: 430a orrs r2, r1
8002242: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8002244: e084 b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
8002246: 68fb ldr r3, [r7, #12]
8002248: 681b ldr r3, [r3, #0]
800224a: 681a ldr r2, [r3, #0]
800224c: 68fb ldr r3, [r7, #12]
800224e: 681b ldr r3, [r3, #0]
8002250: 2180 movs r1, #128 @ 0x80
8002252: 01c9 lsls r1, r1, #7
8002254: 430a orrs r2, r1
8002256: 601a str r2, [r3, #0]
if (hi2c->XferCount != 0U)
8002258: e07a b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
else
{
/* Wrong size Status regarding TCR flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
800225a: 68fb ldr r3, [r7, #12]
800225c: 2140 movs r1, #64 @ 0x40
800225e: 0018 movs r0, r3
8002260: f000 fd64 bl 8002d2c <I2C_ITError>
if (hi2c->XferCount != 0U)
8002264: e074 b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8002266: 68bb ldr r3, [r7, #8]
8002268: 2240 movs r2, #64 @ 0x40
800226a: 4013 ands r3, r2
800226c: d062 beq.n 8002334 <I2C_Mem_ISR_DMA+0x220>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
800226e: 687b ldr r3, [r7, #4]
8002270: 2240 movs r2, #64 @ 0x40
8002272: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
8002274: d05e beq.n 8002334 <I2C_Mem_ISR_DMA+0x220>
{
/* Disable Interrupt related to address step */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8002276: 68fb ldr r3, [r7, #12]
8002278: 2101 movs r1, #1
800227a: 0018 movs r0, r3
800227c: f000 ff86 bl 800318c <I2C_Disable_IRQ>
/* Enable only Error and NACK interrupt for data transfer */
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
8002280: 68fb ldr r3, [r7, #12]
8002282: 2110 movs r1, #16
8002284: 0018 movs r0, r3
8002286: f000 fef7 bl 8003078 <I2C_Enable_IRQ>
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
800228a: 68fb ldr r3, [r7, #12]
800228c: 2241 movs r2, #65 @ 0x41
800228e: 5c9b ldrb r3, [r3, r2]
8002290: b2db uxtb r3, r3
8002292: 2b22 cmp r3, #34 @ 0x22
8002294: d101 bne.n 800229a <I2C_Mem_ISR_DMA+0x186>
{
direction = I2C_GENERATE_START_READ;
8002296: 4b34 ldr r3, [pc, #208] @ (8002368 <I2C_Mem_ISR_DMA+0x254>)
8002298: 617b str r3, [r7, #20]
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
800229a: 68fb ldr r3, [r7, #12]
800229c: 8d5b ldrh r3, [r3, #42] @ 0x2a
800229e: b29b uxth r3, r3
80022a0: 2bff cmp r3, #255 @ 0xff
80022a2: d911 bls.n 80022c8 <I2C_Mem_ISR_DMA+0x1b4>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
80022a4: 68fb ldr r3, [r7, #12]
80022a6: 22ff movs r2, #255 @ 0xff
80022a8: 851a strh r2, [r3, #40] @ 0x28
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
80022aa: 68fb ldr r3, [r7, #12]
80022ac: 6cdb ldr r3, [r3, #76] @ 0x4c
80022ae: b299 uxth r1, r3
80022b0: 68fb ldr r3, [r7, #12]
80022b2: 8d1b ldrh r3, [r3, #40] @ 0x28
80022b4: b2da uxtb r2, r3
80022b6: 2380 movs r3, #128 @ 0x80
80022b8: 045c lsls r4, r3, #17
80022ba: 68f8 ldr r0, [r7, #12]
80022bc: 697b ldr r3, [r7, #20]
80022be: 9300 str r3, [sp, #0]
80022c0: 0023 movs r3, r4
80022c2: f000 fe9f bl 8003004 <I2C_TransferConfig>
80022c6: e012 b.n 80022ee <I2C_Mem_ISR_DMA+0x1da>
I2C_RELOAD_MODE, direction);
}
else
{
hi2c->XferSize = hi2c->XferCount;
80022c8: 68fb ldr r3, [r7, #12]
80022ca: 8d5b ldrh r3, [r3, #42] @ 0x2a
80022cc: b29a uxth r2, r3
80022ce: 68fb ldr r3, [r7, #12]
80022d0: 851a strh r2, [r3, #40] @ 0x28
/* Set NBYTES to write and generate RESTART */
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
80022d2: 68fb ldr r3, [r7, #12]
80022d4: 6cdb ldr r3, [r3, #76] @ 0x4c
80022d6: b299 uxth r1, r3
80022d8: 68fb ldr r3, [r7, #12]
80022da: 8d1b ldrh r3, [r3, #40] @ 0x28
80022dc: b2da uxtb r2, r3
80022de: 2380 movs r3, #128 @ 0x80
80022e0: 049c lsls r4, r3, #18
80022e2: 68f8 ldr r0, [r7, #12]
80022e4: 697b ldr r3, [r7, #20]
80022e6: 9300 str r3, [sp, #0]
80022e8: 0023 movs r3, r4
80022ea: f000 fe8b bl 8003004 <I2C_TransferConfig>
I2C_AUTOEND_MODE, direction);
}
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
80022ee: 68fb ldr r3, [r7, #12]
80022f0: 8d5b ldrh r3, [r3, #42] @ 0x2a
80022f2: b29a uxth r2, r3
80022f4: 68fb ldr r3, [r7, #12]
80022f6: 8d1b ldrh r3, [r3, #40] @ 0x28
80022f8: 1ad3 subs r3, r2, r3
80022fa: b29a uxth r2, r3
80022fc: 68fb ldr r3, [r7, #12]
80022fe: 855a strh r2, [r3, #42] @ 0x2a
/* Enable DMA Request */
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002300: 68fb ldr r3, [r7, #12]
8002302: 2241 movs r2, #65 @ 0x41
8002304: 5c9b ldrb r3, [r3, r2]
8002306: b2db uxtb r3, r3
8002308: 2b22 cmp r3, #34 @ 0x22
800230a: d109 bne.n 8002320 <I2C_Mem_ISR_DMA+0x20c>
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
800230c: 68fb ldr r3, [r7, #12]
800230e: 681b ldr r3, [r3, #0]
8002310: 681a ldr r2, [r3, #0]
8002312: 68fb ldr r3, [r7, #12]
8002314: 681b ldr r3, [r3, #0]
8002316: 2180 movs r1, #128 @ 0x80
8002318: 0209 lsls r1, r1, #8
800231a: 430a orrs r2, r1
800231c: 601a str r2, [r3, #0]
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
800231e: e017 b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
else
{
hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
8002320: 68fb ldr r3, [r7, #12]
8002322: 681b ldr r3, [r3, #0]
8002324: 681a ldr r2, [r3, #0]
8002326: 68fb ldr r3, [r7, #12]
8002328: 681b ldr r3, [r3, #0]
800232a: 2180 movs r1, #128 @ 0x80
800232c: 01c9 lsls r1, r1, #7
800232e: 430a orrs r2, r1
8002330: 601a str r2, [r3, #0]
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002332: e00d b.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8002334: 68bb ldr r3, [r7, #8]
8002336: 2220 movs r2, #32
8002338: 4013 ands r3, r2
800233a: d009 beq.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
800233c: 687b ldr r3, [r7, #4]
800233e: 2220 movs r2, #32
8002340: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8002342: d005 beq.n 8002350 <I2C_Mem_ISR_DMA+0x23c>
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
8002344: 68ba ldr r2, [r7, #8]
8002346: 68fb ldr r3, [r7, #12]
8002348: 0011 movs r1, r2
800234a: 0018 movs r0, r3
800234c: f000 fa40 bl 80027d0 <I2C_ITMasterCplt>
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002350: 68fb ldr r3, [r7, #12]
8002352: 2240 movs r2, #64 @ 0x40
8002354: 2100 movs r1, #0
8002356: 5499 strb r1, [r3, r2]
return HAL_OK;
8002358: 2300 movs r3, #0
}
800235a: 0018 movs r0, r3
800235c: 46bd mov sp, r7
800235e: b007 add sp, #28
8002360: bd90 pop {r4, r7, pc}
8002362: 46c0 nop @ (mov r8, r8)
8002364: 80002000 .word 0x80002000
8002368: 80002400 .word 0x80002400
0800236c <I2C_Slave_ISR_DMA>:
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources)
{
800236c: b580 push {r7, lr}
800236e: b088 sub sp, #32
8002370: af00 add r7, sp, #0
8002372: 60f8 str r0, [r7, #12]
8002374: 60b9 str r1, [r7, #8]
8002376: 607a str r2, [r7, #4]
uint32_t tmpoptions = hi2c->XferOptions;
8002378: 68fb ldr r3, [r7, #12]
800237a: 6adb ldr r3, [r3, #44] @ 0x2c
800237c: 61bb str r3, [r7, #24]
uint32_t treatdmanack = 0U;
800237e: 2300 movs r3, #0
8002380: 61fb str r3, [r7, #28]
HAL_I2C_StateTypeDef tmpstate;
/* Process locked */
__HAL_LOCK(hi2c);
8002382: 68fb ldr r3, [r7, #12]
8002384: 2240 movs r2, #64 @ 0x40
8002386: 5c9b ldrb r3, [r3, r2]
8002388: 2b01 cmp r3, #1
800238a: d101 bne.n 8002390 <I2C_Slave_ISR_DMA+0x24>
800238c: 2302 movs r3, #2
800238e: e0ce b.n 800252e <I2C_Slave_ISR_DMA+0x1c2>
8002390: 68fb ldr r3, [r7, #12]
8002392: 2240 movs r2, #64 @ 0x40
8002394: 2101 movs r1, #1
8002396: 5499 strb r1, [r3, r2]
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
8002398: 68bb ldr r3, [r7, #8]
800239a: 2220 movs r2, #32
800239c: 4013 ands r3, r2
800239e: d00a beq.n 80023b6 <I2C_Slave_ISR_DMA+0x4a>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
80023a0: 687b ldr r3, [r7, #4]
80023a2: 2220 movs r2, #32
80023a4: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
80023a6: d006 beq.n 80023b6 <I2C_Slave_ISR_DMA+0x4a>
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
80023a8: 68ba ldr r2, [r7, #8]
80023aa: 68fb ldr r3, [r7, #12]
80023ac: 0011 movs r1, r2
80023ae: 0018 movs r0, r3
80023b0: f000 fadc bl 800296c <I2C_ITSlaveCplt>
80023b4: e0b6 b.n 8002524 <I2C_Slave_ISR_DMA+0x1b8>
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
80023b6: 68bb ldr r3, [r7, #8]
80023b8: 2210 movs r2, #16
80023ba: 4013 ands r3, r2
80023bc: d100 bne.n 80023c0 <I2C_Slave_ISR_DMA+0x54>
80023be: e0a3 b.n 8002508 <I2C_Slave_ISR_DMA+0x19c>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
80023c0: 687b ldr r3, [r7, #4]
80023c2: 2210 movs r2, #16
80023c4: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
80023c6: d100 bne.n 80023ca <I2C_Slave_ISR_DMA+0x5e>
80023c8: e09e b.n 8002508 <I2C_Slave_ISR_DMA+0x19c>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
80023ca: 687a ldr r2, [r7, #4]
80023cc: 2380 movs r3, #128 @ 0x80
80023ce: 01db lsls r3, r3, #7
80023d0: 4013 ands r3, r2
80023d2: d105 bne.n 80023e0 <I2C_Slave_ISR_DMA+0x74>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
80023d4: 687a ldr r2, [r7, #4]
80023d6: 2380 movs r3, #128 @ 0x80
80023d8: 021b lsls r3, r3, #8
80023da: 4013 ands r3, r2
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
80023dc: d100 bne.n 80023e0 <I2C_Slave_ISR_DMA+0x74>
80023de: e08c b.n 80024fa <I2C_Slave_ISR_DMA+0x18e>
{
/* Split check of hdmarx, for MISRA compliance */
if (hi2c->hdmarx != NULL)
80023e0: 68fb ldr r3, [r7, #12]
80023e2: 6bdb ldr r3, [r3, #60] @ 0x3c
80023e4: 2b00 cmp r3, #0
80023e6: d00c beq.n 8002402 <I2C_Slave_ISR_DMA+0x96>
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
80023e8: 687a ldr r2, [r7, #4]
80023ea: 2380 movs r3, #128 @ 0x80
80023ec: 021b lsls r3, r3, #8
80023ee: 4013 ands r3, r2
80023f0: d007 beq.n 8002402 <I2C_Slave_ISR_DMA+0x96>
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
80023f2: 68fb ldr r3, [r7, #12]
80023f4: 6bdb ldr r3, [r3, #60] @ 0x3c
80023f6: 681b ldr r3, [r3, #0]
80023f8: 685b ldr r3, [r3, #4]
80023fa: 2b00 cmp r3, #0
80023fc: d101 bne.n 8002402 <I2C_Slave_ISR_DMA+0x96>
{
treatdmanack = 1U;
80023fe: 2301 movs r3, #1
8002400: 61fb str r3, [r7, #28]
}
}
}
/* Split check of hdmatx, for MISRA compliance */
if (hi2c->hdmatx != NULL)
8002402: 68fb ldr r3, [r7, #12]
8002404: 6b9b ldr r3, [r3, #56] @ 0x38
8002406: 2b00 cmp r3, #0
8002408: d00c beq.n 8002424 <I2C_Slave_ISR_DMA+0xb8>
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
800240a: 687a ldr r2, [r7, #4]
800240c: 2380 movs r3, #128 @ 0x80
800240e: 01db lsls r3, r3, #7
8002410: 4013 ands r3, r2
8002412: d007 beq.n 8002424 <I2C_Slave_ISR_DMA+0xb8>
{
if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
8002414: 68fb ldr r3, [r7, #12]
8002416: 6b9b ldr r3, [r3, #56] @ 0x38
8002418: 681b ldr r3, [r3, #0]
800241a: 685b ldr r3, [r3, #4]
800241c: 2b00 cmp r3, #0
800241e: d101 bne.n 8002424 <I2C_Slave_ISR_DMA+0xb8>
{
treatdmanack = 1U;
8002420: 2301 movs r3, #1
8002422: 61fb str r3, [r7, #28]
}
}
}
if (treatdmanack == 1U)
8002424: 69fb ldr r3, [r7, #28]
8002426: 2b01 cmp r3, #1
8002428: d12d bne.n 8002486 <I2C_Slave_ISR_DMA+0x11a>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
800242a: 68fb ldr r3, [r7, #12]
800242c: 2241 movs r2, #65 @ 0x41
800242e: 5c9b ldrb r3, [r3, r2]
8002430: b2db uxtb r3, r3
8002432: 2b28 cmp r3, #40 @ 0x28
8002434: d10b bne.n 800244e <I2C_Slave_ISR_DMA+0xe2>
8002436: 69ba ldr r2, [r7, #24]
8002438: 2380 movs r3, #128 @ 0x80
800243a: 049b lsls r3, r3, #18
800243c: 429a cmp r2, r3
800243e: d106 bne.n 800244e <I2C_Slave_ISR_DMA+0xe2>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
8002440: 68ba ldr r2, [r7, #8]
8002442: 68fb ldr r3, [r7, #12]
8002444: 0011 movs r1, r2
8002446: 0018 movs r0, r3
8002448: f000 fc18 bl 8002c7c <I2C_ITListenCplt>
800244c: e054 b.n 80024f8 <I2C_Slave_ISR_DMA+0x18c>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
800244e: 68fb ldr r3, [r7, #12]
8002450: 2241 movs r2, #65 @ 0x41
8002452: 5c9b ldrb r3, [r3, r2]
8002454: b2db uxtb r3, r3
8002456: 2b29 cmp r3, #41 @ 0x29
8002458: d110 bne.n 800247c <I2C_Slave_ISR_DMA+0x110>
800245a: 69bb ldr r3, [r7, #24]
800245c: 4a36 ldr r2, [pc, #216] @ (8002538 <I2C_Slave_ISR_DMA+0x1cc>)
800245e: 4293 cmp r3, r2
8002460: d00c beq.n 800247c <I2C_Slave_ISR_DMA+0x110>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002462: 68fb ldr r3, [r7, #12]
8002464: 681b ldr r3, [r3, #0]
8002466: 2210 movs r2, #16
8002468: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
800246a: 68fb ldr r3, [r7, #12]
800246c: 0018 movs r0, r3
800246e: f000 fd88 bl 8002f82 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8002472: 68fb ldr r3, [r7, #12]
8002474: 0018 movs r0, r3
8002476: f000 f947 bl 8002708 <I2C_ITSlaveSeqCplt>
800247a: e03d b.n 80024f8 <I2C_Slave_ISR_DMA+0x18c>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
800247c: 68fb ldr r3, [r7, #12]
800247e: 681b ldr r3, [r3, #0]
8002480: 2210 movs r2, #16
8002482: 61da str r2, [r3, #28]
if (treatdmanack == 1U)
8002484: e03e b.n 8002504 <I2C_Slave_ISR_DMA+0x198>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002486: 68fb ldr r3, [r7, #12]
8002488: 681b ldr r3, [r3, #0]
800248a: 2210 movs r2, #16
800248c: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800248e: 68fb ldr r3, [r7, #12]
8002490: 6c5b ldr r3, [r3, #68] @ 0x44
8002492: 2204 movs r2, #4
8002494: 431a orrs r2, r3
8002496: 68fb ldr r3, [r7, #12]
8002498: 645a str r2, [r3, #68] @ 0x44
/* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
tmpstate = hi2c->State;
800249a: 2317 movs r3, #23
800249c: 18fb adds r3, r7, r3
800249e: 68fa ldr r2, [r7, #12]
80024a0: 2141 movs r1, #65 @ 0x41
80024a2: 5c52 ldrb r2, [r2, r1]
80024a4: 701a strb r2, [r3, #0]
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
80024a6: 69bb ldr r3, [r7, #24]
80024a8: 2b00 cmp r3, #0
80024aa: d004 beq.n 80024b6 <I2C_Slave_ISR_DMA+0x14a>
80024ac: 69ba ldr r2, [r7, #24]
80024ae: 2380 movs r3, #128 @ 0x80
80024b0: 045b lsls r3, r3, #17
80024b2: 429a cmp r2, r3
80024b4: d126 bne.n 8002504 <I2C_Slave_ISR_DMA+0x198>
{
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
80024b6: 2217 movs r2, #23
80024b8: 18bb adds r3, r7, r2
80024ba: 781b ldrb r3, [r3, #0]
80024bc: 2b21 cmp r3, #33 @ 0x21
80024be: d003 beq.n 80024c8 <I2C_Slave_ISR_DMA+0x15c>
80024c0: 18bb adds r3, r7, r2
80024c2: 781b ldrb r3, [r3, #0]
80024c4: 2b29 cmp r3, #41 @ 0x29
80024c6: d103 bne.n 80024d0 <I2C_Slave_ISR_DMA+0x164>
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
80024c8: 68fb ldr r3, [r7, #12]
80024ca: 2221 movs r2, #33 @ 0x21
80024cc: 631a str r2, [r3, #48] @ 0x30
80024ce: e00b b.n 80024e8 <I2C_Slave_ISR_DMA+0x17c>
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
80024d0: 2217 movs r2, #23
80024d2: 18bb adds r3, r7, r2
80024d4: 781b ldrb r3, [r3, #0]
80024d6: 2b22 cmp r3, #34 @ 0x22
80024d8: d003 beq.n 80024e2 <I2C_Slave_ISR_DMA+0x176>
80024da: 18bb adds r3, r7, r2
80024dc: 781b ldrb r3, [r3, #0]
80024de: 2b2a cmp r3, #42 @ 0x2a
80024e0: d102 bne.n 80024e8 <I2C_Slave_ISR_DMA+0x17c>
{
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
80024e2: 68fb ldr r3, [r7, #12]
80024e4: 2222 movs r2, #34 @ 0x22
80024e6: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
80024e8: 68fb ldr r3, [r7, #12]
80024ea: 6c5a ldr r2, [r3, #68] @ 0x44
80024ec: 68fb ldr r3, [r7, #12]
80024ee: 0011 movs r1, r2
80024f0: 0018 movs r0, r3
80024f2: f000 fc1b bl 8002d2c <I2C_ITError>
if (treatdmanack == 1U)
80024f6: e005 b.n 8002504 <I2C_Slave_ISR_DMA+0x198>
80024f8: e004 b.n 8002504 <I2C_Slave_ISR_DMA+0x198>
}
}
else
{
/* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
80024fa: 68fb ldr r3, [r7, #12]
80024fc: 681b ldr r3, [r3, #0]
80024fe: 2210 movs r2, #16
8002500: 61da str r2, [r3, #28]
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8002502: e00f b.n 8002524 <I2C_Slave_ISR_DMA+0x1b8>
if (treatdmanack == 1U)
8002504: 46c0 nop @ (mov r8, r8)
if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
8002506: e00d b.n 8002524 <I2C_Slave_ISR_DMA+0x1b8>
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
8002508: 68bb ldr r3, [r7, #8]
800250a: 2208 movs r2, #8
800250c: 4013 ands r3, r2
800250e: d009 beq.n 8002524 <I2C_Slave_ISR_DMA+0x1b8>
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
8002510: 687b ldr r3, [r7, #4]
8002512: 2208 movs r2, #8
8002514: 4013 ands r3, r2
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
8002516: d005 beq.n 8002524 <I2C_Slave_ISR_DMA+0x1b8>
{
I2C_ITAddrCplt(hi2c, ITFlags);
8002518: 68ba ldr r2, [r7, #8]
800251a: 68fb ldr r3, [r7, #12]
800251c: 0011 movs r1, r2
800251e: 0018 movs r0, r3
8002520: f000 f80c bl 800253c <I2C_ITAddrCplt>
{
/* Nothing to do */
}
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002524: 68fb ldr r3, [r7, #12]
8002526: 2240 movs r2, #64 @ 0x40
8002528: 2100 movs r1, #0
800252a: 5499 strb r1, [r3, r2]
return HAL_OK;
800252c: 2300 movs r3, #0
}
800252e: 0018 movs r0, r3
8002530: 46bd mov sp, r7
8002532: b008 add sp, #32
8002534: bd80 pop {r7, pc}
8002536: 46c0 nop @ (mov r8, r8)
8002538: ffff0000 .word 0xffff0000
0800253c <I2C_ITAddrCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
800253c: b5b0 push {r4, r5, r7, lr}
800253e: b084 sub sp, #16
8002540: af00 add r7, sp, #0
8002542: 6078 str r0, [r7, #4]
8002544: 6039 str r1, [r7, #0]
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
8002546: 687b ldr r3, [r7, #4]
8002548: 2241 movs r2, #65 @ 0x41
800254a: 5c9b ldrb r3, [r3, r2]
800254c: b2db uxtb r3, r3
800254e: 001a movs r2, r3
8002550: 2328 movs r3, #40 @ 0x28
8002552: 4013 ands r3, r2
8002554: 2b28 cmp r3, #40 @ 0x28
8002556: d000 beq.n 800255a <I2C_ITAddrCplt+0x1e>
8002558: e088 b.n 800266c <I2C_ITAddrCplt+0x130>
{
transferdirection = I2C_GET_DIR(hi2c);
800255a: 687b ldr r3, [r7, #4]
800255c: 681b ldr r3, [r3, #0]
800255e: 699b ldr r3, [r3, #24]
8002560: 0c1b lsrs r3, r3, #16
8002562: b2da uxtb r2, r3
8002564: 250f movs r5, #15
8002566: 197b adds r3, r7, r5
8002568: 2101 movs r1, #1
800256a: 400a ands r2, r1
800256c: 701a strb r2, [r3, #0]
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
800256e: 687b ldr r3, [r7, #4]
8002570: 681b ldr r3, [r3, #0]
8002572: 699b ldr r3, [r3, #24]
8002574: 0c1b lsrs r3, r3, #16
8002576: b29a uxth r2, r3
8002578: 200c movs r0, #12
800257a: 183b adds r3, r7, r0
800257c: 21fe movs r1, #254 @ 0xfe
800257e: 400a ands r2, r1
8002580: 801a strh r2, [r3, #0]
ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
8002582: 687b ldr r3, [r7, #4]
8002584: 681b ldr r3, [r3, #0]
8002586: 689b ldr r3, [r3, #8]
8002588: b29a uxth r2, r3
800258a: 240a movs r4, #10
800258c: 193b adds r3, r7, r4
800258e: 0592 lsls r2, r2, #22
8002590: 0d92 lsrs r2, r2, #22
8002592: 801a strh r2, [r3, #0]
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
8002594: 687b ldr r3, [r7, #4]
8002596: 681b ldr r3, [r3, #0]
8002598: 68db ldr r3, [r3, #12]
800259a: b29a uxth r2, r3
800259c: 2308 movs r3, #8
800259e: 18fb adds r3, r7, r3
80025a0: 21fe movs r1, #254 @ 0xfe
80025a2: 400a ands r2, r1
80025a4: 801a strh r2, [r3, #0]
/* If 10bits addressing mode is selected */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
80025a6: 687b ldr r3, [r7, #4]
80025a8: 68db ldr r3, [r3, #12]
80025aa: 2b02 cmp r3, #2
80025ac: d148 bne.n 8002640 <I2C_ITAddrCplt+0x104>
{
if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
80025ae: 0021 movs r1, r4
80025b0: 187b adds r3, r7, r1
80025b2: 881b ldrh r3, [r3, #0]
80025b4: 09db lsrs r3, r3, #7
80025b6: b29a uxth r2, r3
80025b8: 183b adds r3, r7, r0
80025ba: 881b ldrh r3, [r3, #0]
80025bc: 4053 eors r3, r2
80025be: b29b uxth r3, r3
80025c0: 001a movs r2, r3
80025c2: 2306 movs r3, #6
80025c4: 4013 ands r3, r2
80025c6: d120 bne.n 800260a <I2C_ITAddrCplt+0xce>
{
slaveaddrcode = ownadd1code;
80025c8: 183b adds r3, r7, r0
80025ca: 187a adds r2, r7, r1
80025cc: 8812 ldrh r2, [r2, #0]
80025ce: 801a strh r2, [r3, #0]
hi2c->AddrEventCount++;
80025d0: 687b ldr r3, [r7, #4]
80025d2: 6c9b ldr r3, [r3, #72] @ 0x48
80025d4: 1c5a adds r2, r3, #1
80025d6: 687b ldr r3, [r7, #4]
80025d8: 649a str r2, [r3, #72] @ 0x48
if (hi2c->AddrEventCount == 2U)
80025da: 687b ldr r3, [r7, #4]
80025dc: 6c9b ldr r3, [r3, #72] @ 0x48
80025de: 2b02 cmp r3, #2
80025e0: d14c bne.n 800267c <I2C_ITAddrCplt+0x140>
{
/* Reset Address Event counter */
hi2c->AddrEventCount = 0U;
80025e2: 687b ldr r3, [r7, #4]
80025e4: 2200 movs r2, #0
80025e6: 649a str r2, [r3, #72] @ 0x48
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
80025e8: 687b ldr r3, [r7, #4]
80025ea: 681b ldr r3, [r3, #0]
80025ec: 2208 movs r2, #8
80025ee: 61da str r2, [r3, #28]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80025f0: 687b ldr r3, [r7, #4]
80025f2: 2240 movs r2, #64 @ 0x40
80025f4: 2100 movs r1, #0
80025f6: 5499 strb r1, [r3, r2]
/* Call Slave Addr callback */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
80025f8: 183b adds r3, r7, r0
80025fa: 881a ldrh r2, [r3, #0]
80025fc: 197b adds r3, r7, r5
80025fe: 7819 ldrb r1, [r3, #0]
8002600: 687b ldr r3, [r7, #4]
8002602: 0018 movs r0, r3
8002604: f7fe f88e bl 8000724 <HAL_I2C_AddrCallback>
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
}
}
8002608: e038 b.n 800267c <I2C_ITAddrCplt+0x140>
slaveaddrcode = ownadd2code;
800260a: 240c movs r4, #12
800260c: 193b adds r3, r7, r4
800260e: 2208 movs r2, #8
8002610: 18ba adds r2, r7, r2
8002612: 8812 ldrh r2, [r2, #0]
8002614: 801a strh r2, [r3, #0]
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
8002616: 2380 movs r3, #128 @ 0x80
8002618: 021a lsls r2, r3, #8
800261a: 687b ldr r3, [r7, #4]
800261c: 0011 movs r1, r2
800261e: 0018 movs r0, r3
8002620: f000 fdb4 bl 800318c <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
8002624: 687b ldr r3, [r7, #4]
8002626: 2240 movs r2, #64 @ 0x40
8002628: 2100 movs r1, #0
800262a: 5499 strb r1, [r3, r2]
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
800262c: 193b adds r3, r7, r4
800262e: 881a ldrh r2, [r3, #0]
8002630: 230f movs r3, #15
8002632: 18fb adds r3, r7, r3
8002634: 7819 ldrb r1, [r3, #0]
8002636: 687b ldr r3, [r7, #4]
8002638: 0018 movs r0, r3
800263a: f7fe f873 bl 8000724 <HAL_I2C_AddrCallback>
}
800263e: e01d b.n 800267c <I2C_ITAddrCplt+0x140>
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
8002640: 2380 movs r3, #128 @ 0x80
8002642: 021a lsls r2, r3, #8
8002644: 687b ldr r3, [r7, #4]
8002646: 0011 movs r1, r2
8002648: 0018 movs r0, r3
800264a: f000 fd9f bl 800318c <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
800264e: 687b ldr r3, [r7, #4]
8002650: 2240 movs r2, #64 @ 0x40
8002652: 2100 movs r1, #0
8002654: 5499 strb r1, [r3, r2]
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
8002656: 230c movs r3, #12
8002658: 18fb adds r3, r7, r3
800265a: 881a ldrh r2, [r3, #0]
800265c: 230f movs r3, #15
800265e: 18fb adds r3, r7, r3
8002660: 7819 ldrb r1, [r3, #0]
8002662: 687b ldr r3, [r7, #4]
8002664: 0018 movs r0, r3
8002666: f7fe f85d bl 8000724 <HAL_I2C_AddrCallback>
}
800266a: e007 b.n 800267c <I2C_ITAddrCplt+0x140>
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
800266c: 687b ldr r3, [r7, #4]
800266e: 681b ldr r3, [r3, #0]
8002670: 2208 movs r2, #8
8002672: 61da str r2, [r3, #28]
__HAL_UNLOCK(hi2c);
8002674: 687b ldr r3, [r7, #4]
8002676: 2240 movs r2, #64 @ 0x40
8002678: 2100 movs r1, #0
800267a: 5499 strb r1, [r3, r2]
}
800267c: 46c0 nop @ (mov r8, r8)
800267e: 46bd mov sp, r7
8002680: b004 add sp, #16
8002682: bdb0 pop {r4, r5, r7, pc}
08002684 <I2C_ITMasterSeqCplt>:
* @brief I2C Master sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
{
8002684: b580 push {r7, lr}
8002686: b082 sub sp, #8
8002688: af00 add r7, sp, #0
800268a: 6078 str r0, [r7, #4]
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
800268c: 687b ldr r3, [r7, #4]
800268e: 2242 movs r2, #66 @ 0x42
8002690: 2100 movs r1, #0
8002692: 5499 strb r1, [r3, r2]
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
8002694: 687b ldr r3, [r7, #4]
8002696: 2241 movs r2, #65 @ 0x41
8002698: 5c9b ldrb r3, [r3, r2]
800269a: b2db uxtb r3, r3
800269c: 2b21 cmp r3, #33 @ 0x21
800269e: d117 bne.n 80026d0 <I2C_ITMasterSeqCplt+0x4c>
{
hi2c->State = HAL_I2C_STATE_READY;
80026a0: 687b ldr r3, [r7, #4]
80026a2: 2241 movs r2, #65 @ 0x41
80026a4: 2120 movs r1, #32
80026a6: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
80026a8: 687b ldr r3, [r7, #4]
80026aa: 2211 movs r2, #17
80026ac: 631a str r2, [r3, #48] @ 0x30
hi2c->XferISR = NULL;
80026ae: 687b ldr r3, [r7, #4]
80026b0: 2200 movs r2, #0
80026b2: 635a str r2, [r3, #52] @ 0x34
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
80026b4: 687b ldr r3, [r7, #4]
80026b6: 2101 movs r1, #1
80026b8: 0018 movs r0, r3
80026ba: f000 fd67 bl 800318c <I2C_Disable_IRQ>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80026be: 687b ldr r3, [r7, #4]
80026c0: 2240 movs r2, #64 @ 0x40
80026c2: 2100 movs r1, #0
80026c4: 5499 strb r1, [r3, r2]
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->MasterTxCpltCallback(hi2c);
#else
HAL_I2C_MasterTxCpltCallback(hi2c);
80026c6: 687b ldr r3, [r7, #4]
80026c8: 0018 movs r0, r3
80026ca: f7ff faf6 bl 8001cba <HAL_I2C_MasterTxCpltCallback>
hi2c->MasterRxCpltCallback(hi2c);
#else
HAL_I2C_MasterRxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
80026ce: e016 b.n 80026fe <I2C_ITMasterSeqCplt+0x7a>
hi2c->State = HAL_I2C_STATE_READY;
80026d0: 687b ldr r3, [r7, #4]
80026d2: 2241 movs r2, #65 @ 0x41
80026d4: 2120 movs r1, #32
80026d6: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
80026d8: 687b ldr r3, [r7, #4]
80026da: 2212 movs r2, #18
80026dc: 631a str r2, [r3, #48] @ 0x30
hi2c->XferISR = NULL;
80026de: 687b ldr r3, [r7, #4]
80026e0: 2200 movs r2, #0
80026e2: 635a str r2, [r3, #52] @ 0x34
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
80026e4: 687b ldr r3, [r7, #4]
80026e6: 2102 movs r1, #2
80026e8: 0018 movs r0, r3
80026ea: f000 fd4f bl 800318c <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
80026ee: 687b ldr r3, [r7, #4]
80026f0: 2240 movs r2, #64 @ 0x40
80026f2: 2100 movs r1, #0
80026f4: 5499 strb r1, [r3, r2]
HAL_I2C_MasterRxCpltCallback(hi2c);
80026f6: 687b ldr r3, [r7, #4]
80026f8: 0018 movs r0, r3
80026fa: f7ff fae6 bl 8001cca <HAL_I2C_MasterRxCpltCallback>
}
80026fe: 46c0 nop @ (mov r8, r8)
8002700: 46bd mov sp, r7
8002702: b002 add sp, #8
8002704: bd80 pop {r7, pc}
...
08002708 <I2C_ITSlaveSeqCplt>:
* @brief I2C Slave sequential complete process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
8002708: b580 push {r7, lr}
800270a: b084 sub sp, #16
800270c: af00 add r7, sp, #0
800270e: 6078 str r0, [r7, #4]
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
8002710: 687b ldr r3, [r7, #4]
8002712: 681b ldr r3, [r3, #0]
8002714: 681b ldr r3, [r3, #0]
8002716: 60fb str r3, [r7, #12]
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
8002718: 687b ldr r3, [r7, #4]
800271a: 2242 movs r2, #66 @ 0x42
800271c: 2100 movs r1, #0
800271e: 5499 strb r1, [r3, r2]
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
8002720: 68fa ldr r2, [r7, #12]
8002722: 2380 movs r3, #128 @ 0x80
8002724: 01db lsls r3, r3, #7
8002726: 4013 ands r3, r2
8002728: d008 beq.n 800273c <I2C_ITSlaveSeqCplt+0x34>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
800272a: 687b ldr r3, [r7, #4]
800272c: 681b ldr r3, [r3, #0]
800272e: 681a ldr r2, [r3, #0]
8002730: 687b ldr r3, [r7, #4]
8002732: 681b ldr r3, [r3, #0]
8002734: 4924 ldr r1, [pc, #144] @ (80027c8 <I2C_ITSlaveSeqCplt+0xc0>)
8002736: 400a ands r2, r1
8002738: 601a str r2, [r3, #0]
800273a: e00c b.n 8002756 <I2C_ITSlaveSeqCplt+0x4e>
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
800273c: 68fa ldr r2, [r7, #12]
800273e: 2380 movs r3, #128 @ 0x80
8002740: 021b lsls r3, r3, #8
8002742: 4013 ands r3, r2
8002744: d007 beq.n 8002756 <I2C_ITSlaveSeqCplt+0x4e>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8002746: 687b ldr r3, [r7, #4]
8002748: 681b ldr r3, [r3, #0]
800274a: 681a ldr r2, [r3, #0]
800274c: 687b ldr r3, [r7, #4]
800274e: 681b ldr r3, [r3, #0]
8002750: 491e ldr r1, [pc, #120] @ (80027cc <I2C_ITSlaveSeqCplt+0xc4>)
8002752: 400a ands r2, r1
8002754: 601a str r2, [r3, #0]
else
{
/* Do nothing */
}
if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
8002756: 687b ldr r3, [r7, #4]
8002758: 2241 movs r2, #65 @ 0x41
800275a: 5c9b ldrb r3, [r3, r2]
800275c: b2db uxtb r3, r3
800275e: 2b29 cmp r3, #41 @ 0x29
8002760: d114 bne.n 800278c <I2C_ITSlaveSeqCplt+0x84>
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
8002762: 687b ldr r3, [r7, #4]
8002764: 2241 movs r2, #65 @ 0x41
8002766: 2128 movs r1, #40 @ 0x28
8002768: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
800276a: 687b ldr r3, [r7, #4]
800276c: 2221 movs r2, #33 @ 0x21
800276e: 631a str r2, [r3, #48] @ 0x30
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
8002770: 687b ldr r3, [r7, #4]
8002772: 2101 movs r1, #1
8002774: 0018 movs r0, r3
8002776: f000 fd09 bl 800318c <I2C_Disable_IRQ>
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800277a: 687b ldr r3, [r7, #4]
800277c: 2240 movs r2, #64 @ 0x40
800277e: 2100 movs r1, #0
8002780: 5499 strb r1, [r3, r2]
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
8002782: 687b ldr r3, [r7, #4]
8002784: 0018 movs r0, r3
8002786: f7fe f903 bl 8000990 <HAL_I2C_SlaveTxCpltCallback>
}
else
{
/* Nothing to do */
}
}
800278a: e019 b.n 80027c0 <I2C_ITSlaveSeqCplt+0xb8>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
800278c: 687b ldr r3, [r7, #4]
800278e: 2241 movs r2, #65 @ 0x41
8002790: 5c9b ldrb r3, [r3, r2]
8002792: b2db uxtb r3, r3
8002794: 2b2a cmp r3, #42 @ 0x2a
8002796: d113 bne.n 80027c0 <I2C_ITSlaveSeqCplt+0xb8>
hi2c->State = HAL_I2C_STATE_LISTEN;
8002798: 687b ldr r3, [r7, #4]
800279a: 2241 movs r2, #65 @ 0x41
800279c: 2128 movs r1, #40 @ 0x28
800279e: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
80027a0: 687b ldr r3, [r7, #4]
80027a2: 2222 movs r2, #34 @ 0x22
80027a4: 631a str r2, [r3, #48] @ 0x30
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
80027a6: 687b ldr r3, [r7, #4]
80027a8: 2102 movs r1, #2
80027aa: 0018 movs r0, r3
80027ac: f000 fcee bl 800318c <I2C_Disable_IRQ>
__HAL_UNLOCK(hi2c);
80027b0: 687b ldr r3, [r7, #4]
80027b2: 2240 movs r2, #64 @ 0x40
80027b4: 2100 movs r1, #0
80027b6: 5499 strb r1, [r3, r2]
HAL_I2C_SlaveRxCpltCallback(hi2c);
80027b8: 687b ldr r3, [r7, #4]
80027ba: 0018 movs r0, r3
80027bc: f7fe f898 bl 80008f0 <HAL_I2C_SlaveRxCpltCallback>
}
80027c0: 46c0 nop @ (mov r8, r8)
80027c2: 46bd mov sp, r7
80027c4: b004 add sp, #16
80027c6: bd80 pop {r7, pc}
80027c8: ffffbfff .word 0xffffbfff
80027cc: ffff7fff .word 0xffff7fff
080027d0 <I2C_ITMasterCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
80027d0: b580 push {r7, lr}
80027d2: b086 sub sp, #24
80027d4: af00 add r7, sp, #0
80027d6: 6078 str r0, [r7, #4]
80027d8: 6039 str r1, [r7, #0]
uint32_t tmperror;
uint32_t tmpITFlags = ITFlags;
80027da: 683b ldr r3, [r7, #0]
80027dc: 617b str r3, [r7, #20]
__IO uint32_t tmpreg;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
80027de: 687b ldr r3, [r7, #4]
80027e0: 681b ldr r3, [r3, #0]
80027e2: 2220 movs r2, #32
80027e4: 61da str r2, [r3, #28]
/* Disable Interrupts and Store Previous state */
if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
80027e6: 687b ldr r3, [r7, #4]
80027e8: 2241 movs r2, #65 @ 0x41
80027ea: 5c9b ldrb r3, [r3, r2]
80027ec: b2db uxtb r3, r3
80027ee: 2b21 cmp r3, #33 @ 0x21
80027f0: d108 bne.n 8002804 <I2C_ITMasterCplt+0x34>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
80027f2: 687b ldr r3, [r7, #4]
80027f4: 2101 movs r1, #1
80027f6: 0018 movs r0, r3
80027f8: f000 fcc8 bl 800318c <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
80027fc: 687b ldr r3, [r7, #4]
80027fe: 2211 movs r2, #17
8002800: 631a str r2, [r3, #48] @ 0x30
8002802: e00d b.n 8002820 <I2C_ITMasterCplt+0x50>
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002804: 687b ldr r3, [r7, #4]
8002806: 2241 movs r2, #65 @ 0x41
8002808: 5c9b ldrb r3, [r3, r2]
800280a: b2db uxtb r3, r3
800280c: 2b22 cmp r3, #34 @ 0x22
800280e: d107 bne.n 8002820 <I2C_ITMasterCplt+0x50>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
8002810: 687b ldr r3, [r7, #4]
8002812: 2102 movs r1, #2
8002814: 0018 movs r0, r3
8002816: f000 fcb9 bl 800318c <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
800281a: 687b ldr r3, [r7, #4]
800281c: 2212 movs r2, #18
800281e: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8002820: 687b ldr r3, [r7, #4]
8002822: 681b ldr r3, [r3, #0]
8002824: 685a ldr r2, [r3, #4]
8002826: 687b ldr r3, [r7, #4]
8002828: 681b ldr r3, [r3, #0]
800282a: 494e ldr r1, [pc, #312] @ (8002964 <I2C_ITMasterCplt+0x194>)
800282c: 400a ands r2, r1
800282e: 605a str r2, [r3, #4]
/* Reset handle parameters */
hi2c->XferISR = NULL;
8002830: 687b ldr r3, [r7, #4]
8002832: 2200 movs r2, #0
8002834: 635a str r2, [r3, #52] @ 0x34
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8002836: 687b ldr r3, [r7, #4]
8002838: 4a4b ldr r2, [pc, #300] @ (8002968 <I2C_ITMasterCplt+0x198>)
800283a: 62da str r2, [r3, #44] @ 0x2c
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
800283c: 697b ldr r3, [r7, #20]
800283e: 2210 movs r2, #16
8002840: 4013 ands r3, r2
8002842: d009 beq.n 8002858 <I2C_ITMasterCplt+0x88>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002844: 687b ldr r3, [r7, #4]
8002846: 681b ldr r3, [r3, #0]
8002848: 2210 movs r2, #16
800284a: 61da str r2, [r3, #28]
/* Set acknowledge error code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
800284c: 687b ldr r3, [r7, #4]
800284e: 6c5b ldr r3, [r3, #68] @ 0x44
8002850: 2204 movs r2, #4
8002852: 431a orrs r2, r3
8002854: 687b ldr r3, [r7, #4]
8002856: 645a str r2, [r3, #68] @ 0x44
}
/* Fetch Last receive data if any */
if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
8002858: 687b ldr r3, [r7, #4]
800285a: 2241 movs r2, #65 @ 0x41
800285c: 5c9b ldrb r3, [r3, r2]
800285e: b2db uxtb r3, r3
8002860: 2b60 cmp r3, #96 @ 0x60
8002862: d109 bne.n 8002878 <I2C_ITMasterCplt+0xa8>
8002864: 697b ldr r3, [r7, #20]
8002866: 2204 movs r2, #4
8002868: 4013 ands r3, r2
800286a: d005 beq.n 8002878 <I2C_ITMasterCplt+0xa8>
{
/* Read data from RXDR */
tmpreg = (uint8_t)hi2c->Instance->RXDR;
800286c: 687b ldr r3, [r7, #4]
800286e: 681b ldr r3, [r3, #0]
8002870: 6a5b ldr r3, [r3, #36] @ 0x24
8002872: b2db uxtb r3, r3
8002874: 60fb str r3, [r7, #12]
UNUSED(tmpreg);
8002876: 68fb ldr r3, [r7, #12]
}
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8002878: 687b ldr r3, [r7, #4]
800287a: 0018 movs r0, r3
800287c: f000 fb81 bl 8002f82 <I2C_Flush_TXDR>
/* Store current volatile hi2c->ErrorCode, misra rule */
tmperror = hi2c->ErrorCode;
8002880: 687b ldr r3, [r7, #4]
8002882: 6c5b ldr r3, [r3, #68] @ 0x44
8002884: 613b str r3, [r7, #16]
/* Call the corresponding callback to inform upper layer of End of Transfer */
if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
8002886: 687b ldr r3, [r7, #4]
8002888: 2241 movs r2, #65 @ 0x41
800288a: 5c9b ldrb r3, [r3, r2]
800288c: b2db uxtb r3, r3
800288e: 2b60 cmp r3, #96 @ 0x60
8002890: d002 beq.n 8002898 <I2C_ITMasterCplt+0xc8>
8002892: 693b ldr r3, [r7, #16]
8002894: 2b00 cmp r3, #0
8002896: d007 beq.n 80028a8 <I2C_ITMasterCplt+0xd8>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
8002898: 687b ldr r3, [r7, #4]
800289a: 6c5a ldr r2, [r3, #68] @ 0x44
800289c: 687b ldr r3, [r7, #4]
800289e: 0011 movs r1, r2
80028a0: 0018 movs r0, r3
80028a2: f000 fa43 bl 8002d2c <I2C_ITError>
}
else
{
/* Nothing to do */
}
}
80028a6: e058 b.n 800295a <I2C_ITMasterCplt+0x18a>
else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
80028a8: 687b ldr r3, [r7, #4]
80028aa: 2241 movs r2, #65 @ 0x41
80028ac: 5c9b ldrb r3, [r3, r2]
80028ae: b2db uxtb r3, r3
80028b0: 2b21 cmp r3, #33 @ 0x21
80028b2: d126 bne.n 8002902 <I2C_ITMasterCplt+0x132>
hi2c->State = HAL_I2C_STATE_READY;
80028b4: 687b ldr r3, [r7, #4]
80028b6: 2241 movs r2, #65 @ 0x41
80028b8: 2120 movs r1, #32
80028ba: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
80028bc: 687b ldr r3, [r7, #4]
80028be: 2200 movs r2, #0
80028c0: 631a str r2, [r3, #48] @ 0x30
if (hi2c->Mode == HAL_I2C_MODE_MEM)
80028c2: 687b ldr r3, [r7, #4]
80028c4: 2242 movs r2, #66 @ 0x42
80028c6: 5c9b ldrb r3, [r3, r2]
80028c8: b2db uxtb r3, r3
80028ca: 2b40 cmp r3, #64 @ 0x40
80028cc: d10c bne.n 80028e8 <I2C_ITMasterCplt+0x118>
hi2c->Mode = HAL_I2C_MODE_NONE;
80028ce: 687b ldr r3, [r7, #4]
80028d0: 2242 movs r2, #66 @ 0x42
80028d2: 2100 movs r1, #0
80028d4: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(hi2c);
80028d6: 687b ldr r3, [r7, #4]
80028d8: 2240 movs r2, #64 @ 0x40
80028da: 2100 movs r1, #0
80028dc: 5499 strb r1, [r3, r2]
HAL_I2C_MemTxCpltCallback(hi2c);
80028de: 687b ldr r3, [r7, #4]
80028e0: 0018 movs r0, r3
80028e2: f7ff f9fa bl 8001cda <HAL_I2C_MemTxCpltCallback>
}
80028e6: e038 b.n 800295a <I2C_ITMasterCplt+0x18a>
hi2c->Mode = HAL_I2C_MODE_NONE;
80028e8: 687b ldr r3, [r7, #4]
80028ea: 2242 movs r2, #66 @ 0x42
80028ec: 2100 movs r1, #0
80028ee: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(hi2c);
80028f0: 687b ldr r3, [r7, #4]
80028f2: 2240 movs r2, #64 @ 0x40
80028f4: 2100 movs r1, #0
80028f6: 5499 strb r1, [r3, r2]
HAL_I2C_MasterTxCpltCallback(hi2c);
80028f8: 687b ldr r3, [r7, #4]
80028fa: 0018 movs r0, r3
80028fc: f7ff f9dd bl 8001cba <HAL_I2C_MasterTxCpltCallback>
}
8002900: e02b b.n 800295a <I2C_ITMasterCplt+0x18a>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002902: 687b ldr r3, [r7, #4]
8002904: 2241 movs r2, #65 @ 0x41
8002906: 5c9b ldrb r3, [r3, r2]
8002908: b2db uxtb r3, r3
800290a: 2b22 cmp r3, #34 @ 0x22
800290c: d125 bne.n 800295a <I2C_ITMasterCplt+0x18a>
hi2c->State = HAL_I2C_STATE_READY;
800290e: 687b ldr r3, [r7, #4]
8002910: 2241 movs r2, #65 @ 0x41
8002912: 2120 movs r1, #32
8002914: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8002916: 687b ldr r3, [r7, #4]
8002918: 2200 movs r2, #0
800291a: 631a str r2, [r3, #48] @ 0x30
if (hi2c->Mode == HAL_I2C_MODE_MEM)
800291c: 687b ldr r3, [r7, #4]
800291e: 2242 movs r2, #66 @ 0x42
8002920: 5c9b ldrb r3, [r3, r2]
8002922: b2db uxtb r3, r3
8002924: 2b40 cmp r3, #64 @ 0x40
8002926: d10c bne.n 8002942 <I2C_ITMasterCplt+0x172>
hi2c->Mode = HAL_I2C_MODE_NONE;
8002928: 687b ldr r3, [r7, #4]
800292a: 2242 movs r2, #66 @ 0x42
800292c: 2100 movs r1, #0
800292e: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(hi2c);
8002930: 687b ldr r3, [r7, #4]
8002932: 2240 movs r2, #64 @ 0x40
8002934: 2100 movs r1, #0
8002936: 5499 strb r1, [r3, r2]
HAL_I2C_MemRxCpltCallback(hi2c);
8002938: 687b ldr r3, [r7, #4]
800293a: 0018 movs r0, r3
800293c: f7ff f9d5 bl 8001cea <HAL_I2C_MemRxCpltCallback>
}
8002940: e00b b.n 800295a <I2C_ITMasterCplt+0x18a>
hi2c->Mode = HAL_I2C_MODE_NONE;
8002942: 687b ldr r3, [r7, #4]
8002944: 2242 movs r2, #66 @ 0x42
8002946: 2100 movs r1, #0
8002948: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(hi2c);
800294a: 687b ldr r3, [r7, #4]
800294c: 2240 movs r2, #64 @ 0x40
800294e: 2100 movs r1, #0
8002950: 5499 strb r1, [r3, r2]
HAL_I2C_MasterRxCpltCallback(hi2c);
8002952: 687b ldr r3, [r7, #4]
8002954: 0018 movs r0, r3
8002956: f7ff f9b8 bl 8001cca <HAL_I2C_MasterRxCpltCallback>
}
800295a: 46c0 nop @ (mov r8, r8)
800295c: 46bd mov sp, r7
800295e: b006 add sp, #24
8002960: bd80 pop {r7, pc}
8002962: 46c0 nop @ (mov r8, r8)
8002964: fe00e800 .word 0xfe00e800
8002968: ffff0000 .word 0xffff0000
0800296c <I2C_ITSlaveCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
800296c: b580 push {r7, lr}
800296e: b086 sub sp, #24
8002970: af00 add r7, sp, #0
8002972: 6078 str r0, [r7, #4]
8002974: 6039 str r1, [r7, #0]
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
8002976: 687b ldr r3, [r7, #4]
8002978: 681b ldr r3, [r3, #0]
800297a: 681b ldr r3, [r3, #0]
800297c: 613b str r3, [r7, #16]
uint32_t tmpITFlags = ITFlags;
800297e: 683b ldr r3, [r7, #0]
8002980: 617b str r3, [r7, #20]
uint32_t tmpoptions = hi2c->XferOptions;
8002982: 687b ldr r3, [r7, #4]
8002984: 6adb ldr r3, [r3, #44] @ 0x2c
8002986: 60fb str r3, [r7, #12]
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
8002988: 200b movs r0, #11
800298a: 183b adds r3, r7, r0
800298c: 687a ldr r2, [r7, #4]
800298e: 2141 movs r1, #65 @ 0x41
8002990: 5c52 ldrb r2, [r2, r1]
8002992: 701a strb r2, [r3, #0]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8002994: 687b ldr r3, [r7, #4]
8002996: 681b ldr r3, [r3, #0]
8002998: 2220 movs r2, #32
800299a: 61da str r2, [r3, #28]
/* Disable Interrupts and Store Previous state */
if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
800299c: 183b adds r3, r7, r0
800299e: 781b ldrb r3, [r3, #0]
80029a0: 2b21 cmp r3, #33 @ 0x21
80029a2: d003 beq.n 80029ac <I2C_ITSlaveCplt+0x40>
80029a4: 183b adds r3, r7, r0
80029a6: 781b ldrb r3, [r3, #0]
80029a8: 2b29 cmp r3, #41 @ 0x29
80029aa: d109 bne.n 80029c0 <I2C_ITSlaveCplt+0x54>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
80029ac: 4aac ldr r2, [pc, #688] @ (8002c60 <I2C_ITSlaveCplt+0x2f4>)
80029ae: 687b ldr r3, [r7, #4]
80029b0: 0011 movs r1, r2
80029b2: 0018 movs r0, r3
80029b4: f000 fbea bl 800318c <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
80029b8: 687b ldr r3, [r7, #4]
80029ba: 2221 movs r2, #33 @ 0x21
80029bc: 631a str r2, [r3, #48] @ 0x30
80029be: e020 b.n 8002a02 <I2C_ITSlaveCplt+0x96>
}
else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
80029c0: 220b movs r2, #11
80029c2: 18bb adds r3, r7, r2
80029c4: 781b ldrb r3, [r3, #0]
80029c6: 2b22 cmp r3, #34 @ 0x22
80029c8: d003 beq.n 80029d2 <I2C_ITSlaveCplt+0x66>
80029ca: 18bb adds r3, r7, r2
80029cc: 781b ldrb r3, [r3, #0]
80029ce: 2b2a cmp r3, #42 @ 0x2a
80029d0: d109 bne.n 80029e6 <I2C_ITSlaveCplt+0x7a>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
80029d2: 4aa4 ldr r2, [pc, #656] @ (8002c64 <I2C_ITSlaveCplt+0x2f8>)
80029d4: 687b ldr r3, [r7, #4]
80029d6: 0011 movs r1, r2
80029d8: 0018 movs r0, r3
80029da: f000 fbd7 bl 800318c <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
80029de: 687b ldr r3, [r7, #4]
80029e0: 2222 movs r2, #34 @ 0x22
80029e2: 631a str r2, [r3, #48] @ 0x30
80029e4: e00d b.n 8002a02 <I2C_ITSlaveCplt+0x96>
}
else if (tmpstate == HAL_I2C_STATE_LISTEN)
80029e6: 230b movs r3, #11
80029e8: 18fb adds r3, r7, r3
80029ea: 781b ldrb r3, [r3, #0]
80029ec: 2b28 cmp r3, #40 @ 0x28
80029ee: d108 bne.n 8002a02 <I2C_ITSlaveCplt+0x96>
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
80029f0: 4a9d ldr r2, [pc, #628] @ (8002c68 <I2C_ITSlaveCplt+0x2fc>)
80029f2: 687b ldr r3, [r7, #4]
80029f4: 0011 movs r1, r2
80029f6: 0018 movs r0, r3
80029f8: f000 fbc8 bl 800318c <I2C_Disable_IRQ>
hi2c->PreviousState = I2C_STATE_NONE;
80029fc: 687b ldr r3, [r7, #4]
80029fe: 2200 movs r2, #0
8002a00: 631a str r2, [r3, #48] @ 0x30
{
/* Do nothing */
}
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
8002a02: 687b ldr r3, [r7, #4]
8002a04: 681b ldr r3, [r3, #0]
8002a06: 685a ldr r2, [r3, #4]
8002a08: 687b ldr r3, [r7, #4]
8002a0a: 681b ldr r3, [r3, #0]
8002a0c: 2180 movs r1, #128 @ 0x80
8002a0e: 0209 lsls r1, r1, #8
8002a10: 430a orrs r2, r1
8002a12: 605a str r2, [r3, #4]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
8002a14: 687b ldr r3, [r7, #4]
8002a16: 681b ldr r3, [r3, #0]
8002a18: 685a ldr r2, [r3, #4]
8002a1a: 687b ldr r3, [r7, #4]
8002a1c: 681b ldr r3, [r3, #0]
8002a1e: 4993 ldr r1, [pc, #588] @ (8002c6c <I2C_ITSlaveCplt+0x300>)
8002a20: 400a ands r2, r1
8002a22: 605a str r2, [r3, #4]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8002a24: 687b ldr r3, [r7, #4]
8002a26: 0018 movs r0, r3
8002a28: f000 faab bl 8002f82 <I2C_Flush_TXDR>
/* If a DMA is ongoing, Update handle size context */
if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
8002a2c: 693a ldr r2, [r7, #16]
8002a2e: 2380 movs r3, #128 @ 0x80
8002a30: 01db lsls r3, r3, #7
8002a32: 4013 ands r3, r2
8002a34: d013 beq.n 8002a5e <I2C_ITSlaveCplt+0xf2>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8002a36: 687b ldr r3, [r7, #4]
8002a38: 681b ldr r3, [r3, #0]
8002a3a: 681a ldr r2, [r3, #0]
8002a3c: 687b ldr r3, [r7, #4]
8002a3e: 681b ldr r3, [r3, #0]
8002a40: 498b ldr r1, [pc, #556] @ (8002c70 <I2C_ITSlaveCplt+0x304>)
8002a42: 400a ands r2, r1
8002a44: 601a str r2, [r3, #0]
if (hi2c->hdmatx != NULL)
8002a46: 687b ldr r3, [r7, #4]
8002a48: 6b9b ldr r3, [r3, #56] @ 0x38
8002a4a: 2b00 cmp r3, #0
8002a4c: d01f beq.n 8002a8e <I2C_ITSlaveCplt+0x122>
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
8002a4e: 687b ldr r3, [r7, #4]
8002a50: 6b9b ldr r3, [r3, #56] @ 0x38
8002a52: 681b ldr r3, [r3, #0]
8002a54: 685b ldr r3, [r3, #4]
8002a56: b29a uxth r2, r3
8002a58: 687b ldr r3, [r7, #4]
8002a5a: 855a strh r2, [r3, #42] @ 0x2a
8002a5c: e017 b.n 8002a8e <I2C_ITSlaveCplt+0x122>
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
8002a5e: 693a ldr r2, [r7, #16]
8002a60: 2380 movs r3, #128 @ 0x80
8002a62: 021b lsls r3, r3, #8
8002a64: 4013 ands r3, r2
8002a66: d012 beq.n 8002a8e <I2C_ITSlaveCplt+0x122>
{
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 681b ldr r3, [r3, #0]
8002a6c: 681a ldr r2, [r3, #0]
8002a6e: 687b ldr r3, [r7, #4]
8002a70: 681b ldr r3, [r3, #0]
8002a72: 4980 ldr r1, [pc, #512] @ (8002c74 <I2C_ITSlaveCplt+0x308>)
8002a74: 400a ands r2, r1
8002a76: 601a str r2, [r3, #0]
if (hi2c->hdmarx != NULL)
8002a78: 687b ldr r3, [r7, #4]
8002a7a: 6bdb ldr r3, [r3, #60] @ 0x3c
8002a7c: 2b00 cmp r3, #0
8002a7e: d006 beq.n 8002a8e <I2C_ITSlaveCplt+0x122>
{
hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
8002a80: 687b ldr r3, [r7, #4]
8002a82: 6bdb ldr r3, [r3, #60] @ 0x3c
8002a84: 681b ldr r3, [r3, #0]
8002a86: 685b ldr r3, [r3, #4]
8002a88: b29a uxth r2, r3
8002a8a: 687b ldr r3, [r7, #4]
8002a8c: 855a strh r2, [r3, #42] @ 0x2a
{
/* Do nothing */
}
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
8002a8e: 697b ldr r3, [r7, #20]
8002a90: 2204 movs r2, #4
8002a92: 4013 ands r3, r2
8002a94: d020 beq.n 8002ad8 <I2C_ITSlaveCplt+0x16c>
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
8002a96: 697b ldr r3, [r7, #20]
8002a98: 2204 movs r2, #4
8002a9a: 4393 bics r3, r2
8002a9c: 617b str r3, [r7, #20]
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8002a9e: 687b ldr r3, [r7, #4]
8002aa0: 681b ldr r3, [r3, #0]
8002aa2: 6a5a ldr r2, [r3, #36] @ 0x24
8002aa4: 687b ldr r3, [r7, #4]
8002aa6: 6a5b ldr r3, [r3, #36] @ 0x24
8002aa8: b2d2 uxtb r2, r2
8002aaa: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8002aac: 687b ldr r3, [r7, #4]
8002aae: 6a5b ldr r3, [r3, #36] @ 0x24
8002ab0: 1c5a adds r2, r3, #1
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 625a str r2, [r3, #36] @ 0x24
if ((hi2c->XferSize > 0U))
8002ab6: 687b ldr r3, [r7, #4]
8002ab8: 8d1b ldrh r3, [r3, #40] @ 0x28
8002aba: 2b00 cmp r3, #0
8002abc: d00c beq.n 8002ad8 <I2C_ITSlaveCplt+0x16c>
{
hi2c->XferSize--;
8002abe: 687b ldr r3, [r7, #4]
8002ac0: 8d1b ldrh r3, [r3, #40] @ 0x28
8002ac2: 3b01 subs r3, #1
8002ac4: b29a uxth r2, r3
8002ac6: 687b ldr r3, [r7, #4]
8002ac8: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8002aca: 687b ldr r3, [r7, #4]
8002acc: 8d5b ldrh r3, [r3, #42] @ 0x2a
8002ace: b29b uxth r3, r3
8002ad0: 3b01 subs r3, #1
8002ad2: b29a uxth r2, r3
8002ad4: 687b ldr r3, [r7, #4]
8002ad6: 855a strh r2, [r3, #42] @ 0x2a
}
}
/* All data are not transferred, so set error code accordingly */
if (hi2c->XferCount != 0U)
8002ad8: 687b ldr r3, [r7, #4]
8002ada: 8d5b ldrh r3, [r3, #42] @ 0x2a
8002adc: b29b uxth r3, r3
8002ade: 2b00 cmp r3, #0
8002ae0: d005 beq.n 8002aee <I2C_ITSlaveCplt+0x182>
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8002ae2: 687b ldr r3, [r7, #4]
8002ae4: 6c5b ldr r3, [r3, #68] @ 0x44
8002ae6: 2204 movs r2, #4
8002ae8: 431a orrs r2, r3
8002aea: 687b ldr r3, [r7, #4]
8002aec: 645a str r2, [r3, #68] @ 0x44
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8002aee: 697b ldr r3, [r7, #20]
8002af0: 2210 movs r2, #16
8002af2: 4013 ands r3, r2
8002af4: d04f beq.n 8002b96 <I2C_ITSlaveCplt+0x22a>
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
8002af6: 693b ldr r3, [r7, #16]
8002af8: 2210 movs r2, #16
8002afa: 4013 ands r3, r2
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
8002afc: d04b beq.n 8002b96 <I2C_ITSlaveCplt+0x22a>
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
8002afe: 687b ldr r3, [r7, #4]
8002b00: 8d5b ldrh r3, [r3, #42] @ 0x2a
8002b02: b29b uxth r3, r3
8002b04: 2b00 cmp r3, #0
8002b06: d12d bne.n 8002b64 <I2C_ITSlaveCplt+0x1f8>
{
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
8002b08: 687b ldr r3, [r7, #4]
8002b0a: 2241 movs r2, #65 @ 0x41
8002b0c: 5c9b ldrb r3, [r3, r2]
8002b0e: b2db uxtb r3, r3
8002b10: 2b28 cmp r3, #40 @ 0x28
8002b12: d10b bne.n 8002b2c <I2C_ITSlaveCplt+0x1c0>
8002b14: 68fa ldr r2, [r7, #12]
8002b16: 2380 movs r3, #128 @ 0x80
8002b18: 049b lsls r3, r3, #18
8002b1a: 429a cmp r2, r3
8002b1c: d106 bne.n 8002b2c <I2C_ITSlaveCplt+0x1c0>
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
8002b1e: 697a ldr r2, [r7, #20]
8002b20: 687b ldr r3, [r7, #4]
8002b22: 0011 movs r1, r2
8002b24: 0018 movs r0, r3
8002b26: f000 f8a9 bl 8002c7c <I2C_ITListenCplt>
8002b2a: e034 b.n 8002b96 <I2C_ITSlaveCplt+0x22a>
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
8002b2c: 687b ldr r3, [r7, #4]
8002b2e: 2241 movs r2, #65 @ 0x41
8002b30: 5c9b ldrb r3, [r3, r2]
8002b32: b2db uxtb r3, r3
8002b34: 2b29 cmp r3, #41 @ 0x29
8002b36: d110 bne.n 8002b5a <I2C_ITSlaveCplt+0x1ee>
8002b38: 68fb ldr r3, [r7, #12]
8002b3a: 4a4f ldr r2, [pc, #316] @ (8002c78 <I2C_ITSlaveCplt+0x30c>)
8002b3c: 4293 cmp r3, r2
8002b3e: d00c beq.n 8002b5a <I2C_ITSlaveCplt+0x1ee>
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002b40: 687b ldr r3, [r7, #4]
8002b42: 681b ldr r3, [r3, #0]
8002b44: 2210 movs r2, #16
8002b46: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8002b48: 687b ldr r3, [r7, #4]
8002b4a: 0018 movs r0, r3
8002b4c: f000 fa19 bl 8002f82 <I2C_Flush_TXDR>
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSeqCplt(hi2c);
8002b50: 687b ldr r3, [r7, #4]
8002b52: 0018 movs r0, r3
8002b54: f7ff fdd8 bl 8002708 <I2C_ITSlaveSeqCplt>
8002b58: e01d b.n 8002b96 <I2C_ITSlaveCplt+0x22a>
}
else
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002b5a: 687b ldr r3, [r7, #4]
8002b5c: 681b ldr r3, [r3, #0]
8002b5e: 2210 movs r2, #16
8002b60: 61da str r2, [r3, #28]
8002b62: e018 b.n 8002b96 <I2C_ITSlaveCplt+0x22a>
}
else
{
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002b64: 687b ldr r3, [r7, #4]
8002b66: 681b ldr r3, [r3, #0]
8002b68: 2210 movs r2, #16
8002b6a: 61da str r2, [r3, #28]
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8002b6c: 687b ldr r3, [r7, #4]
8002b6e: 6c5b ldr r3, [r3, #68] @ 0x44
8002b70: 2204 movs r2, #4
8002b72: 431a orrs r2, r3
8002b74: 687b ldr r3, [r7, #4]
8002b76: 645a str r2, [r3, #68] @ 0x44
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
8002b78: 68fb ldr r3, [r7, #12]
8002b7a: 2b00 cmp r3, #0
8002b7c: d004 beq.n 8002b88 <I2C_ITSlaveCplt+0x21c>
8002b7e: 68fa ldr r2, [r7, #12]
8002b80: 2380 movs r3, #128 @ 0x80
8002b82: 045b lsls r3, r3, #17
8002b84: 429a cmp r2, r3
8002b86: d106 bne.n 8002b96 <I2C_ITSlaveCplt+0x22a>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
8002b88: 687b ldr r3, [r7, #4]
8002b8a: 6c5a ldr r2, [r3, #68] @ 0x44
8002b8c: 687b ldr r3, [r7, #4]
8002b8e: 0011 movs r1, r2
8002b90: 0018 movs r0, r3
8002b92: f000 f8cb bl 8002d2c <I2C_ITError>
}
}
}
hi2c->Mode = HAL_I2C_MODE_NONE;
8002b96: 687b ldr r3, [r7, #4]
8002b98: 2242 movs r2, #66 @ 0x42
8002b9a: 2100 movs r1, #0
8002b9c: 5499 strb r1, [r3, r2]
hi2c->XferISR = NULL;
8002b9e: 687b ldr r3, [r7, #4]
8002ba0: 2200 movs r2, #0
8002ba2: 635a str r2, [r3, #52] @ 0x34
if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: 6c5b ldr r3, [r3, #68] @ 0x44
8002ba8: 2b00 cmp r3, #0
8002baa: d013 beq.n 8002bd4 <I2C_ITSlaveCplt+0x268>
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
8002bac: 687b ldr r3, [r7, #4]
8002bae: 6c5a ldr r2, [r3, #68] @ 0x44
8002bb0: 687b ldr r3, [r7, #4]
8002bb2: 0011 movs r1, r2
8002bb4: 0018 movs r0, r3
8002bb6: f000 f8b9 bl 8002d2c <I2C_ITError>
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
if (hi2c->State == HAL_I2C_STATE_LISTEN)
8002bba: 687b ldr r3, [r7, #4]
8002bbc: 2241 movs r2, #65 @ 0x41
8002bbe: 5c9b ldrb r3, [r3, r2]
8002bc0: b2db uxtb r3, r3
8002bc2: 2b28 cmp r3, #40 @ 0x28
8002bc4: d147 bne.n 8002c56 <I2C_ITSlaveCplt+0x2ea>
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
8002bc6: 697a ldr r2, [r7, #20]
8002bc8: 687b ldr r3, [r7, #4]
8002bca: 0011 movs r1, r2
8002bcc: 0018 movs r0, r3
8002bce: f000 f855 bl 8002c7c <I2C_ITListenCplt>
hi2c->SlaveTxCpltCallback(hi2c);
#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
8002bd2: e040 b.n 8002c56 <I2C_ITSlaveCplt+0x2ea>
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
8002bd4: 687b ldr r3, [r7, #4]
8002bd6: 6adb ldr r3, [r3, #44] @ 0x2c
8002bd8: 4a27 ldr r2, [pc, #156] @ (8002c78 <I2C_ITSlaveCplt+0x30c>)
8002bda: 4293 cmp r3, r2
8002bdc: d016 beq.n 8002c0c <I2C_ITSlaveCplt+0x2a0>
I2C_ITSlaveSeqCplt(hi2c);
8002bde: 687b ldr r3, [r7, #4]
8002be0: 0018 movs r0, r3
8002be2: f7ff fd91 bl 8002708 <I2C_ITSlaveSeqCplt>
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8002be6: 687b ldr r3, [r7, #4]
8002be8: 4a23 ldr r2, [pc, #140] @ (8002c78 <I2C_ITSlaveCplt+0x30c>)
8002bea: 62da str r2, [r3, #44] @ 0x2c
hi2c->State = HAL_I2C_STATE_READY;
8002bec: 687b ldr r3, [r7, #4]
8002bee: 2241 movs r2, #65 @ 0x41
8002bf0: 2120 movs r1, #32
8002bf2: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8002bf4: 687b ldr r3, [r7, #4]
8002bf6: 2200 movs r2, #0
8002bf8: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8002bfa: 687b ldr r3, [r7, #4]
8002bfc: 2240 movs r2, #64 @ 0x40
8002bfe: 2100 movs r1, #0
8002c00: 5499 strb r1, [r3, r2]
HAL_I2C_ListenCpltCallback(hi2c);
8002c02: 687b ldr r3, [r7, #4]
8002c04: 0018 movs r0, r3
8002c06: f7fd fd77 bl 80006f8 <HAL_I2C_ListenCpltCallback>
}
8002c0a: e024 b.n 8002c56 <I2C_ITSlaveCplt+0x2ea>
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
8002c0c: 687b ldr r3, [r7, #4]
8002c0e: 2241 movs r2, #65 @ 0x41
8002c10: 5c9b ldrb r3, [r3, r2]
8002c12: b2db uxtb r3, r3
8002c14: 2b22 cmp r3, #34 @ 0x22
8002c16: d10f bne.n 8002c38 <I2C_ITSlaveCplt+0x2cc>
hi2c->State = HAL_I2C_STATE_READY;
8002c18: 687b ldr r3, [r7, #4]
8002c1a: 2241 movs r2, #65 @ 0x41
8002c1c: 2120 movs r1, #32
8002c1e: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8002c20: 687b ldr r3, [r7, #4]
8002c22: 2200 movs r2, #0
8002c24: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8002c26: 687b ldr r3, [r7, #4]
8002c28: 2240 movs r2, #64 @ 0x40
8002c2a: 2100 movs r1, #0
8002c2c: 5499 strb r1, [r3, r2]
HAL_I2C_SlaveRxCpltCallback(hi2c);
8002c2e: 687b ldr r3, [r7, #4]
8002c30: 0018 movs r0, r3
8002c32: f7fd fe5d bl 80008f0 <HAL_I2C_SlaveRxCpltCallback>
}
8002c36: e00e b.n 8002c56 <I2C_ITSlaveCplt+0x2ea>
hi2c->State = HAL_I2C_STATE_READY;
8002c38: 687b ldr r3, [r7, #4]
8002c3a: 2241 movs r2, #65 @ 0x41
8002c3c: 2120 movs r1, #32
8002c3e: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8002c40: 687b ldr r3, [r7, #4]
8002c42: 2200 movs r2, #0
8002c44: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8002c46: 687b ldr r3, [r7, #4]
8002c48: 2240 movs r2, #64 @ 0x40
8002c4a: 2100 movs r1, #0
8002c4c: 5499 strb r1, [r3, r2]
HAL_I2C_SlaveTxCpltCallback(hi2c);
8002c4e: 687b ldr r3, [r7, #4]
8002c50: 0018 movs r0, r3
8002c52: f7fd fe9d bl 8000990 <HAL_I2C_SlaveTxCpltCallback>
}
8002c56: 46c0 nop @ (mov r8, r8)
8002c58: 46bd mov sp, r7
8002c5a: b006 add sp, #24
8002c5c: bd80 pop {r7, pc}
8002c5e: 46c0 nop @ (mov r8, r8)
8002c60: 00008001 .word 0x00008001
8002c64: 00008002 .word 0x00008002
8002c68: 00008003 .word 0x00008003
8002c6c: fe00e800 .word 0xfe00e800
8002c70: ffffbfff .word 0xffffbfff
8002c74: ffff7fff .word 0xffff7fff
8002c78: ffff0000 .word 0xffff0000
08002c7c <I2C_ITListenCplt>:
* @param hi2c I2C handle.
* @param ITFlags Interrupt flags to handle.
* @retval None
*/
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
8002c7c: b580 push {r7, lr}
8002c7e: b082 sub sp, #8
8002c80: af00 add r7, sp, #0
8002c82: 6078 str r0, [r7, #4]
8002c84: 6039 str r1, [r7, #0]
/* Reset handle parameters */
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8002c86: 687b ldr r3, [r7, #4]
8002c88: 4a26 ldr r2, [pc, #152] @ (8002d24 <I2C_ITListenCplt+0xa8>)
8002c8a: 62da str r2, [r3, #44] @ 0x2c
hi2c->PreviousState = I2C_STATE_NONE;
8002c8c: 687b ldr r3, [r7, #4]
8002c8e: 2200 movs r2, #0
8002c90: 631a str r2, [r3, #48] @ 0x30
hi2c->State = HAL_I2C_STATE_READY;
8002c92: 687b ldr r3, [r7, #4]
8002c94: 2241 movs r2, #65 @ 0x41
8002c96: 2120 movs r1, #32
8002c98: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
8002c9a: 687b ldr r3, [r7, #4]
8002c9c: 2242 movs r2, #66 @ 0x42
8002c9e: 2100 movs r1, #0
8002ca0: 5499 strb r1, [r3, r2]
hi2c->XferISR = NULL;
8002ca2: 687b ldr r3, [r7, #4]
8002ca4: 2200 movs r2, #0
8002ca6: 635a str r2, [r3, #52] @ 0x34
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
8002ca8: 683b ldr r3, [r7, #0]
8002caa: 2204 movs r2, #4
8002cac: 4013 ands r3, r2
8002cae: d022 beq.n 8002cf6 <I2C_ITListenCplt+0x7a>
{
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
8002cb0: 687b ldr r3, [r7, #4]
8002cb2: 681b ldr r3, [r3, #0]
8002cb4: 6a5a ldr r2, [r3, #36] @ 0x24
8002cb6: 687b ldr r3, [r7, #4]
8002cb8: 6a5b ldr r3, [r3, #36] @ 0x24
8002cba: b2d2 uxtb r2, r2
8002cbc: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
8002cbe: 687b ldr r3, [r7, #4]
8002cc0: 6a5b ldr r3, [r3, #36] @ 0x24
8002cc2: 1c5a adds r2, r3, #1
8002cc4: 687b ldr r3, [r7, #4]
8002cc6: 625a str r2, [r3, #36] @ 0x24
if ((hi2c->XferSize > 0U))
8002cc8: 687b ldr r3, [r7, #4]
8002cca: 8d1b ldrh r3, [r3, #40] @ 0x28
8002ccc: 2b00 cmp r3, #0
8002cce: d012 beq.n 8002cf6 <I2C_ITListenCplt+0x7a>
{
hi2c->XferSize--;
8002cd0: 687b ldr r3, [r7, #4]
8002cd2: 8d1b ldrh r3, [r3, #40] @ 0x28
8002cd4: 3b01 subs r3, #1
8002cd6: b29a uxth r2, r3
8002cd8: 687b ldr r3, [r7, #4]
8002cda: 851a strh r2, [r3, #40] @ 0x28
hi2c->XferCount--;
8002cdc: 687b ldr r3, [r7, #4]
8002cde: 8d5b ldrh r3, [r3, #42] @ 0x2a
8002ce0: b29b uxth r3, r3
8002ce2: 3b01 subs r3, #1
8002ce4: b29a uxth r2, r3
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 855a strh r2, [r3, #42] @ 0x2a
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8002cea: 687b ldr r3, [r7, #4]
8002cec: 6c5b ldr r3, [r3, #68] @ 0x44
8002cee: 2204 movs r2, #4
8002cf0: 431a orrs r2, r3
8002cf2: 687b ldr r3, [r7, #4]
8002cf4: 645a str r2, [r3, #68] @ 0x44
}
}
/* Disable all Interrupts*/
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
8002cf6: 4a0c ldr r2, [pc, #48] @ (8002d28 <I2C_ITListenCplt+0xac>)
8002cf8: 687b ldr r3, [r7, #4]
8002cfa: 0011 movs r1, r2
8002cfc: 0018 movs r0, r3
8002cfe: f000 fa45 bl 800318c <I2C_Disable_IRQ>
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002d02: 687b ldr r3, [r7, #4]
8002d04: 681b ldr r3, [r3, #0]
8002d06: 2210 movs r2, #16
8002d08: 61da str r2, [r3, #28]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002d0a: 687b ldr r3, [r7, #4]
8002d0c: 2240 movs r2, #64 @ 0x40
8002d0e: 2100 movs r1, #0
8002d10: 5499 strb r1, [r3, r2]
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->ListenCpltCallback(hi2c);
#else
HAL_I2C_ListenCpltCallback(hi2c);
8002d12: 687b ldr r3, [r7, #4]
8002d14: 0018 movs r0, r3
8002d16: f7fd fcef bl 80006f8 <HAL_I2C_ListenCpltCallback>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
8002d1a: 46c0 nop @ (mov r8, r8)
8002d1c: 46bd mov sp, r7
8002d1e: b002 add sp, #8
8002d20: bd80 pop {r7, pc}
8002d22: 46c0 nop @ (mov r8, r8)
8002d24: ffff0000 .word 0xffff0000
8002d28: 00008003 .word 0x00008003
08002d2c <I2C_ITError>:
* @param hi2c I2C handle.
* @param ErrorCode Error code to handle.
* @retval None
*/
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
8002d2c: b580 push {r7, lr}
8002d2e: b084 sub sp, #16
8002d30: af00 add r7, sp, #0
8002d32: 6078 str r0, [r7, #4]
8002d34: 6039 str r1, [r7, #0]
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
8002d36: 200f movs r0, #15
8002d38: 183b adds r3, r7, r0
8002d3a: 687a ldr r2, [r7, #4]
8002d3c: 2141 movs r1, #65 @ 0x41
8002d3e: 5c52 ldrb r2, [r2, r1]
8002d40: 701a strb r2, [r3, #0]
uint32_t tmppreviousstate;
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
8002d42: 687b ldr r3, [r7, #4]
8002d44: 2242 movs r2, #66 @ 0x42
8002d46: 2100 movs r1, #0
8002d48: 5499 strb r1, [r3, r2]
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
8002d4a: 687b ldr r3, [r7, #4]
8002d4c: 4a72 ldr r2, [pc, #456] @ (8002f18 <I2C_ITError+0x1ec>)
8002d4e: 62da str r2, [r3, #44] @ 0x2c
hi2c->XferCount = 0U;
8002d50: 687b ldr r3, [r7, #4]
8002d52: 2200 movs r2, #0
8002d54: 855a strh r2, [r3, #42] @ 0x2a
/* Set new error code */
hi2c->ErrorCode |= ErrorCode;
8002d56: 687b ldr r3, [r7, #4]
8002d58: 6c5a ldr r2, [r3, #68] @ 0x44
8002d5a: 683b ldr r3, [r7, #0]
8002d5c: 431a orrs r2, r3
8002d5e: 687b ldr r3, [r7, #4]
8002d60: 645a str r2, [r3, #68] @ 0x44
/* Disable Interrupts */
if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
8002d62: 183b adds r3, r7, r0
8002d64: 781b ldrb r3, [r3, #0]
8002d66: 2b28 cmp r3, #40 @ 0x28
8002d68: d007 beq.n 8002d7a <I2C_ITError+0x4e>
8002d6a: 183b adds r3, r7, r0
8002d6c: 781b ldrb r3, [r3, #0]
8002d6e: 2b29 cmp r3, #41 @ 0x29
8002d70: d003 beq.n 8002d7a <I2C_ITError+0x4e>
(tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
8002d72: 183b adds r3, r7, r0
8002d74: 781b ldrb r3, [r3, #0]
8002d76: 2b2a cmp r3, #42 @ 0x2a
8002d78: d10c bne.n 8002d94 <I2C_ITError+0x68>
(tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
8002d7a: 687b ldr r3, [r7, #4]
8002d7c: 2103 movs r1, #3
8002d7e: 0018 movs r0, r3
8002d80: f000 fa04 bl 800318c <I2C_Disable_IRQ>
/* keep HAL_I2C_STATE_LISTEN if set */
hi2c->State = HAL_I2C_STATE_LISTEN;
8002d84: 687b ldr r3, [r7, #4]
8002d86: 2241 movs r2, #65 @ 0x41
8002d88: 2128 movs r1, #40 @ 0x28
8002d8a: 5499 strb r1, [r3, r2]
hi2c->XferISR = I2C_Slave_ISR_IT;
8002d8c: 687b ldr r3, [r7, #4]
8002d8e: 4a63 ldr r2, [pc, #396] @ (8002f1c <I2C_ITError+0x1f0>)
8002d90: 635a str r2, [r3, #52] @ 0x34
8002d92: e032 b.n 8002dfa <I2C_ITError+0xce>
}
else
{
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
8002d94: 4a62 ldr r2, [pc, #392] @ (8002f20 <I2C_ITError+0x1f4>)
8002d96: 687b ldr r3, [r7, #4]
8002d98: 0011 movs r1, r2
8002d9a: 0018 movs r0, r3
8002d9c: f000 f9f6 bl 800318c <I2C_Disable_IRQ>
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
8002da0: 687b ldr r3, [r7, #4]
8002da2: 0018 movs r0, r3
8002da4: f000 f8ed bl 8002f82 <I2C_Flush_TXDR>
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
8002da8: 687b ldr r3, [r7, #4]
8002daa: 2241 movs r2, #65 @ 0x41
8002dac: 5c9b ldrb r3, [r3, r2]
8002dae: b2db uxtb r3, r3
8002db0: 2b60 cmp r3, #96 @ 0x60
8002db2: d01f beq.n 8002df4 <I2C_ITError+0xc8>
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
8002db4: 687b ldr r3, [r7, #4]
8002db6: 2241 movs r2, #65 @ 0x41
8002db8: 2120 movs r1, #32
8002dba: 5499 strb r1, [r3, r2]
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
8002dbc: 687b ldr r3, [r7, #4]
8002dbe: 681b ldr r3, [r3, #0]
8002dc0: 699b ldr r3, [r3, #24]
8002dc2: 2220 movs r2, #32
8002dc4: 4013 ands r3, r2
8002dc6: 2b20 cmp r3, #32
8002dc8: d114 bne.n 8002df4 <I2C_ITError+0xc8>
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
8002dca: 687b ldr r3, [r7, #4]
8002dcc: 681b ldr r3, [r3, #0]
8002dce: 699b ldr r3, [r3, #24]
8002dd0: 2210 movs r2, #16
8002dd2: 4013 ands r3, r2
8002dd4: 2b10 cmp r3, #16
8002dd6: d109 bne.n 8002dec <I2C_ITError+0xc0>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
8002dd8: 687b ldr r3, [r7, #4]
8002dda: 681b ldr r3, [r3, #0]
8002ddc: 2210 movs r2, #16
8002dde: 61da str r2, [r3, #28]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
8002de0: 687b ldr r3, [r7, #4]
8002de2: 6c5b ldr r3, [r3, #68] @ 0x44
8002de4: 2204 movs r2, #4
8002de6: 431a orrs r2, r3
8002de8: 687b ldr r3, [r7, #4]
8002dea: 645a str r2, [r3, #68] @ 0x44
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
8002dec: 687b ldr r3, [r7, #4]
8002dee: 681b ldr r3, [r3, #0]
8002df0: 2220 movs r2, #32
8002df2: 61da str r2, [r3, #28]
}
}
hi2c->XferISR = NULL;
8002df4: 687b ldr r3, [r7, #4]
8002df6: 2200 movs r2, #0
8002df8: 635a str r2, [r3, #52] @ 0x34
}
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
8002dfa: 687b ldr r3, [r7, #4]
8002dfc: 6b1b ldr r3, [r3, #48] @ 0x30
8002dfe: 60bb str r3, [r7, #8]
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
8002e00: 687b ldr r3, [r7, #4]
8002e02: 6b9b ldr r3, [r3, #56] @ 0x38
8002e04: 2b00 cmp r3, #0
8002e06: d03b beq.n 8002e80 <I2C_ITError+0x154>
8002e08: 68bb ldr r3, [r7, #8]
8002e0a: 2b11 cmp r3, #17
8002e0c: d002 beq.n 8002e14 <I2C_ITError+0xe8>
8002e0e: 68bb ldr r3, [r7, #8]
8002e10: 2b21 cmp r3, #33 @ 0x21
8002e12: d135 bne.n 8002e80 <I2C_ITError+0x154>
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
8002e14: 687b ldr r3, [r7, #4]
8002e16: 681b ldr r3, [r3, #0]
8002e18: 681a ldr r2, [r3, #0]
8002e1a: 2380 movs r3, #128 @ 0x80
8002e1c: 01db lsls r3, r3, #7
8002e1e: 401a ands r2, r3
8002e20: 2380 movs r3, #128 @ 0x80
8002e22: 01db lsls r3, r3, #7
8002e24: 429a cmp r2, r3
8002e26: d107 bne.n 8002e38 <I2C_ITError+0x10c>
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
8002e28: 687b ldr r3, [r7, #4]
8002e2a: 681b ldr r3, [r3, #0]
8002e2c: 681a ldr r2, [r3, #0]
8002e2e: 687b ldr r3, [r7, #4]
8002e30: 681b ldr r3, [r3, #0]
8002e32: 493c ldr r1, [pc, #240] @ (8002f24 <I2C_ITError+0x1f8>)
8002e34: 400a ands r2, r1
8002e36: 601a str r2, [r3, #0]
}
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8002e38: 687b ldr r3, [r7, #4]
8002e3a: 6b9b ldr r3, [r3, #56] @ 0x38
8002e3c: 0018 movs r0, r3
8002e3e: f7fe fad5 bl 80013ec <HAL_DMA_GetState>
8002e42: 0003 movs r3, r0
8002e44: 2b01 cmp r3, #1
8002e46: d016 beq.n 8002e76 <I2C_ITError+0x14a>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
8002e48: 687b ldr r3, [r7, #4]
8002e4a: 6b9b ldr r3, [r3, #56] @ 0x38
8002e4c: 4a36 ldr r2, [pc, #216] @ (8002f28 <I2C_ITError+0x1fc>)
8002e4e: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002e50: 687b ldr r3, [r7, #4]
8002e52: 2240 movs r2, #64 @ 0x40
8002e54: 2100 movs r1, #0
8002e56: 5499 strb r1, [r3, r2]
/* Abort DMA TX */
if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
8002e58: 687b ldr r3, [r7, #4]
8002e5a: 6b9b ldr r3, [r3, #56] @ 0x38
8002e5c: 0018 movs r0, r3
8002e5e: f7fe fa5b bl 8001318 <HAL_DMA_Abort_IT>
8002e62: 1e03 subs r3, r0, #0
8002e64: d051 beq.n 8002f0a <I2C_ITError+0x1de>
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
8002e66: 687b ldr r3, [r7, #4]
8002e68: 6b9b ldr r3, [r3, #56] @ 0x38
8002e6a: 6b9a ldr r2, [r3, #56] @ 0x38
8002e6c: 687b ldr r3, [r7, #4]
8002e6e: 6b9b ldr r3, [r3, #56] @ 0x38
8002e70: 0018 movs r0, r3
8002e72: 4790 blx r2
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8002e74: e049 b.n 8002f0a <I2C_ITError+0x1de>
}
}
else
{
I2C_TreatErrorCallback(hi2c);
8002e76: 687b ldr r3, [r7, #4]
8002e78: 0018 movs r0, r3
8002e7a: f000 f859 bl 8002f30 <I2C_TreatErrorCallback>
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8002e7e: e044 b.n 8002f0a <I2C_ITError+0x1de>
}
}
/* Abort DMA RX transfer if any */
else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
8002e80: 687b ldr r3, [r7, #4]
8002e82: 6bdb ldr r3, [r3, #60] @ 0x3c
8002e84: 2b00 cmp r3, #0
8002e86: d03b beq.n 8002f00 <I2C_ITError+0x1d4>
8002e88: 68bb ldr r3, [r7, #8]
8002e8a: 2b12 cmp r3, #18
8002e8c: d002 beq.n 8002e94 <I2C_ITError+0x168>
8002e8e: 68bb ldr r3, [r7, #8]
8002e90: 2b22 cmp r3, #34 @ 0x22
8002e92: d135 bne.n 8002f00 <I2C_ITError+0x1d4>
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
8002e94: 687b ldr r3, [r7, #4]
8002e96: 681b ldr r3, [r3, #0]
8002e98: 681a ldr r2, [r3, #0]
8002e9a: 2380 movs r3, #128 @ 0x80
8002e9c: 021b lsls r3, r3, #8
8002e9e: 401a ands r2, r3
8002ea0: 2380 movs r3, #128 @ 0x80
8002ea2: 021b lsls r3, r3, #8
8002ea4: 429a cmp r2, r3
8002ea6: d107 bne.n 8002eb8 <I2C_ITError+0x18c>
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
8002ea8: 687b ldr r3, [r7, #4]
8002eaa: 681b ldr r3, [r3, #0]
8002eac: 681a ldr r2, [r3, #0]
8002eae: 687b ldr r3, [r7, #4]
8002eb0: 681b ldr r3, [r3, #0]
8002eb2: 491e ldr r1, [pc, #120] @ (8002f2c <I2C_ITError+0x200>)
8002eb4: 400a ands r2, r1
8002eb6: 601a str r2, [r3, #0]
}
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8002eb8: 687b ldr r3, [r7, #4]
8002eba: 6bdb ldr r3, [r3, #60] @ 0x3c
8002ebc: 0018 movs r0, r3
8002ebe: f7fe fa95 bl 80013ec <HAL_DMA_GetState>
8002ec2: 0003 movs r3, r0
8002ec4: 2b01 cmp r3, #1
8002ec6: d016 beq.n 8002ef6 <I2C_ITError+0x1ca>
{
/* Set the I2C DMA Abort callback :
will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
8002ec8: 687b ldr r3, [r7, #4]
8002eca: 6bdb ldr r3, [r3, #60] @ 0x3c
8002ecc: 4a16 ldr r2, [pc, #88] @ (8002f28 <I2C_ITError+0x1fc>)
8002ece: 639a str r2, [r3, #56] @ 0x38
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002ed0: 687b ldr r3, [r7, #4]
8002ed2: 2240 movs r2, #64 @ 0x40
8002ed4: 2100 movs r1, #0
8002ed6: 5499 strb r1, [r3, r2]
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
8002ed8: 687b ldr r3, [r7, #4]
8002eda: 6bdb ldr r3, [r3, #60] @ 0x3c
8002edc: 0018 movs r0, r3
8002ede: f7fe fa1b bl 8001318 <HAL_DMA_Abort_IT>
8002ee2: 1e03 subs r3, r0, #0
8002ee4: d013 beq.n 8002f0e <I2C_ITError+0x1e2>
{
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
8002ee6: 687b ldr r3, [r7, #4]
8002ee8: 6bdb ldr r3, [r3, #60] @ 0x3c
8002eea: 6b9a ldr r2, [r3, #56] @ 0x38
8002eec: 687b ldr r3, [r7, #4]
8002eee: 6bdb ldr r3, [r3, #60] @ 0x3c
8002ef0: 0018 movs r0, r3
8002ef2: 4790 blx r2
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8002ef4: e00b b.n 8002f0e <I2C_ITError+0x1e2>
}
}
else
{
I2C_TreatErrorCallback(hi2c);
8002ef6: 687b ldr r3, [r7, #4]
8002ef8: 0018 movs r0, r3
8002efa: f000 f819 bl 8002f30 <I2C_TreatErrorCallback>
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8002efe: e006 b.n 8002f0e <I2C_ITError+0x1e2>
}
}
else
{
I2C_TreatErrorCallback(hi2c);
8002f00: 687b ldr r3, [r7, #4]
8002f02: 0018 movs r0, r3
8002f04: f000 f814 bl 8002f30 <I2C_TreatErrorCallback>
}
}
8002f08: e002 b.n 8002f10 <I2C_ITError+0x1e4>
if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
8002f0a: 46c0 nop @ (mov r8, r8)
8002f0c: e000 b.n 8002f10 <I2C_ITError+0x1e4>
if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
8002f0e: 46c0 nop @ (mov r8, r8)
}
8002f10: 46c0 nop @ (mov r8, r8)
8002f12: 46bd mov sp, r7
8002f14: b004 add sp, #16
8002f16: bd80 pop {r7, pc}
8002f18: ffff0000 .word 0xffff0000
8002f1c: 08001d1d .word 0x08001d1d
8002f20: 00008003 .word 0x00008003
8002f24: ffffbfff .word 0xffffbfff
8002f28: 08002fc7 .word 0x08002fc7
8002f2c: ffff7fff .word 0xffff7fff
08002f30 <I2C_TreatErrorCallback>:
* @brief I2C Error callback treatment.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
{
8002f30: b580 push {r7, lr}
8002f32: b082 sub sp, #8
8002f34: af00 add r7, sp, #0
8002f36: 6078 str r0, [r7, #4]
if (hi2c->State == HAL_I2C_STATE_ABORT)
8002f38: 687b ldr r3, [r7, #4]
8002f3a: 2241 movs r2, #65 @ 0x41
8002f3c: 5c9b ldrb r3, [r3, r2]
8002f3e: b2db uxtb r3, r3
8002f40: 2b60 cmp r3, #96 @ 0x60
8002f42: d10f bne.n 8002f64 <I2C_TreatErrorCallback+0x34>
{
hi2c->State = HAL_I2C_STATE_READY;
8002f44: 687b ldr r3, [r7, #4]
8002f46: 2241 movs r2, #65 @ 0x41
8002f48: 2120 movs r1, #32
8002f4a: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
8002f4c: 687b ldr r3, [r7, #4]
8002f4e: 2200 movs r2, #0
8002f50: 631a str r2, [r3, #48] @ 0x30
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
8002f52: 687b ldr r3, [r7, #4]
8002f54: 2240 movs r2, #64 @ 0x40
8002f56: 2100 movs r1, #0
8002f58: 5499 strb r1, [r3, r2]
/* Call the corresponding callback to inform upper layer of End of Transfer */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
hi2c->AbortCpltCallback(hi2c);
#else
HAL_I2C_AbortCpltCallback(hi2c);
8002f5a: 687b ldr r3, [r7, #4]
8002f5c: 0018 movs r0, r3
8002f5e: f7fe fed4 bl 8001d0a <HAL_I2C_AbortCpltCallback>
hi2c->ErrorCallback(hi2c);
#else
HAL_I2C_ErrorCallback(hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
8002f62: e00a b.n 8002f7a <I2C_TreatErrorCallback+0x4a>
hi2c->PreviousState = I2C_STATE_NONE;
8002f64: 687b ldr r3, [r7, #4]
8002f66: 2200 movs r2, #0
8002f68: 631a str r2, [r3, #48] @ 0x30
__HAL_UNLOCK(hi2c);
8002f6a: 687b ldr r3, [r7, #4]
8002f6c: 2240 movs r2, #64 @ 0x40
8002f6e: 2100 movs r1, #0
8002f70: 5499 strb r1, [r3, r2]
HAL_I2C_ErrorCallback(hi2c);
8002f72: 687b ldr r3, [r7, #4]
8002f74: 0018 movs r0, r3
8002f76: f7fe fec0 bl 8001cfa <HAL_I2C_ErrorCallback>
}
8002f7a: 46c0 nop @ (mov r8, r8)
8002f7c: 46bd mov sp, r7
8002f7e: b002 add sp, #8
8002f80: bd80 pop {r7, pc}
08002f82 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
8002f82: b580 push {r7, lr}
8002f84: b082 sub sp, #8
8002f86: af00 add r7, sp, #0
8002f88: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
8002f8a: 687b ldr r3, [r7, #4]
8002f8c: 681b ldr r3, [r3, #0]
8002f8e: 699b ldr r3, [r3, #24]
8002f90: 2202 movs r2, #2
8002f92: 4013 ands r3, r2
8002f94: 2b02 cmp r3, #2
8002f96: d103 bne.n 8002fa0 <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
8002f98: 687b ldr r3, [r7, #4]
8002f9a: 681b ldr r3, [r3, #0]
8002f9c: 2200 movs r2, #0
8002f9e: 629a str r2, [r3, #40] @ 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
8002fa0: 687b ldr r3, [r7, #4]
8002fa2: 681b ldr r3, [r3, #0]
8002fa4: 699b ldr r3, [r3, #24]
8002fa6: 2201 movs r2, #1
8002fa8: 4013 ands r3, r2
8002faa: 2b01 cmp r3, #1
8002fac: d007 beq.n 8002fbe <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
8002fae: 687b ldr r3, [r7, #4]
8002fb0: 681b ldr r3, [r3, #0]
8002fb2: 699a ldr r2, [r3, #24]
8002fb4: 687b ldr r3, [r7, #4]
8002fb6: 681b ldr r3, [r3, #0]
8002fb8: 2101 movs r1, #1
8002fba: 430a orrs r2, r1
8002fbc: 619a str r2, [r3, #24]
}
}
8002fbe: 46c0 nop @ (mov r8, r8)
8002fc0: 46bd mov sp, r7
8002fc2: b002 add sp, #8
8002fc4: bd80 pop {r7, pc}
08002fc6 <I2C_DMAAbort>:
* (To be called at end of DMA Abort procedure).
* @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
8002fc6: b580 push {r7, lr}
8002fc8: b084 sub sp, #16
8002fca: af00 add r7, sp, #0
8002fcc: 6078 str r0, [r7, #4]
/* Derogation MISRAC2012-Rule-11.5 */
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 6a9b ldr r3, [r3, #40] @ 0x28
8002fd2: 60fb str r3, [r7, #12]
/* Reset AbortCpltCallback */
if (hi2c->hdmatx != NULL)
8002fd4: 68fb ldr r3, [r7, #12]
8002fd6: 6b9b ldr r3, [r3, #56] @ 0x38
8002fd8: 2b00 cmp r3, #0
8002fda: d003 beq.n 8002fe4 <I2C_DMAAbort+0x1e>
{
hi2c->hdmatx->XferAbortCallback = NULL;
8002fdc: 68fb ldr r3, [r7, #12]
8002fde: 6b9b ldr r3, [r3, #56] @ 0x38
8002fe0: 2200 movs r2, #0
8002fe2: 639a str r2, [r3, #56] @ 0x38
}
if (hi2c->hdmarx != NULL)
8002fe4: 68fb ldr r3, [r7, #12]
8002fe6: 6bdb ldr r3, [r3, #60] @ 0x3c
8002fe8: 2b00 cmp r3, #0
8002fea: d003 beq.n 8002ff4 <I2C_DMAAbort+0x2e>
{
hi2c->hdmarx->XferAbortCallback = NULL;
8002fec: 68fb ldr r3, [r7, #12]
8002fee: 6bdb ldr r3, [r3, #60] @ 0x3c
8002ff0: 2200 movs r2, #0
8002ff2: 639a str r2, [r3, #56] @ 0x38
}
I2C_TreatErrorCallback(hi2c);
8002ff4: 68fb ldr r3, [r7, #12]
8002ff6: 0018 movs r0, r3
8002ff8: f7ff ff9a bl 8002f30 <I2C_TreatErrorCallback>
}
8002ffc: 46c0 nop @ (mov r8, r8)
8002ffe: 46bd mov sp, r7
8003000: b004 add sp, #16
8003002: bd80 pop {r7, pc}
08003004 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
8003004: b590 push {r4, r7, lr}
8003006: b087 sub sp, #28
8003008: af00 add r7, sp, #0
800300a: 60f8 str r0, [r7, #12]
800300c: 0008 movs r0, r1
800300e: 0011 movs r1, r2
8003010: 607b str r3, [r7, #4]
8003012: 240a movs r4, #10
8003014: 193b adds r3, r7, r4
8003016: 1c02 adds r2, r0, #0
8003018: 801a strh r2, [r3, #0]
800301a: 2009 movs r0, #9
800301c: 183b adds r3, r7, r0
800301e: 1c0a adds r2, r1, #0
8003020: 701a strb r2, [r3, #0]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8003022: 193b adds r3, r7, r4
8003024: 881b ldrh r3, [r3, #0]
8003026: 059b lsls r3, r3, #22
8003028: 0d9a lsrs r2, r3, #22
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
800302a: 183b adds r3, r7, r0
800302c: 781b ldrb r3, [r3, #0]
800302e: 0419 lsls r1, r3, #16
8003030: 23ff movs r3, #255 @ 0xff
8003032: 041b lsls r3, r3, #16
8003034: 400b ands r3, r1
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
8003036: 431a orrs r2, r3
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
8003038: 687b ldr r3, [r7, #4]
800303a: 431a orrs r2, r3
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
800303c: 6abb ldr r3, [r7, #40] @ 0x28
800303e: 4313 orrs r3, r2
8003040: 005b lsls r3, r3, #1
8003042: 085b lsrs r3, r3, #1
8003044: 617b str r3, [r7, #20]
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \
8003046: 68fb ldr r3, [r7, #12]
8003048: 681b ldr r3, [r3, #0]
800304a: 685b ldr r3, [r3, #4]
800304c: 6aba ldr r2, [r7, #40] @ 0x28
800304e: 0d51 lsrs r1, r2, #21
8003050: 2280 movs r2, #128 @ 0x80
8003052: 00d2 lsls r2, r2, #3
8003054: 400a ands r2, r1
8003056: 4907 ldr r1, [pc, #28] @ (8003074 <I2C_TransferConfig+0x70>)
8003058: 430a orrs r2, r1
800305a: 43d2 mvns r2, r2
800305c: 401a ands r2, r3
800305e: 0011 movs r1, r2
8003060: 68fb ldr r3, [r7, #12]
8003062: 681b ldr r3, [r3, #0]
8003064: 697a ldr r2, [r7, #20]
8003066: 430a orrs r2, r1
8003068: 605a str r2, [r3, #4]
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
800306a: 46c0 nop @ (mov r8, r8)
800306c: 46bd mov sp, r7
800306e: b007 add sp, #28
8003070: bd90 pop {r4, r7, pc}
8003072: 46c0 nop @ (mov r8, r8)
8003074: 03ff63ff .word 0x03ff63ff
08003078 <I2C_Enable_IRQ>:
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
8003078: b580 push {r7, lr}
800307a: b084 sub sp, #16
800307c: af00 add r7, sp, #0
800307e: 6078 str r0, [r7, #4]
8003080: 000a movs r2, r1
8003082: 1cbb adds r3, r7, #2
8003084: 801a strh r2, [r3, #0]
uint32_t tmpisr = 0U;
8003086: 2300 movs r3, #0
8003088: 60fb str r3, [r7, #12]
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
800308a: 687b ldr r3, [r7, #4]
800308c: 6b5a ldr r2, [r3, #52] @ 0x34
800308e: 4b3c ldr r3, [pc, #240] @ (8003180 <I2C_Enable_IRQ+0x108>)
8003090: 429a cmp r2, r3
8003092: d035 beq.n 8003100 <I2C_Enable_IRQ+0x88>
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
8003094: 687b ldr r3, [r7, #4]
8003096: 6b5a ldr r2, [r3, #52] @ 0x34
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
8003098: 4b3a ldr r3, [pc, #232] @ (8003184 <I2C_Enable_IRQ+0x10c>)
800309a: 429a cmp r2, r3
800309c: d030 beq.n 8003100 <I2C_Enable_IRQ+0x88>
(hi2c->XferISR != I2C_Mem_ISR_DMA))
800309e: 687b ldr r3, [r7, #4]
80030a0: 6b5a ldr r2, [r3, #52] @ 0x34
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
80030a2: 4b39 ldr r3, [pc, #228] @ (8003188 <I2C_Enable_IRQ+0x110>)
80030a4: 429a cmp r2, r3
80030a6: d02b beq.n 8003100 <I2C_Enable_IRQ+0x88>
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
80030a8: 1cbb adds r3, r7, #2
80030aa: 2200 movs r2, #0
80030ac: 5e9b ldrsh r3, [r3, r2]
80030ae: 2b00 cmp r3, #0
80030b0: da03 bge.n 80030ba <I2C_Enable_IRQ+0x42>
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
80030b2: 68fb ldr r3, [r7, #12]
80030b4: 22b8 movs r2, #184 @ 0xb8
80030b6: 4313 orrs r3, r2
80030b8: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
80030ba: 1cbb adds r3, r7, #2
80030bc: 881b ldrh r3, [r3, #0]
80030be: 2201 movs r2, #1
80030c0: 4013 ands r3, r2
80030c2: d003 beq.n 80030cc <I2C_Enable_IRQ+0x54>
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
80030c4: 68fb ldr r3, [r7, #12]
80030c6: 22f2 movs r2, #242 @ 0xf2
80030c8: 4313 orrs r3, r2
80030ca: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
80030cc: 1cbb adds r3, r7, #2
80030ce: 881b ldrh r3, [r3, #0]
80030d0: 2202 movs r2, #2
80030d2: 4013 ands r3, r2
80030d4: d003 beq.n 80030de <I2C_Enable_IRQ+0x66>
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
80030d6: 68fb ldr r3, [r7, #12]
80030d8: 22f4 movs r2, #244 @ 0xf4
80030da: 4313 orrs r3, r2
80030dc: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
80030de: 1cbb adds r3, r7, #2
80030e0: 881b ldrh r3, [r3, #0]
80030e2: 2b10 cmp r3, #16
80030e4: d103 bne.n 80030ee <I2C_Enable_IRQ+0x76>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
80030e6: 68fb ldr r3, [r7, #12]
80030e8: 2290 movs r2, #144 @ 0x90
80030ea: 4313 orrs r3, r2
80030ec: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
80030ee: 1cbb adds r3, r7, #2
80030f0: 881b ldrh r3, [r3, #0]
80030f2: 2b20 cmp r3, #32
80030f4: d137 bne.n 8003166 <I2C_Enable_IRQ+0xee>
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
80030f6: 68fb ldr r3, [r7, #12]
80030f8: 2220 movs r2, #32
80030fa: 4313 orrs r3, r2
80030fc: 60fb str r3, [r7, #12]
if (InterruptRequest == I2C_XFER_CPLT_IT)
80030fe: e032 b.n 8003166 <I2C_Enable_IRQ+0xee>
}
}
else
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
8003100: 1cbb adds r3, r7, #2
8003102: 2200 movs r2, #0
8003104: 5e9b ldrsh r3, [r3, r2]
8003106: 2b00 cmp r3, #0
8003108: da03 bge.n 8003112 <I2C_Enable_IRQ+0x9a>
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
800310a: 68fb ldr r3, [r7, #12]
800310c: 22b8 movs r2, #184 @ 0xb8
800310e: 4313 orrs r3, r2
8003110: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
8003112: 1cbb adds r3, r7, #2
8003114: 881b ldrh r3, [r3, #0]
8003116: 2201 movs r2, #1
8003118: 4013 ands r3, r2
800311a: d003 beq.n 8003124 <I2C_Enable_IRQ+0xac>
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
800311c: 68fb ldr r3, [r7, #12]
800311e: 22f2 movs r2, #242 @ 0xf2
8003120: 4313 orrs r3, r2
8003122: 60fb str r3, [r7, #12]
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
8003124: 1cbb adds r3, r7, #2
8003126: 881b ldrh r3, [r3, #0]
8003128: 2202 movs r2, #2
800312a: 4013 ands r3, r2
800312c: d003 beq.n 8003136 <I2C_Enable_IRQ+0xbe>
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
800312e: 68fb ldr r3, [r7, #12]
8003130: 22f4 movs r2, #244 @ 0xf4
8003132: 4313 orrs r3, r2
8003134: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
8003136: 1cbb adds r3, r7, #2
8003138: 881b ldrh r3, [r3, #0]
800313a: 2b10 cmp r3, #16
800313c: d103 bne.n 8003146 <I2C_Enable_IRQ+0xce>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
800313e: 68fb ldr r3, [r7, #12]
8003140: 2290 movs r2, #144 @ 0x90
8003142: 4313 orrs r3, r2
8003144: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
8003146: 1cbb adds r3, r7, #2
8003148: 881b ldrh r3, [r3, #0]
800314a: 2b20 cmp r3, #32
800314c: d103 bne.n 8003156 <I2C_Enable_IRQ+0xde>
{
/* Enable STOP interrupts */
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
800314e: 68fb ldr r3, [r7, #12]
8003150: 2260 movs r2, #96 @ 0x60
8003152: 4313 orrs r3, r2
8003154: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
8003156: 1cbb adds r3, r7, #2
8003158: 881b ldrh r3, [r3, #0]
800315a: 2b40 cmp r3, #64 @ 0x40
800315c: d103 bne.n 8003166 <I2C_Enable_IRQ+0xee>
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
800315e: 68fb ldr r3, [r7, #12]
8003160: 2240 movs r2, #64 @ 0x40
8003162: 4313 orrs r3, r2
8003164: 60fb str r3, [r7, #12]
}
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
8003166: 687b ldr r3, [r7, #4]
8003168: 681b ldr r3, [r3, #0]
800316a: 6819 ldr r1, [r3, #0]
800316c: 687b ldr r3, [r7, #4]
800316e: 681b ldr r3, [r3, #0]
8003170: 68fa ldr r2, [r7, #12]
8003172: 430a orrs r2, r1
8003174: 601a str r2, [r3, #0]
}
8003176: 46c0 nop @ (mov r8, r8)
8003178: 46bd mov sp, r7
800317a: b004 add sp, #16
800317c: bd80 pop {r7, pc}
800317e: 46c0 nop @ (mov r8, r8)
8003180: 08001f1d .word 0x08001f1d
8003184: 0800236d .word 0x0800236d
8003188: 08002115 .word 0x08002115
0800318c <I2C_Disable_IRQ>:
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
* @retval None
*/
static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
800318c: b580 push {r7, lr}
800318e: b084 sub sp, #16
8003190: af00 add r7, sp, #0
8003192: 6078 str r0, [r7, #4]
8003194: 000a movs r2, r1
8003196: 1cbb adds r3, r7, #2
8003198: 801a strh r2, [r3, #0]
uint32_t tmpisr = 0U;
800319a: 2300 movs r3, #0
800319c: 60fb str r3, [r7, #12]
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
800319e: 1cbb adds r3, r7, #2
80031a0: 881b ldrh r3, [r3, #0]
80031a2: 2201 movs r2, #1
80031a4: 4013 ands r3, r2
80031a6: d010 beq.n 80031ca <I2C_Disable_IRQ+0x3e>
{
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
80031a8: 68fb ldr r3, [r7, #12]
80031aa: 2242 movs r2, #66 @ 0x42
80031ac: 4313 orrs r3, r2
80031ae: 60fb str r3, [r7, #12]
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
80031b0: 687b ldr r3, [r7, #4]
80031b2: 2241 movs r2, #65 @ 0x41
80031b4: 5c9b ldrb r3, [r3, r2]
80031b6: b2db uxtb r3, r3
80031b8: 001a movs r2, r3
80031ba: 2328 movs r3, #40 @ 0x28
80031bc: 4013 ands r3, r2
80031be: 2b28 cmp r3, #40 @ 0x28
80031c0: d003 beq.n 80031ca <I2C_Disable_IRQ+0x3e>
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
80031c2: 68fb ldr r3, [r7, #12]
80031c4: 22b0 movs r2, #176 @ 0xb0
80031c6: 4313 orrs r3, r2
80031c8: 60fb str r3, [r7, #12]
}
}
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
80031ca: 1cbb adds r3, r7, #2
80031cc: 881b ldrh r3, [r3, #0]
80031ce: 2202 movs r2, #2
80031d0: 4013 ands r3, r2
80031d2: d010 beq.n 80031f6 <I2C_Disable_IRQ+0x6a>
{
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
80031d4: 68fb ldr r3, [r7, #12]
80031d6: 2244 movs r2, #68 @ 0x44
80031d8: 4313 orrs r3, r2
80031da: 60fb str r3, [r7, #12]
if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
80031dc: 687b ldr r3, [r7, #4]
80031de: 2241 movs r2, #65 @ 0x41
80031e0: 5c9b ldrb r3, [r3, r2]
80031e2: b2db uxtb r3, r3
80031e4: 001a movs r2, r3
80031e6: 2328 movs r3, #40 @ 0x28
80031e8: 4013 ands r3, r2
80031ea: 2b28 cmp r3, #40 @ 0x28
80031ec: d003 beq.n 80031f6 <I2C_Disable_IRQ+0x6a>
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
80031ee: 68fb ldr r3, [r7, #12]
80031f0: 22b0 movs r2, #176 @ 0xb0
80031f2: 4313 orrs r3, r2
80031f4: 60fb str r3, [r7, #12]
}
}
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
80031f6: 1cbb adds r3, r7, #2
80031f8: 2200 movs r2, #0
80031fa: 5e9b ldrsh r3, [r3, r2]
80031fc: 2b00 cmp r3, #0
80031fe: da03 bge.n 8003208 <I2C_Disable_IRQ+0x7c>
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
8003200: 68fb ldr r3, [r7, #12]
8003202: 22b8 movs r2, #184 @ 0xb8
8003204: 4313 orrs r3, r2
8003206: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_ERROR_IT)
8003208: 1cbb adds r3, r7, #2
800320a: 881b ldrh r3, [r3, #0]
800320c: 2b10 cmp r3, #16
800320e: d103 bne.n 8003218 <I2C_Disable_IRQ+0x8c>
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
8003210: 68fb ldr r3, [r7, #12]
8003212: 2290 movs r2, #144 @ 0x90
8003214: 4313 orrs r3, r2
8003216: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_CPLT_IT)
8003218: 1cbb adds r3, r7, #2
800321a: 881b ldrh r3, [r3, #0]
800321c: 2b20 cmp r3, #32
800321e: d103 bne.n 8003228 <I2C_Disable_IRQ+0x9c>
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
8003220: 68fb ldr r3, [r7, #12]
8003222: 2220 movs r2, #32
8003224: 4313 orrs r3, r2
8003226: 60fb str r3, [r7, #12]
}
if (InterruptRequest == I2C_XFER_RELOAD_IT)
8003228: 1cbb adds r3, r7, #2
800322a: 881b ldrh r3, [r3, #0]
800322c: 2b40 cmp r3, #64 @ 0x40
800322e: d103 bne.n 8003238 <I2C_Disable_IRQ+0xac>
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
8003230: 68fb ldr r3, [r7, #12]
8003232: 2240 movs r2, #64 @ 0x40
8003234: 4313 orrs r3, r2
8003236: 60fb str r3, [r7, #12]
}
/* Disable interrupts only at the end */
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
8003238: 687b ldr r3, [r7, #4]
800323a: 681b ldr r3, [r3, #0]
800323c: 681a ldr r2, [r3, #0]
800323e: 68fb ldr r3, [r7, #12]
8003240: 43d9 mvns r1, r3
8003242: 687b ldr r3, [r7, #4]
8003244: 681b ldr r3, [r3, #0]
8003246: 400a ands r2, r1
8003248: 601a str r2, [r3, #0]
}
800324a: 46c0 nop @ (mov r8, r8)
800324c: 46bd mov sp, r7
800324e: b004 add sp, #16
8003250: bd80 pop {r7, pc}
...
08003254 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8003254: b580 push {r7, lr}
8003256: b082 sub sp, #8
8003258: af00 add r7, sp, #0
800325a: 6078 str r0, [r7, #4]
800325c: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
800325e: 687b ldr r3, [r7, #4]
8003260: 2241 movs r2, #65 @ 0x41
8003262: 5c9b ldrb r3, [r3, r2]
8003264: b2db uxtb r3, r3
8003266: 2b20 cmp r3, #32
8003268: d138 bne.n 80032dc <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
800326a: 687b ldr r3, [r7, #4]
800326c: 2240 movs r2, #64 @ 0x40
800326e: 5c9b ldrb r3, [r3, r2]
8003270: 2b01 cmp r3, #1
8003272: d101 bne.n 8003278 <HAL_I2CEx_ConfigAnalogFilter+0x24>
8003274: 2302 movs r3, #2
8003276: e032 b.n 80032de <HAL_I2CEx_ConfigAnalogFilter+0x8a>
8003278: 687b ldr r3, [r7, #4]
800327a: 2240 movs r2, #64 @ 0x40
800327c: 2101 movs r1, #1
800327e: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
8003280: 687b ldr r3, [r7, #4]
8003282: 2241 movs r2, #65 @ 0x41
8003284: 2124 movs r1, #36 @ 0x24
8003286: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003288: 687b ldr r3, [r7, #4]
800328a: 681b ldr r3, [r3, #0]
800328c: 681a ldr r2, [r3, #0]
800328e: 687b ldr r3, [r7, #4]
8003290: 681b ldr r3, [r3, #0]
8003292: 2101 movs r1, #1
8003294: 438a bics r2, r1
8003296: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8003298: 687b ldr r3, [r7, #4]
800329a: 681b ldr r3, [r3, #0]
800329c: 681a ldr r2, [r3, #0]
800329e: 687b ldr r3, [r7, #4]
80032a0: 681b ldr r3, [r3, #0]
80032a2: 4911 ldr r1, [pc, #68] @ (80032e8 <HAL_I2CEx_ConfigAnalogFilter+0x94>)
80032a4: 400a ands r2, r1
80032a6: 601a str r2, [r3, #0]
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
80032a8: 687b ldr r3, [r7, #4]
80032aa: 681b ldr r3, [r3, #0]
80032ac: 6819 ldr r1, [r3, #0]
80032ae: 687b ldr r3, [r7, #4]
80032b0: 681b ldr r3, [r3, #0]
80032b2: 683a ldr r2, [r7, #0]
80032b4: 430a orrs r2, r1
80032b6: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
80032b8: 687b ldr r3, [r7, #4]
80032ba: 681b ldr r3, [r3, #0]
80032bc: 681a ldr r2, [r3, #0]
80032be: 687b ldr r3, [r7, #4]
80032c0: 681b ldr r3, [r3, #0]
80032c2: 2101 movs r1, #1
80032c4: 430a orrs r2, r1
80032c6: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
80032c8: 687b ldr r3, [r7, #4]
80032ca: 2241 movs r2, #65 @ 0x41
80032cc: 2120 movs r1, #32
80032ce: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
80032d0: 687b ldr r3, [r7, #4]
80032d2: 2240 movs r2, #64 @ 0x40
80032d4: 2100 movs r1, #0
80032d6: 5499 strb r1, [r3, r2]
return HAL_OK;
80032d8: 2300 movs r3, #0
80032da: e000 b.n 80032de <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
80032dc: 2302 movs r3, #2
}
}
80032de: 0018 movs r0, r3
80032e0: 46bd mov sp, r7
80032e2: b002 add sp, #8
80032e4: bd80 pop {r7, pc}
80032e6: 46c0 nop @ (mov r8, r8)
80032e8: ffffefff .word 0xffffefff
080032ec <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
80032ec: b580 push {r7, lr}
80032ee: b084 sub sp, #16
80032f0: af00 add r7, sp, #0
80032f2: 6078 str r0, [r7, #4]
80032f4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
80032f6: 687b ldr r3, [r7, #4]
80032f8: 2241 movs r2, #65 @ 0x41
80032fa: 5c9b ldrb r3, [r3, r2]
80032fc: b2db uxtb r3, r3
80032fe: 2b20 cmp r3, #32
8003300: d139 bne.n 8003376 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
8003302: 687b ldr r3, [r7, #4]
8003304: 2240 movs r2, #64 @ 0x40
8003306: 5c9b ldrb r3, [r3, r2]
8003308: 2b01 cmp r3, #1
800330a: d101 bne.n 8003310 <HAL_I2CEx_ConfigDigitalFilter+0x24>
800330c: 2302 movs r3, #2
800330e: e033 b.n 8003378 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
8003310: 687b ldr r3, [r7, #4]
8003312: 2240 movs r2, #64 @ 0x40
8003314: 2101 movs r1, #1
8003316: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
8003318: 687b ldr r3, [r7, #4]
800331a: 2241 movs r2, #65 @ 0x41
800331c: 2124 movs r1, #36 @ 0x24
800331e: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003320: 687b ldr r3, [r7, #4]
8003322: 681b ldr r3, [r3, #0]
8003324: 681a ldr r2, [r3, #0]
8003326: 687b ldr r3, [r7, #4]
8003328: 681b ldr r3, [r3, #0]
800332a: 2101 movs r1, #1
800332c: 438a bics r2, r1
800332e: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
8003330: 687b ldr r3, [r7, #4]
8003332: 681b ldr r3, [r3, #0]
8003334: 681b ldr r3, [r3, #0]
8003336: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
8003338: 68fb ldr r3, [r7, #12]
800333a: 4a11 ldr r2, [pc, #68] @ (8003380 <HAL_I2CEx_ConfigDigitalFilter+0x94>)
800333c: 4013 ands r3, r2
800333e: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
8003340: 683b ldr r3, [r7, #0]
8003342: 021b lsls r3, r3, #8
8003344: 68fa ldr r2, [r7, #12]
8003346: 4313 orrs r3, r2
8003348: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
800334a: 687b ldr r3, [r7, #4]
800334c: 681b ldr r3, [r3, #0]
800334e: 68fa ldr r2, [r7, #12]
8003350: 601a str r2, [r3, #0]
__HAL_I2C_ENABLE(hi2c);
8003352: 687b ldr r3, [r7, #4]
8003354: 681b ldr r3, [r3, #0]
8003356: 681a ldr r2, [r3, #0]
8003358: 687b ldr r3, [r7, #4]
800335a: 681b ldr r3, [r3, #0]
800335c: 2101 movs r1, #1
800335e: 430a orrs r2, r1
8003360: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003362: 687b ldr r3, [r7, #4]
8003364: 2241 movs r2, #65 @ 0x41
8003366: 2120 movs r1, #32
8003368: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
800336a: 687b ldr r3, [r7, #4]
800336c: 2240 movs r2, #64 @ 0x40
800336e: 2100 movs r1, #0
8003370: 5499 strb r1, [r3, r2]
return HAL_OK;
8003372: 2300 movs r3, #0
8003374: e000 b.n 8003378 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
8003376: 2302 movs r3, #2
}
}
8003378: 0018 movs r0, r3
800337a: 46bd mov sp, r7
800337c: b004 add sp, #16
800337e: bd80 pop {r7, pc}
8003380: fffff0ff .word 0xfffff0ff
08003384 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 6 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8003384: b580 push {r7, lr}
8003386: b084 sub sp, #16
8003388: af00 add r7, sp, #0
800338a: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
/* Modify voltage scaling range */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
800338c: 4b19 ldr r3, [pc, #100] @ (80033f4 <HAL_PWREx_ControlVoltageScaling+0x70>)
800338e: 681b ldr r3, [r3, #0]
8003390: 4a19 ldr r2, [pc, #100] @ (80033f8 <HAL_PWREx_ControlVoltageScaling+0x74>)
8003392: 4013 ands r3, r2
8003394: 0019 movs r1, r3
8003396: 4b17 ldr r3, [pc, #92] @ (80033f4 <HAL_PWREx_ControlVoltageScaling+0x70>)
8003398: 687a ldr r2, [r7, #4]
800339a: 430a orrs r2, r1
800339c: 601a str r2, [r3, #0]
/* In case of Range 1 selected, we need to ensure that main regulator reaches new value */
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
800339e: 687a ldr r2, [r7, #4]
80033a0: 2380 movs r3, #128 @ 0x80
80033a2: 009b lsls r3, r3, #2
80033a4: 429a cmp r2, r3
80033a6: d11f bne.n 80033e8 <HAL_PWREx_ControlVoltageScaling+0x64>
{
/* Set timeout value */
wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U;
80033a8: 4b14 ldr r3, [pc, #80] @ (80033fc <HAL_PWREx_ControlVoltageScaling+0x78>)
80033aa: 681a ldr r2, [r3, #0]
80033ac: 0013 movs r3, r2
80033ae: 005b lsls r3, r3, #1
80033b0: 189b adds r3, r3, r2
80033b2: 005b lsls r3, r3, #1
80033b4: 4912 ldr r1, [pc, #72] @ (8003400 <HAL_PWREx_ControlVoltageScaling+0x7c>)
80033b6: 0018 movs r0, r3
80033b8: f7fc fea2 bl 8000100 <__udivsi3>
80033bc: 0003 movs r3, r0
80033be: 3301 adds r3, #1
80033c0: 60fb str r3, [r7, #12]
/* Wait until VOSF is reset */
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80033c2: e008 b.n 80033d6 <HAL_PWREx_ControlVoltageScaling+0x52>
{
if (wait_loop_index != 0U)
80033c4: 68fb ldr r3, [r7, #12]
80033c6: 2b00 cmp r3, #0
80033c8: d003 beq.n 80033d2 <HAL_PWREx_ControlVoltageScaling+0x4e>
{
wait_loop_index--;
80033ca: 68fb ldr r3, [r7, #12]
80033cc: 3b01 subs r3, #1
80033ce: 60fb str r3, [r7, #12]
80033d0: e001 b.n 80033d6 <HAL_PWREx_ControlVoltageScaling+0x52>
}
else
{
return HAL_TIMEOUT;
80033d2: 2303 movs r3, #3
80033d4: e009 b.n 80033ea <HAL_PWREx_ControlVoltageScaling+0x66>
while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80033d6: 4b07 ldr r3, [pc, #28] @ (80033f4 <HAL_PWREx_ControlVoltageScaling+0x70>)
80033d8: 695a ldr r2, [r3, #20]
80033da: 2380 movs r3, #128 @ 0x80
80033dc: 00db lsls r3, r3, #3
80033de: 401a ands r2, r3
80033e0: 2380 movs r3, #128 @ 0x80
80033e2: 00db lsls r3, r3, #3
80033e4: 429a cmp r2, r3
80033e6: d0ed beq.n 80033c4 <HAL_PWREx_ControlVoltageScaling+0x40>
}
}
}
return HAL_OK;
80033e8: 2300 movs r3, #0
}
80033ea: 0018 movs r0, r3
80033ec: 46bd mov sp, r7
80033ee: b004 add sp, #16
80033f0: bd80 pop {r7, pc}
80033f2: 46c0 nop @ (mov r8, r8)
80033f4: 40007000 .word 0x40007000
80033f8: fffff9ff .word 0xfffff9ff
80033fc: 20000004 .word 0x20000004
8003400: 000f4240 .word 0x000f4240
08003404 <LL_RCC_GetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
8003404: b580 push {r7, lr}
8003406: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE));
8003408: 4b03 ldr r3, [pc, #12] @ (8003418 <LL_RCC_GetAPB1Prescaler+0x14>)
800340a: 689a ldr r2, [r3, #8]
800340c: 23e0 movs r3, #224 @ 0xe0
800340e: 01db lsls r3, r3, #7
8003410: 4013 ands r3, r2
}
8003412: 0018 movs r0, r3
8003414: 46bd mov sp, r7
8003416: bd80 pop {r7, pc}
8003418: 40021000 .word 0x40021000
0800341c <HAL_RCC_OscConfig>:
* supported by this function. User should request a transition to LSE Off
* first and then to LSE On or LSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800341c: b580 push {r7, lr}
800341e: b088 sub sp, #32
8003420: af00 add r7, sp, #0
8003422: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8003424: 687b ldr r3, [r7, #4]
8003426: 2b00 cmp r3, #0
8003428: d101 bne.n 800342e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800342a: 2301 movs r3, #1
800342c: e2f3 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800342e: 687b ldr r3, [r7, #4]
8003430: 681b ldr r3, [r3, #0]
8003432: 2201 movs r2, #1
8003434: 4013 ands r3, r2
8003436: d100 bne.n 800343a <HAL_RCC_OscConfig+0x1e>
8003438: e07c b.n 8003534 <HAL_RCC_OscConfig+0x118>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800343a: 4bc3 ldr r3, [pc, #780] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800343c: 689b ldr r3, [r3, #8]
800343e: 2238 movs r2, #56 @ 0x38
8003440: 4013 ands r3, r2
8003442: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8003444: 4bc0 ldr r3, [pc, #768] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003446: 68db ldr r3, [r3, #12]
8003448: 2203 movs r2, #3
800344a: 4013 ands r3, r2
800344c: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE))
800344e: 69bb ldr r3, [r7, #24]
8003450: 2b10 cmp r3, #16
8003452: d102 bne.n 800345a <HAL_RCC_OscConfig+0x3e>
8003454: 697b ldr r3, [r7, #20]
8003456: 2b03 cmp r3, #3
8003458: d002 beq.n 8003460 <HAL_RCC_OscConfig+0x44>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE))
800345a: 69bb ldr r3, [r7, #24]
800345c: 2b08 cmp r3, #8
800345e: d10b bne.n 8003478 <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003460: 4bb9 ldr r3, [pc, #740] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003462: 681a ldr r2, [r3, #0]
8003464: 2380 movs r3, #128 @ 0x80
8003466: 029b lsls r3, r3, #10
8003468: 4013 ands r3, r2
800346a: d062 beq.n 8003532 <HAL_RCC_OscConfig+0x116>
800346c: 687b ldr r3, [r7, #4]
800346e: 685b ldr r3, [r3, #4]
8003470: 2b00 cmp r3, #0
8003472: d15e bne.n 8003532 <HAL_RCC_OscConfig+0x116>
{
return HAL_ERROR;
8003474: 2301 movs r3, #1
8003476: e2ce b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003478: 687b ldr r3, [r7, #4]
800347a: 685a ldr r2, [r3, #4]
800347c: 2380 movs r3, #128 @ 0x80
800347e: 025b lsls r3, r3, #9
8003480: 429a cmp r2, r3
8003482: d107 bne.n 8003494 <HAL_RCC_OscConfig+0x78>
8003484: 4bb0 ldr r3, [pc, #704] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003486: 681a ldr r2, [r3, #0]
8003488: 4baf ldr r3, [pc, #700] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800348a: 2180 movs r1, #128 @ 0x80
800348c: 0249 lsls r1, r1, #9
800348e: 430a orrs r2, r1
8003490: 601a str r2, [r3, #0]
8003492: e020 b.n 80034d6 <HAL_RCC_OscConfig+0xba>
8003494: 687b ldr r3, [r7, #4]
8003496: 685a ldr r2, [r3, #4]
8003498: 23a0 movs r3, #160 @ 0xa0
800349a: 02db lsls r3, r3, #11
800349c: 429a cmp r2, r3
800349e: d10e bne.n 80034be <HAL_RCC_OscConfig+0xa2>
80034a0: 4ba9 ldr r3, [pc, #676] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034a2: 681a ldr r2, [r3, #0]
80034a4: 4ba8 ldr r3, [pc, #672] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034a6: 2180 movs r1, #128 @ 0x80
80034a8: 02c9 lsls r1, r1, #11
80034aa: 430a orrs r2, r1
80034ac: 601a str r2, [r3, #0]
80034ae: 4ba6 ldr r3, [pc, #664] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034b0: 681a ldr r2, [r3, #0]
80034b2: 4ba5 ldr r3, [pc, #660] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034b4: 2180 movs r1, #128 @ 0x80
80034b6: 0249 lsls r1, r1, #9
80034b8: 430a orrs r2, r1
80034ba: 601a str r2, [r3, #0]
80034bc: e00b b.n 80034d6 <HAL_RCC_OscConfig+0xba>
80034be: 4ba2 ldr r3, [pc, #648] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034c0: 681a ldr r2, [r3, #0]
80034c2: 4ba1 ldr r3, [pc, #644] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034c4: 49a1 ldr r1, [pc, #644] @ (800374c <HAL_RCC_OscConfig+0x330>)
80034c6: 400a ands r2, r1
80034c8: 601a str r2, [r3, #0]
80034ca: 4b9f ldr r3, [pc, #636] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034cc: 681a ldr r2, [r3, #0]
80034ce: 4b9e ldr r3, [pc, #632] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034d0: 499f ldr r1, [pc, #636] @ (8003750 <HAL_RCC_OscConfig+0x334>)
80034d2: 400a ands r2, r1
80034d4: 601a str r2, [r3, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80034d6: 687b ldr r3, [r7, #4]
80034d8: 685b ldr r3, [r3, #4]
80034da: 2b00 cmp r3, #0
80034dc: d014 beq.n 8003508 <HAL_RCC_OscConfig+0xec>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80034de: f7fd fe1d bl 800111c <HAL_GetTick>
80034e2: 0003 movs r3, r0
80034e4: 613b str r3, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80034e6: e008 b.n 80034fa <HAL_RCC_OscConfig+0xde>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80034e8: f7fd fe18 bl 800111c <HAL_GetTick>
80034ec: 0002 movs r2, r0
80034ee: 693b ldr r3, [r7, #16]
80034f0: 1ad3 subs r3, r2, r3
80034f2: 2b64 cmp r3, #100 @ 0x64
80034f4: d901 bls.n 80034fa <HAL_RCC_OscConfig+0xde>
{
return HAL_TIMEOUT;
80034f6: 2303 movs r3, #3
80034f8: e28d b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80034fa: 4b93 ldr r3, [pc, #588] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80034fc: 681a ldr r2, [r3, #0]
80034fe: 2380 movs r3, #128 @ 0x80
8003500: 029b lsls r3, r3, #10
8003502: 4013 ands r3, r2
8003504: d0f0 beq.n 80034e8 <HAL_RCC_OscConfig+0xcc>
8003506: e015 b.n 8003534 <HAL_RCC_OscConfig+0x118>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003508: f7fd fe08 bl 800111c <HAL_GetTick>
800350c: 0003 movs r3, r0
800350e: 613b str r3, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8003510: e008 b.n 8003524 <HAL_RCC_OscConfig+0x108>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8003512: f7fd fe03 bl 800111c <HAL_GetTick>
8003516: 0002 movs r2, r0
8003518: 693b ldr r3, [r7, #16]
800351a: 1ad3 subs r3, r2, r3
800351c: 2b64 cmp r3, #100 @ 0x64
800351e: d901 bls.n 8003524 <HAL_RCC_OscConfig+0x108>
{
return HAL_TIMEOUT;
8003520: 2303 movs r3, #3
8003522: e278 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
8003524: 4b88 ldr r3, [pc, #544] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003526: 681a ldr r2, [r3, #0]
8003528: 2380 movs r3, #128 @ 0x80
800352a: 029b lsls r3, r3, #10
800352c: 4013 ands r3, r2
800352e: d1f0 bne.n 8003512 <HAL_RCC_OscConfig+0xf6>
8003530: e000 b.n 8003534 <HAL_RCC_OscConfig+0x118>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003532: 46c0 nop @ (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003534: 687b ldr r3, [r7, #4]
8003536: 681b ldr r3, [r3, #0]
8003538: 2202 movs r2, #2
800353a: 4013 ands r3, r2
800353c: d100 bne.n 8003540 <HAL_RCC_OscConfig+0x124>
800353e: e099 b.n 8003674 <HAL_RCC_OscConfig+0x258>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
/* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003540: 4b81 ldr r3, [pc, #516] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003542: 689b ldr r3, [r3, #8]
8003544: 2238 movs r2, #56 @ 0x38
8003546: 4013 ands r3, r2
8003548: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
800354a: 4b7f ldr r3, [pc, #508] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800354c: 68db ldr r3, [r3, #12]
800354e: 2203 movs r2, #3
8003550: 4013 ands r3, r2
8003552: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI))
8003554: 69bb ldr r3, [r7, #24]
8003556: 2b10 cmp r3, #16
8003558: d102 bne.n 8003560 <HAL_RCC_OscConfig+0x144>
800355a: 697b ldr r3, [r7, #20]
800355c: 2b02 cmp r3, #2
800355e: d002 beq.n 8003566 <HAL_RCC_OscConfig+0x14a>
|| (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI))
8003560: 69bb ldr r3, [r7, #24]
8003562: 2b00 cmp r3, #0
8003564: d135 bne.n 80035d2 <HAL_RCC_OscConfig+0x1b6>
{
/* When HSI is used as system clock or as PLL input clock it can not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003566: 4b78 ldr r3, [pc, #480] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003568: 681a ldr r2, [r3, #0]
800356a: 2380 movs r3, #128 @ 0x80
800356c: 00db lsls r3, r3, #3
800356e: 4013 ands r3, r2
8003570: d005 beq.n 800357e <HAL_RCC_OscConfig+0x162>
8003572: 687b ldr r3, [r7, #4]
8003574: 68db ldr r3, [r3, #12]
8003576: 2b00 cmp r3, #0
8003578: d101 bne.n 800357e <HAL_RCC_OscConfig+0x162>
{
return HAL_ERROR;
800357a: 2301 movs r3, #1
800357c: e24b b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800357e: 4b72 ldr r3, [pc, #456] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003580: 685b ldr r3, [r3, #4]
8003582: 4a74 ldr r2, [pc, #464] @ (8003754 <HAL_RCC_OscConfig+0x338>)
8003584: 4013 ands r3, r2
8003586: 0019 movs r1, r3
8003588: 687b ldr r3, [r7, #4]
800358a: 695b ldr r3, [r3, #20]
800358c: 021a lsls r2, r3, #8
800358e: 4b6e ldr r3, [pc, #440] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003590: 430a orrs r2, r1
8003592: 605a str r2, [r3, #4]
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)
8003594: 69bb ldr r3, [r7, #24]
8003596: 2b00 cmp r3, #0
8003598: d112 bne.n 80035c0 <HAL_RCC_OscConfig+0x1a4>
{
/* Adjust the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
800359a: 4b6b ldr r3, [pc, #428] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800359c: 681b ldr r3, [r3, #0]
800359e: 4a6e ldr r2, [pc, #440] @ (8003758 <HAL_RCC_OscConfig+0x33c>)
80035a0: 4013 ands r3, r2
80035a2: 0019 movs r1, r3
80035a4: 687b ldr r3, [r7, #4]
80035a6: 691a ldr r2, [r3, #16]
80035a8: 4b67 ldr r3, [pc, #412] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035aa: 430a orrs r2, r1
80035ac: 601a str r2, [r3, #0]
/* Update the SystemCoreClock global variable with HSISYS value */
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
80035ae: 4b66 ldr r3, [pc, #408] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035b0: 681b ldr r3, [r3, #0]
80035b2: 0adb lsrs r3, r3, #11
80035b4: 2207 movs r2, #7
80035b6: 4013 ands r3, r2
80035b8: 4a68 ldr r2, [pc, #416] @ (800375c <HAL_RCC_OscConfig+0x340>)
80035ba: 40da lsrs r2, r3
80035bc: 4b68 ldr r3, [pc, #416] @ (8003760 <HAL_RCC_OscConfig+0x344>)
80035be: 601a str r2, [r3, #0]
}
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
80035c0: 4b68 ldr r3, [pc, #416] @ (8003764 <HAL_RCC_OscConfig+0x348>)
80035c2: 681b ldr r3, [r3, #0]
80035c4: 0018 movs r0, r3
80035c6: f7fd fd4d bl 8001064 <HAL_InitTick>
80035ca: 1e03 subs r3, r0, #0
80035cc: d051 beq.n 8003672 <HAL_RCC_OscConfig+0x256>
{
return HAL_ERROR;
80035ce: 2301 movs r3, #1
80035d0: e221 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80035d2: 687b ldr r3, [r7, #4]
80035d4: 68db ldr r3, [r3, #12]
80035d6: 2b00 cmp r3, #0
80035d8: d030 beq.n 800363c <HAL_RCC_OscConfig+0x220>
{
/* Configure the HSI16 division factor */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
80035da: 4b5b ldr r3, [pc, #364] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035dc: 681b ldr r3, [r3, #0]
80035de: 4a5e ldr r2, [pc, #376] @ (8003758 <HAL_RCC_OscConfig+0x33c>)
80035e0: 4013 ands r3, r2
80035e2: 0019 movs r1, r3
80035e4: 687b ldr r3, [r7, #4]
80035e6: 691a ldr r2, [r3, #16]
80035e8: 4b57 ldr r3, [pc, #348] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035ea: 430a orrs r2, r1
80035ec: 601a str r2, [r3, #0]
/* Enable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_ENABLE();
80035ee: 4b56 ldr r3, [pc, #344] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035f0: 681a ldr r2, [r3, #0]
80035f2: 4b55 ldr r3, [pc, #340] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80035f4: 2180 movs r1, #128 @ 0x80
80035f6: 0049 lsls r1, r1, #1
80035f8: 430a orrs r2, r1
80035fa: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80035fc: f7fd fd8e bl 800111c <HAL_GetTick>
8003600: 0003 movs r3, r0
8003602: 613b str r3, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003604: e008 b.n 8003618 <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003606: f7fd fd89 bl 800111c <HAL_GetTick>
800360a: 0002 movs r2, r0
800360c: 693b ldr r3, [r7, #16]
800360e: 1ad3 subs r3, r2, r3
8003610: 2b02 cmp r3, #2
8003612: d901 bls.n 8003618 <HAL_RCC_OscConfig+0x1fc>
{
return HAL_TIMEOUT;
8003614: 2303 movs r3, #3
8003616: e1fe b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003618: 4b4b ldr r3, [pc, #300] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800361a: 681a ldr r2, [r3, #0]
800361c: 2380 movs r3, #128 @ 0x80
800361e: 00db lsls r3, r3, #3
8003620: 4013 ands r3, r2
8003622: d0f0 beq.n 8003606 <HAL_RCC_OscConfig+0x1ea>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003624: 4b48 ldr r3, [pc, #288] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003626: 685b ldr r3, [r3, #4]
8003628: 4a4a ldr r2, [pc, #296] @ (8003754 <HAL_RCC_OscConfig+0x338>)
800362a: 4013 ands r3, r2
800362c: 0019 movs r1, r3
800362e: 687b ldr r3, [r7, #4]
8003630: 695b ldr r3, [r3, #20]
8003632: 021a lsls r2, r3, #8
8003634: 4b44 ldr r3, [pc, #272] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003636: 430a orrs r2, r1
8003638: 605a str r2, [r3, #4]
800363a: e01b b.n 8003674 <HAL_RCC_OscConfig+0x258>
}
else
{
/* Disable the Internal High Speed oscillator (HSI16). */
__HAL_RCC_HSI_DISABLE();
800363c: 4b42 ldr r3, [pc, #264] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800363e: 681a ldr r2, [r3, #0]
8003640: 4b41 ldr r3, [pc, #260] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003642: 4949 ldr r1, [pc, #292] @ (8003768 <HAL_RCC_OscConfig+0x34c>)
8003644: 400a ands r2, r1
8003646: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003648: f7fd fd68 bl 800111c <HAL_GetTick>
800364c: 0003 movs r3, r0
800364e: 613b str r3, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003650: e008 b.n 8003664 <HAL_RCC_OscConfig+0x248>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8003652: f7fd fd63 bl 800111c <HAL_GetTick>
8003656: 0002 movs r2, r0
8003658: 693b ldr r3, [r7, #16]
800365a: 1ad3 subs r3, r2, r3
800365c: 2b02 cmp r3, #2
800365e: d901 bls.n 8003664 <HAL_RCC_OscConfig+0x248>
{
return HAL_TIMEOUT;
8003660: 2303 movs r3, #3
8003662: e1d8 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003664: 4b38 ldr r3, [pc, #224] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003666: 681a ldr r2, [r3, #0]
8003668: 2380 movs r3, #128 @ 0x80
800366a: 00db lsls r3, r3, #3
800366c: 4013 ands r3, r2
800366e: d1f0 bne.n 8003652 <HAL_RCC_OscConfig+0x236>
8003670: e000 b.n 8003674 <HAL_RCC_OscConfig+0x258>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
8003672: 46c0 nop @ (mov r8, r8)
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003674: 687b ldr r3, [r7, #4]
8003676: 681b ldr r3, [r3, #0]
8003678: 2208 movs r2, #8
800367a: 4013 ands r3, r2
800367c: d047 beq.n 800370e <HAL_RCC_OscConfig+0x2f2>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check if LSI is used as system clock */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
800367e: 4b32 ldr r3, [pc, #200] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003680: 689b ldr r3, [r3, #8]
8003682: 2238 movs r2, #56 @ 0x38
8003684: 4013 ands r3, r2
8003686: 2b18 cmp r3, #24
8003688: d10a bne.n 80036a0 <HAL_RCC_OscConfig+0x284>
{
/* When LSI is used as system clock it will not be disabled */
if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF))
800368a: 4b2f ldr r3, [pc, #188] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
800368c: 6e1b ldr r3, [r3, #96] @ 0x60
800368e: 2202 movs r2, #2
8003690: 4013 ands r3, r2
8003692: d03c beq.n 800370e <HAL_RCC_OscConfig+0x2f2>
8003694: 687b ldr r3, [r7, #4]
8003696: 699b ldr r3, [r3, #24]
8003698: 2b00 cmp r3, #0
800369a: d138 bne.n 800370e <HAL_RCC_OscConfig+0x2f2>
{
return HAL_ERROR;
800369c: 2301 movs r3, #1
800369e: e1ba b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
}
else
{
/* Check the LSI State */
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80036a0: 687b ldr r3, [r7, #4]
80036a2: 699b ldr r3, [r3, #24]
80036a4: 2b00 cmp r3, #0
80036a6: d019 beq.n 80036dc <HAL_RCC_OscConfig+0x2c0>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80036a8: 4b27 ldr r3, [pc, #156] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80036aa: 6e1a ldr r2, [r3, #96] @ 0x60
80036ac: 4b26 ldr r3, [pc, #152] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80036ae: 2101 movs r1, #1
80036b0: 430a orrs r2, r1
80036b2: 661a str r2, [r3, #96] @ 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
80036b4: f7fd fd32 bl 800111c <HAL_GetTick>
80036b8: 0003 movs r3, r0
80036ba: 613b str r3, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80036bc: e008 b.n 80036d0 <HAL_RCC_OscConfig+0x2b4>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80036be: f7fd fd2d bl 800111c <HAL_GetTick>
80036c2: 0002 movs r2, r0
80036c4: 693b ldr r3, [r7, #16]
80036c6: 1ad3 subs r3, r2, r3
80036c8: 2b02 cmp r3, #2
80036ca: d901 bls.n 80036d0 <HAL_RCC_OscConfig+0x2b4>
{
return HAL_TIMEOUT;
80036cc: 2303 movs r3, #3
80036ce: e1a2 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
80036d0: 4b1d ldr r3, [pc, #116] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80036d2: 6e1b ldr r3, [r3, #96] @ 0x60
80036d4: 2202 movs r2, #2
80036d6: 4013 ands r3, r2
80036d8: d0f1 beq.n 80036be <HAL_RCC_OscConfig+0x2a2>
80036da: e018 b.n 800370e <HAL_RCC_OscConfig+0x2f2>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80036dc: 4b1a ldr r3, [pc, #104] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80036de: 6e1a ldr r2, [r3, #96] @ 0x60
80036e0: 4b19 ldr r3, [pc, #100] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
80036e2: 2101 movs r1, #1
80036e4: 438a bics r2, r1
80036e6: 661a str r2, [r3, #96] @ 0x60
/* Get Start Tick*/
tickstart = HAL_GetTick();
80036e8: f7fd fd18 bl 800111c <HAL_GetTick>
80036ec: 0003 movs r3, r0
80036ee: 613b str r3, [r7, #16]
/* Wait till LSI is disabled */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
80036f0: e008 b.n 8003704 <HAL_RCC_OscConfig+0x2e8>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80036f2: f7fd fd13 bl 800111c <HAL_GetTick>
80036f6: 0002 movs r2, r0
80036f8: 693b ldr r3, [r7, #16]
80036fa: 1ad3 subs r3, r2, r3
80036fc: 2b02 cmp r3, #2
80036fe: d901 bls.n 8003704 <HAL_RCC_OscConfig+0x2e8>
{
return HAL_TIMEOUT;
8003700: 2303 movs r3, #3
8003702: e188 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8003704: 4b10 ldr r3, [pc, #64] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003706: 6e1b ldr r3, [r3, #96] @ 0x60
8003708: 2202 movs r2, #2
800370a: 4013 ands r3, r2
800370c: d1f1 bne.n 80036f2 <HAL_RCC_OscConfig+0x2d6>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800370e: 687b ldr r3, [r7, #4]
8003710: 681b ldr r3, [r3, #0]
8003712: 2204 movs r2, #4
8003714: 4013 ands r3, r2
8003716: d100 bne.n 800371a <HAL_RCC_OscConfig+0x2fe>
8003718: e0c6 b.n 80038a8 <HAL_RCC_OscConfig+0x48c>
{
FlagStatus pwrclkchanged = RESET;
800371a: 231f movs r3, #31
800371c: 18fb adds r3, r7, r3
800371e: 2200 movs r2, #0
8003720: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* When the LSE is used as system clock, it is not allowed disable it */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8003722: 4b09 ldr r3, [pc, #36] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003724: 689b ldr r3, [r3, #8]
8003726: 2238 movs r2, #56 @ 0x38
8003728: 4013 ands r3, r2
800372a: 2b20 cmp r3, #32
800372c: d11e bne.n 800376c <HAL_RCC_OscConfig+0x350>
{
if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF))
800372e: 4b06 ldr r3, [pc, #24] @ (8003748 <HAL_RCC_OscConfig+0x32c>)
8003730: 6ddb ldr r3, [r3, #92] @ 0x5c
8003732: 2202 movs r2, #2
8003734: 4013 ands r3, r2
8003736: d100 bne.n 800373a <HAL_RCC_OscConfig+0x31e>
8003738: e0b6 b.n 80038a8 <HAL_RCC_OscConfig+0x48c>
800373a: 687b ldr r3, [r7, #4]
800373c: 689b ldr r3, [r3, #8]
800373e: 2b00 cmp r3, #0
8003740: d000 beq.n 8003744 <HAL_RCC_OscConfig+0x328>
8003742: e0b1 b.n 80038a8 <HAL_RCC_OscConfig+0x48c>
{
return HAL_ERROR;
8003744: 2301 movs r3, #1
8003746: e166 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
8003748: 40021000 .word 0x40021000
800374c: fffeffff .word 0xfffeffff
8003750: fffbffff .word 0xfffbffff
8003754: ffff80ff .word 0xffff80ff
8003758: ffffc7ff .word 0xffffc7ff
800375c: 00f42400 .word 0x00f42400
8003760: 20000004 .word 0x20000004
8003764: 20000008 .word 0x20000008
8003768: fffffeff .word 0xfffffeff
}
else
{
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
800376c: 4bac ldr r3, [pc, #688] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800376e: 6bda ldr r2, [r3, #60] @ 0x3c
8003770: 2380 movs r3, #128 @ 0x80
8003772: 055b lsls r3, r3, #21
8003774: 4013 ands r3, r2
8003776: d101 bne.n 800377c <HAL_RCC_OscConfig+0x360>
8003778: 2301 movs r3, #1
800377a: e000 b.n 800377e <HAL_RCC_OscConfig+0x362>
800377c: 2300 movs r3, #0
800377e: 2b00 cmp r3, #0
8003780: d011 beq.n 80037a6 <HAL_RCC_OscConfig+0x38a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003782: 4ba7 ldr r3, [pc, #668] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003784: 6bda ldr r2, [r3, #60] @ 0x3c
8003786: 4ba6 ldr r3, [pc, #664] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003788: 2180 movs r1, #128 @ 0x80
800378a: 0549 lsls r1, r1, #21
800378c: 430a orrs r2, r1
800378e: 63da str r2, [r3, #60] @ 0x3c
8003790: 4ba3 ldr r3, [pc, #652] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003792: 6bda ldr r2, [r3, #60] @ 0x3c
8003794: 2380 movs r3, #128 @ 0x80
8003796: 055b lsls r3, r3, #21
8003798: 4013 ands r3, r2
800379a: 60fb str r3, [r7, #12]
800379c: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
800379e: 231f movs r3, #31
80037a0: 18fb adds r3, r7, r3
80037a2: 2201 movs r2, #1
80037a4: 701a strb r2, [r3, #0]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80037a6: 4b9f ldr r3, [pc, #636] @ (8003a24 <HAL_RCC_OscConfig+0x608>)
80037a8: 681a ldr r2, [r3, #0]
80037aa: 2380 movs r3, #128 @ 0x80
80037ac: 005b lsls r3, r3, #1
80037ae: 4013 ands r3, r2
80037b0: d11a bne.n 80037e8 <HAL_RCC_OscConfig+0x3cc>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80037b2: 4b9c ldr r3, [pc, #624] @ (8003a24 <HAL_RCC_OscConfig+0x608>)
80037b4: 681a ldr r2, [r3, #0]
80037b6: 4b9b ldr r3, [pc, #620] @ (8003a24 <HAL_RCC_OscConfig+0x608>)
80037b8: 2180 movs r1, #128 @ 0x80
80037ba: 0049 lsls r1, r1, #1
80037bc: 430a orrs r2, r1
80037be: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80037c0: f7fd fcac bl 800111c <HAL_GetTick>
80037c4: 0003 movs r3, r0
80037c6: 613b str r3, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80037c8: e008 b.n 80037dc <HAL_RCC_OscConfig+0x3c0>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80037ca: f7fd fca7 bl 800111c <HAL_GetTick>
80037ce: 0002 movs r2, r0
80037d0: 693b ldr r3, [r7, #16]
80037d2: 1ad3 subs r3, r2, r3
80037d4: 2b02 cmp r3, #2
80037d6: d901 bls.n 80037dc <HAL_RCC_OscConfig+0x3c0>
{
return HAL_TIMEOUT;
80037d8: 2303 movs r3, #3
80037da: e11c b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80037dc: 4b91 ldr r3, [pc, #580] @ (8003a24 <HAL_RCC_OscConfig+0x608>)
80037de: 681a ldr r2, [r3, #0]
80037e0: 2380 movs r3, #128 @ 0x80
80037e2: 005b lsls r3, r3, #1
80037e4: 4013 ands r3, r2
80037e6: d0f0 beq.n 80037ca <HAL_RCC_OscConfig+0x3ae>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80037e8: 687b ldr r3, [r7, #4]
80037ea: 689b ldr r3, [r3, #8]
80037ec: 2b01 cmp r3, #1
80037ee: d106 bne.n 80037fe <HAL_RCC_OscConfig+0x3e2>
80037f0: 4b8b ldr r3, [pc, #556] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80037f2: 6dda ldr r2, [r3, #92] @ 0x5c
80037f4: 4b8a ldr r3, [pc, #552] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80037f6: 2101 movs r1, #1
80037f8: 430a orrs r2, r1
80037fa: 65da str r2, [r3, #92] @ 0x5c
80037fc: e01c b.n 8003838 <HAL_RCC_OscConfig+0x41c>
80037fe: 687b ldr r3, [r7, #4]
8003800: 689b ldr r3, [r3, #8]
8003802: 2b05 cmp r3, #5
8003804: d10c bne.n 8003820 <HAL_RCC_OscConfig+0x404>
8003806: 4b86 ldr r3, [pc, #536] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003808: 6dda ldr r2, [r3, #92] @ 0x5c
800380a: 4b85 ldr r3, [pc, #532] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800380c: 2104 movs r1, #4
800380e: 430a orrs r2, r1
8003810: 65da str r2, [r3, #92] @ 0x5c
8003812: 4b83 ldr r3, [pc, #524] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003814: 6dda ldr r2, [r3, #92] @ 0x5c
8003816: 4b82 ldr r3, [pc, #520] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003818: 2101 movs r1, #1
800381a: 430a orrs r2, r1
800381c: 65da str r2, [r3, #92] @ 0x5c
800381e: e00b b.n 8003838 <HAL_RCC_OscConfig+0x41c>
8003820: 4b7f ldr r3, [pc, #508] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003822: 6dda ldr r2, [r3, #92] @ 0x5c
8003824: 4b7e ldr r3, [pc, #504] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003826: 2101 movs r1, #1
8003828: 438a bics r2, r1
800382a: 65da str r2, [r3, #92] @ 0x5c
800382c: 4b7c ldr r3, [pc, #496] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800382e: 6dda ldr r2, [r3, #92] @ 0x5c
8003830: 4b7b ldr r3, [pc, #492] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003832: 2104 movs r1, #4
8003834: 438a bics r2, r1
8003836: 65da str r2, [r3, #92] @ 0x5c
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8003838: 687b ldr r3, [r7, #4]
800383a: 689b ldr r3, [r3, #8]
800383c: 2b00 cmp r3, #0
800383e: d014 beq.n 800386a <HAL_RCC_OscConfig+0x44e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003840: f7fd fc6c bl 800111c <HAL_GetTick>
8003844: 0003 movs r3, r0
8003846: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003848: e009 b.n 800385e <HAL_RCC_OscConfig+0x442>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800384a: f7fd fc67 bl 800111c <HAL_GetTick>
800384e: 0002 movs r2, r0
8003850: 693b ldr r3, [r7, #16]
8003852: 1ad3 subs r3, r2, r3
8003854: 4a74 ldr r2, [pc, #464] @ (8003a28 <HAL_RCC_OscConfig+0x60c>)
8003856: 4293 cmp r3, r2
8003858: d901 bls.n 800385e <HAL_RCC_OscConfig+0x442>
{
return HAL_TIMEOUT;
800385a: 2303 movs r3, #3
800385c: e0db b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800385e: 4b70 ldr r3, [pc, #448] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003860: 6ddb ldr r3, [r3, #92] @ 0x5c
8003862: 2202 movs r2, #2
8003864: 4013 ands r3, r2
8003866: d0f0 beq.n 800384a <HAL_RCC_OscConfig+0x42e>
8003868: e013 b.n 8003892 <HAL_RCC_OscConfig+0x476>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800386a: f7fd fc57 bl 800111c <HAL_GetTick>
800386e: 0003 movs r3, r0
8003870: 613b str r3, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003872: e009 b.n 8003888 <HAL_RCC_OscConfig+0x46c>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003874: f7fd fc52 bl 800111c <HAL_GetTick>
8003878: 0002 movs r2, r0
800387a: 693b ldr r3, [r7, #16]
800387c: 1ad3 subs r3, r2, r3
800387e: 4a6a ldr r2, [pc, #424] @ (8003a28 <HAL_RCC_OscConfig+0x60c>)
8003880: 4293 cmp r3, r2
8003882: d901 bls.n 8003888 <HAL_RCC_OscConfig+0x46c>
{
return HAL_TIMEOUT;
8003884: 2303 movs r3, #3
8003886: e0c6 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8003888: 4b65 ldr r3, [pc, #404] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800388a: 6ddb ldr r3, [r3, #92] @ 0x5c
800388c: 2202 movs r2, #2
800388e: 4013 ands r3, r2
8003890: d1f0 bne.n 8003874 <HAL_RCC_OscConfig+0x458>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003892: 231f movs r3, #31
8003894: 18fb adds r3, r7, r3
8003896: 781b ldrb r3, [r3, #0]
8003898: 2b01 cmp r3, #1
800389a: d105 bne.n 80038a8 <HAL_RCC_OscConfig+0x48c>
{
__HAL_RCC_PWR_CLK_DISABLE();
800389c: 4b60 ldr r3, [pc, #384] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800389e: 6bda ldr r2, [r3, #60] @ 0x3c
80038a0: 4b5f ldr r3, [pc, #380] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038a2: 4962 ldr r1, [pc, #392] @ (8003a2c <HAL_RCC_OscConfig+0x610>)
80038a4: 400a ands r2, r1
80038a6: 63da str r2, [r3, #60] @ 0x3c
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
80038a8: 687b ldr r3, [r7, #4]
80038aa: 69db ldr r3, [r3, #28]
80038ac: 2b00 cmp r3, #0
80038ae: d100 bne.n 80038b2 <HAL_RCC_OscConfig+0x496>
80038b0: e0b0 b.n 8003a14 <HAL_RCC_OscConfig+0x5f8>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
80038b2: 4b5b ldr r3, [pc, #364] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038b4: 689b ldr r3, [r3, #8]
80038b6: 2238 movs r2, #56 @ 0x38
80038b8: 4013 ands r3, r2
80038ba: 2b10 cmp r3, #16
80038bc: d100 bne.n 80038c0 <HAL_RCC_OscConfig+0x4a4>
80038be: e078 b.n 80039b2 <HAL_RCC_OscConfig+0x596>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
80038c0: 687b ldr r3, [r7, #4]
80038c2: 69db ldr r3, [r3, #28]
80038c4: 2b02 cmp r3, #2
80038c6: d153 bne.n 8003970 <HAL_RCC_OscConfig+0x554>
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
#endif /* RCC_PLLQ_SUPPORT */
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80038c8: 4b55 ldr r3, [pc, #340] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038ca: 681a ldr r2, [r3, #0]
80038cc: 4b54 ldr r3, [pc, #336] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038ce: 4958 ldr r1, [pc, #352] @ (8003a30 <HAL_RCC_OscConfig+0x614>)
80038d0: 400a ands r2, r1
80038d2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80038d4: f7fd fc22 bl 800111c <HAL_GetTick>
80038d8: 0003 movs r3, r0
80038da: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80038dc: e008 b.n 80038f0 <HAL_RCC_OscConfig+0x4d4>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80038de: f7fd fc1d bl 800111c <HAL_GetTick>
80038e2: 0002 movs r2, r0
80038e4: 693b ldr r3, [r7, #16]
80038e6: 1ad3 subs r3, r2, r3
80038e8: 2b02 cmp r3, #2
80038ea: d901 bls.n 80038f0 <HAL_RCC_OscConfig+0x4d4>
{
return HAL_TIMEOUT;
80038ec: 2303 movs r3, #3
80038ee: e092 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80038f0: 4b4b ldr r3, [pc, #300] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038f2: 681a ldr r2, [r3, #0]
80038f4: 2380 movs r3, #128 @ 0x80
80038f6: 049b lsls r3, r3, #18
80038f8: 4013 ands r3, r2
80038fa: d1f0 bne.n 80038de <HAL_RCC_OscConfig+0x4c2>
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
#else /* !RCC_PLLQ_SUPPORT */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80038fc: 4b48 ldr r3, [pc, #288] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80038fe: 68db ldr r3, [r3, #12]
8003900: 4a4c ldr r2, [pc, #304] @ (8003a34 <HAL_RCC_OscConfig+0x618>)
8003902: 4013 ands r3, r2
8003904: 0019 movs r1, r3
8003906: 687b ldr r3, [r7, #4]
8003908: 6a1a ldr r2, [r3, #32]
800390a: 687b ldr r3, [r7, #4]
800390c: 6a5b ldr r3, [r3, #36] @ 0x24
800390e: 431a orrs r2, r3
8003910: 687b ldr r3, [r7, #4]
8003912: 6a9b ldr r3, [r3, #40] @ 0x28
8003914: 021b lsls r3, r3, #8
8003916: 431a orrs r2, r3
8003918: 687b ldr r3, [r7, #4]
800391a: 6adb ldr r3, [r3, #44] @ 0x2c
800391c: 431a orrs r2, r3
800391e: 687b ldr r3, [r7, #4]
8003920: 6b1b ldr r3, [r3, #48] @ 0x30
8003922: 431a orrs r2, r3
8003924: 4b3e ldr r3, [pc, #248] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003926: 430a orrs r2, r1
8003928: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLR);
#endif /* RCC_PLLQ_SUPPORT */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800392a: 4b3d ldr r3, [pc, #244] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800392c: 681a ldr r2, [r3, #0]
800392e: 4b3c ldr r3, [pc, #240] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003930: 2180 movs r1, #128 @ 0x80
8003932: 0449 lsls r1, r1, #17
8003934: 430a orrs r2, r1
8003936: 601a str r2, [r3, #0]
/* Enable PLLR Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK);
8003938: 4b39 ldr r3, [pc, #228] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800393a: 68da ldr r2, [r3, #12]
800393c: 4b38 ldr r3, [pc, #224] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800393e: 2180 movs r1, #128 @ 0x80
8003940: 0549 lsls r1, r1, #21
8003942: 430a orrs r2, r1
8003944: 60da str r2, [r3, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003946: f7fd fbe9 bl 800111c <HAL_GetTick>
800394a: 0003 movs r3, r0
800394c: 613b str r3, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
800394e: e008 b.n 8003962 <HAL_RCC_OscConfig+0x546>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003950: f7fd fbe4 bl 800111c <HAL_GetTick>
8003954: 0002 movs r2, r0
8003956: 693b ldr r3, [r7, #16]
8003958: 1ad3 subs r3, r2, r3
800395a: 2b02 cmp r3, #2
800395c: d901 bls.n 8003962 <HAL_RCC_OscConfig+0x546>
{
return HAL_TIMEOUT;
800395e: 2303 movs r3, #3
8003960: e059 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003962: 4b2f ldr r3, [pc, #188] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003964: 681a ldr r2, [r3, #0]
8003966: 2380 movs r3, #128 @ 0x80
8003968: 049b lsls r3, r3, #18
800396a: 4013 ands r3, r2
800396c: d0f0 beq.n 8003950 <HAL_RCC_OscConfig+0x534>
800396e: e051 b.n 8003a14 <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003970: 4b2b ldr r3, [pc, #172] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003972: 681a ldr r2, [r3, #0]
8003974: 4b2a ldr r3, [pc, #168] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
8003976: 492e ldr r1, [pc, #184] @ (8003a30 <HAL_RCC_OscConfig+0x614>)
8003978: 400a ands r2, r1
800397a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800397c: f7fd fbce bl 800111c <HAL_GetTick>
8003980: 0003 movs r3, r0
8003982: 613b str r3, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003984: e008 b.n 8003998 <HAL_RCC_OscConfig+0x57c>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8003986: f7fd fbc9 bl 800111c <HAL_GetTick>
800398a: 0002 movs r2, r0
800398c: 693b ldr r3, [r7, #16]
800398e: 1ad3 subs r3, r2, r3
8003990: 2b02 cmp r3, #2
8003992: d901 bls.n 8003998 <HAL_RCC_OscConfig+0x57c>
{
return HAL_TIMEOUT;
8003994: 2303 movs r3, #3
8003996: e03e b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8003998: 4b21 ldr r3, [pc, #132] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
800399a: 681a ldr r2, [r3, #0]
800399c: 2380 movs r3, #128 @ 0x80
800399e: 049b lsls r3, r3, #18
80039a0: 4013 ands r3, r2
80039a2: d1f0 bne.n 8003986 <HAL_RCC_OscConfig+0x56a>
}
/* Unselect main PLL clock source and disable main PLL outputs to save power */
#if defined(RCC_PLLQ_SUPPORT)
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN);
#else
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN);
80039a4: 4b1e ldr r3, [pc, #120] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80039a6: 68da ldr r2, [r3, #12]
80039a8: 4b1d ldr r3, [pc, #116] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80039aa: 4923 ldr r1, [pc, #140] @ (8003a38 <HAL_RCC_OscConfig+0x61c>)
80039ac: 400a ands r2, r1
80039ae: 60da str r2, [r3, #12]
80039b0: e030 b.n 8003a14 <HAL_RCC_OscConfig+0x5f8>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80039b2: 687b ldr r3, [r7, #4]
80039b4: 69db ldr r3, [r3, #28]
80039b6: 2b01 cmp r3, #1
80039b8: d101 bne.n 80039be <HAL_RCC_OscConfig+0x5a2>
{
return HAL_ERROR;
80039ba: 2301 movs r3, #1
80039bc: e02b b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
80039be: 4b18 ldr r3, [pc, #96] @ (8003a20 <HAL_RCC_OscConfig+0x604>)
80039c0: 68db ldr r3, [r3, #12]
80039c2: 617b str r3, [r7, #20]
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80039c4: 697b ldr r3, [r7, #20]
80039c6: 2203 movs r2, #3
80039c8: 401a ands r2, r3
80039ca: 687b ldr r3, [r7, #4]
80039cc: 6a1b ldr r3, [r3, #32]
80039ce: 429a cmp r2, r3
80039d0: d11e bne.n 8003a10 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80039d2: 697b ldr r3, [r7, #20]
80039d4: 2270 movs r2, #112 @ 0x70
80039d6: 401a ands r2, r3
80039d8: 687b ldr r3, [r7, #4]
80039da: 6a5b ldr r3, [r3, #36] @ 0x24
if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80039dc: 429a cmp r2, r3
80039de: d117 bne.n 8003a10 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80039e0: 697a ldr r2, [r7, #20]
80039e2: 23fe movs r3, #254 @ 0xfe
80039e4: 01db lsls r3, r3, #7
80039e6: 401a ands r2, r3
80039e8: 687b ldr r3, [r7, #4]
80039ea: 6a9b ldr r3, [r3, #40] @ 0x28
80039ec: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
80039ee: 429a cmp r2, r3
80039f0: d10e bne.n 8003a10 <HAL_RCC_OscConfig+0x5f4>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
80039f2: 697a ldr r2, [r7, #20]
80039f4: 23f8 movs r3, #248 @ 0xf8
80039f6: 039b lsls r3, r3, #14
80039f8: 401a ands r2, r3
80039fa: 687b ldr r3, [r7, #4]
80039fc: 6adb ldr r3, [r3, #44] @ 0x2c
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
80039fe: 429a cmp r2, r3
8003a00: d106 bne.n 8003a10 <HAL_RCC_OscConfig+0x5f4>
#if defined (RCC_PLLQ_SUPPORT)
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
#endif /* RCC_PLLQ_SUPPORT */
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
8003a02: 697b ldr r3, [r7, #20]
8003a04: 0f5b lsrs r3, r3, #29
8003a06: 075a lsls r2, r3, #29
8003a08: 687b ldr r3, [r7, #4]
8003a0a: 6b1b ldr r3, [r3, #48] @ 0x30
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
8003a0c: 429a cmp r2, r3
8003a0e: d001 beq.n 8003a14 <HAL_RCC_OscConfig+0x5f8>
{
return HAL_ERROR;
8003a10: 2301 movs r3, #1
8003a12: e000 b.n 8003a16 <HAL_RCC_OscConfig+0x5fa>
}
}
}
}
return HAL_OK;
8003a14: 2300 movs r3, #0
}
8003a16: 0018 movs r0, r3
8003a18: 46bd mov sp, r7
8003a1a: b008 add sp, #32
8003a1c: bd80 pop {r7, pc}
8003a1e: 46c0 nop @ (mov r8, r8)
8003a20: 40021000 .word 0x40021000
8003a24: 40007000 .word 0x40007000
8003a28: 00001388 .word 0x00001388
8003a2c: efffffff .word 0xefffffff
8003a30: feffffff .word 0xfeffffff
8003a34: 1fc1808c .word 0x1fc1808c
8003a38: effefffc .word 0xeffefffc
08003a3c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003a3c: b580 push {r7, lr}
8003a3e: b084 sub sp, #16
8003a40: af00 add r7, sp, #0
8003a42: 6078 str r0, [r7, #4]
8003a44: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8003a46: 687b ldr r3, [r7, #4]
8003a48: 2b00 cmp r3, #0
8003a4a: d101 bne.n 8003a50 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8003a4c: 2301 movs r3, #1
8003a4e: e0e9 b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the FLASH clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8003a50: 4b76 ldr r3, [pc, #472] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003a52: 681b ldr r3, [r3, #0]
8003a54: 2207 movs r2, #7
8003a56: 4013 ands r3, r2
8003a58: 683a ldr r2, [r7, #0]
8003a5a: 429a cmp r2, r3
8003a5c: d91e bls.n 8003a9c <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003a5e: 4b73 ldr r3, [pc, #460] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003a60: 681b ldr r3, [r3, #0]
8003a62: 2207 movs r2, #7
8003a64: 4393 bics r3, r2
8003a66: 0019 movs r1, r3
8003a68: 4b70 ldr r3, [pc, #448] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003a6a: 683a ldr r2, [r7, #0]
8003a6c: 430a orrs r2, r1
8003a6e: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8003a70: f7fd fb54 bl 800111c <HAL_GetTick>
8003a74: 0003 movs r3, r0
8003a76: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003a78: e009 b.n 8003a8e <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003a7a: f7fd fb4f bl 800111c <HAL_GetTick>
8003a7e: 0002 movs r2, r0
8003a80: 68fb ldr r3, [r7, #12]
8003a82: 1ad3 subs r3, r2, r3
8003a84: 4a6a ldr r2, [pc, #424] @ (8003c30 <HAL_RCC_ClockConfig+0x1f4>)
8003a86: 4293 cmp r3, r2
8003a88: d901 bls.n 8003a8e <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
8003a8a: 2303 movs r3, #3
8003a8c: e0ca b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003a8e: 4b67 ldr r3, [pc, #412] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003a90: 681b ldr r3, [r3, #0]
8003a92: 2207 movs r2, #7
8003a94: 4013 ands r3, r2
8003a96: 683a ldr r2, [r7, #0]
8003a98: 429a cmp r2, r3
8003a9a: d1ee bne.n 8003a7a <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8003a9c: 687b ldr r3, [r7, #4]
8003a9e: 681b ldr r3, [r3, #0]
8003aa0: 2202 movs r2, #2
8003aa2: 4013 ands r3, r2
8003aa4: d015 beq.n 8003ad2 <HAL_RCC_ClockConfig+0x96>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003aa6: 687b ldr r3, [r7, #4]
8003aa8: 681b ldr r3, [r3, #0]
8003aaa: 2204 movs r2, #4
8003aac: 4013 ands r3, r2
8003aae: d006 beq.n 8003abe <HAL_RCC_ClockConfig+0x82>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
8003ab0: 4b60 ldr r3, [pc, #384] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003ab2: 689a ldr r2, [r3, #8]
8003ab4: 4b5f ldr r3, [pc, #380] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003ab6: 21e0 movs r1, #224 @ 0xe0
8003ab8: 01c9 lsls r1, r1, #7
8003aba: 430a orrs r2, r1
8003abc: 609a str r2, [r3, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003abe: 4b5d ldr r3, [pc, #372] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003ac0: 689b ldr r3, [r3, #8]
8003ac2: 4a5d ldr r2, [pc, #372] @ (8003c38 <HAL_RCC_ClockConfig+0x1fc>)
8003ac4: 4013 ands r3, r2
8003ac6: 0019 movs r1, r3
8003ac8: 687b ldr r3, [r7, #4]
8003aca: 689a ldr r2, [r3, #8]
8003acc: 4b59 ldr r3, [pc, #356] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003ace: 430a orrs r2, r1
8003ad0: 609a str r2, [r3, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003ad2: 687b ldr r3, [r7, #4]
8003ad4: 681b ldr r3, [r3, #0]
8003ad6: 2201 movs r2, #1
8003ad8: 4013 ands r3, r2
8003ada: d057 beq.n 8003b8c <HAL_RCC_ClockConfig+0x150>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003adc: 687b ldr r3, [r7, #4]
8003ade: 685b ldr r3, [r3, #4]
8003ae0: 2b01 cmp r3, #1
8003ae2: d107 bne.n 8003af4 <HAL_RCC_ClockConfig+0xb8>
{
/* Check the HSE ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8003ae4: 4b53 ldr r3, [pc, #332] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003ae6: 681a ldr r2, [r3, #0]
8003ae8: 2380 movs r3, #128 @ 0x80
8003aea: 029b lsls r3, r3, #10
8003aec: 4013 ands r3, r2
8003aee: d12b bne.n 8003b48 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003af0: 2301 movs r3, #1
8003af2: e097 b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* PLL is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8003af4: 687b ldr r3, [r7, #4]
8003af6: 685b ldr r3, [r3, #4]
8003af8: 2b02 cmp r3, #2
8003afa: d107 bne.n 8003b0c <HAL_RCC_ClockConfig+0xd0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8003afc: 4b4d ldr r3, [pc, #308] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003afe: 681a ldr r2, [r3, #0]
8003b00: 2380 movs r3, #128 @ 0x80
8003b02: 049b lsls r3, r3, #18
8003b04: 4013 ands r3, r2
8003b06: d11f bne.n 8003b48 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003b08: 2301 movs r3, #1
8003b0a: e08b b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* HSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8003b0c: 687b ldr r3, [r7, #4]
8003b0e: 685b ldr r3, [r3, #4]
8003b10: 2b00 cmp r3, #0
8003b12: d107 bne.n 8003b24 <HAL_RCC_ClockConfig+0xe8>
{
/* Check the HSI ready flag */
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003b14: 4b47 ldr r3, [pc, #284] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b16: 681a ldr r2, [r3, #0]
8003b18: 2380 movs r3, #128 @ 0x80
8003b1a: 00db lsls r3, r3, #3
8003b1c: 4013 ands r3, r2
8003b1e: d113 bne.n 8003b48 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003b20: 2301 movs r3, #1
8003b22: e07f b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
}
}
/* LSI is selected as System Clock Source */
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
8003b24: 687b ldr r3, [r7, #4]
8003b26: 685b ldr r3, [r3, #4]
8003b28: 2b03 cmp r3, #3
8003b2a: d106 bne.n 8003b3a <HAL_RCC_ClockConfig+0xfe>
{
/* Check the LSI ready flag */
if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8003b2c: 4b41 ldr r3, [pc, #260] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b2e: 6e1b ldr r3, [r3, #96] @ 0x60
8003b30: 2202 movs r2, #2
8003b32: 4013 ands r3, r2
8003b34: d108 bne.n 8003b48 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003b36: 2301 movs r3, #1
8003b38: e074 b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
}
/* LSE is selected as System Clock Source */
else
{
/* Check the LSE ready flag */
if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003b3a: 4b3e ldr r3, [pc, #248] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b3c: 6ddb ldr r3, [r3, #92] @ 0x5c
8003b3e: 2202 movs r2, #2
8003b40: 4013 ands r3, r2
8003b42: d101 bne.n 8003b48 <HAL_RCC_ClockConfig+0x10c>
{
return HAL_ERROR;
8003b44: 2301 movs r3, #1
8003b46: e06d b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8003b48: 4b3a ldr r3, [pc, #232] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b4a: 689b ldr r3, [r3, #8]
8003b4c: 2207 movs r2, #7
8003b4e: 4393 bics r3, r2
8003b50: 0019 movs r1, r3
8003b52: 687b ldr r3, [r7, #4]
8003b54: 685a ldr r2, [r3, #4]
8003b56: 4b37 ldr r3, [pc, #220] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b58: 430a orrs r2, r1
8003b5a: 609a str r2, [r3, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003b5c: f7fd fade bl 800111c <HAL_GetTick>
8003b60: 0003 movs r3, r0
8003b62: 60fb str r3, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003b64: e009 b.n 8003b7a <HAL_RCC_ClockConfig+0x13e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003b66: f7fd fad9 bl 800111c <HAL_GetTick>
8003b6a: 0002 movs r2, r0
8003b6c: 68fb ldr r3, [r7, #12]
8003b6e: 1ad3 subs r3, r2, r3
8003b70: 4a2f ldr r2, [pc, #188] @ (8003c30 <HAL_RCC_ClockConfig+0x1f4>)
8003b72: 4293 cmp r3, r2
8003b74: d901 bls.n 8003b7a <HAL_RCC_ClockConfig+0x13e>
{
return HAL_TIMEOUT;
8003b76: 2303 movs r3, #3
8003b78: e054 b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003b7a: 4b2e ldr r3, [pc, #184] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003b7c: 689b ldr r3, [r3, #8]
8003b7e: 2238 movs r2, #56 @ 0x38
8003b80: 401a ands r2, r3
8003b82: 687b ldr r3, [r7, #4]
8003b84: 685b ldr r3, [r3, #4]
8003b86: 00db lsls r3, r3, #3
8003b88: 429a cmp r2, r3
8003b8a: d1ec bne.n 8003b66 <HAL_RCC_ClockConfig+0x12a>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8003b8c: 4b27 ldr r3, [pc, #156] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003b8e: 681b ldr r3, [r3, #0]
8003b90: 2207 movs r2, #7
8003b92: 4013 ands r3, r2
8003b94: 683a ldr r2, [r7, #0]
8003b96: 429a cmp r2, r3
8003b98: d21e bcs.n 8003bd8 <HAL_RCC_ClockConfig+0x19c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8003b9a: 4b24 ldr r3, [pc, #144] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003b9c: 681b ldr r3, [r3, #0]
8003b9e: 2207 movs r2, #7
8003ba0: 4393 bics r3, r2
8003ba2: 0019 movs r1, r3
8003ba4: 4b21 ldr r3, [pc, #132] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003ba6: 683a ldr r2, [r7, #0]
8003ba8: 430a orrs r2, r1
8003baa: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8003bac: f7fd fab6 bl 800111c <HAL_GetTick>
8003bb0: 0003 movs r3, r0
8003bb2: 60fb str r3, [r7, #12]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003bb4: e009 b.n 8003bca <HAL_RCC_ClockConfig+0x18e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003bb6: f7fd fab1 bl 800111c <HAL_GetTick>
8003bba: 0002 movs r2, r0
8003bbc: 68fb ldr r3, [r7, #12]
8003bbe: 1ad3 subs r3, r2, r3
8003bc0: 4a1b ldr r2, [pc, #108] @ (8003c30 <HAL_RCC_ClockConfig+0x1f4>)
8003bc2: 4293 cmp r3, r2
8003bc4: d901 bls.n 8003bca <HAL_RCC_ClockConfig+0x18e>
{
return HAL_TIMEOUT;
8003bc6: 2303 movs r3, #3
8003bc8: e02c b.n 8003c24 <HAL_RCC_ClockConfig+0x1e8>
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003bca: 4b18 ldr r3, [pc, #96] @ (8003c2c <HAL_RCC_ClockConfig+0x1f0>)
8003bcc: 681b ldr r3, [r3, #0]
8003bce: 2207 movs r2, #7
8003bd0: 4013 ands r3, r2
8003bd2: 683a ldr r2, [r7, #0]
8003bd4: 429a cmp r2, r3
8003bd6: d1ee bne.n 8003bb6 <HAL_RCC_ClockConfig+0x17a>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003bd8: 687b ldr r3, [r7, #4]
8003bda: 681b ldr r3, [r3, #0]
8003bdc: 2204 movs r2, #4
8003bde: 4013 ands r3, r2
8003be0: d009 beq.n 8003bf6 <HAL_RCC_ClockConfig+0x1ba>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8003be2: 4b14 ldr r3, [pc, #80] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003be4: 689b ldr r3, [r3, #8]
8003be6: 4a15 ldr r2, [pc, #84] @ (8003c3c <HAL_RCC_ClockConfig+0x200>)
8003be8: 4013 ands r3, r2
8003bea: 0019 movs r1, r3
8003bec: 687b ldr r3, [r7, #4]
8003bee: 68da ldr r2, [r3, #12]
8003bf0: 4b10 ldr r3, [pc, #64] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003bf2: 430a orrs r2, r1
8003bf4: 609a str r2, [r3, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
8003bf6: f000 f829 bl 8003c4c <HAL_RCC_GetSysClockFreq>
8003bfa: 0001 movs r1, r0
8003bfc: 4b0d ldr r3, [pc, #52] @ (8003c34 <HAL_RCC_ClockConfig+0x1f8>)
8003bfe: 689b ldr r3, [r3, #8]
8003c00: 0a1b lsrs r3, r3, #8
8003c02: 220f movs r2, #15
8003c04: 401a ands r2, r3
8003c06: 4b0e ldr r3, [pc, #56] @ (8003c40 <HAL_RCC_ClockConfig+0x204>)
8003c08: 0092 lsls r2, r2, #2
8003c0a: 58d3 ldr r3, [r2, r3]
8003c0c: 221f movs r2, #31
8003c0e: 4013 ands r3, r2
8003c10: 000a movs r2, r1
8003c12: 40da lsrs r2, r3
8003c14: 4b0b ldr r3, [pc, #44] @ (8003c44 <HAL_RCC_ClockConfig+0x208>)
8003c16: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8003c18: 4b0b ldr r3, [pc, #44] @ (8003c48 <HAL_RCC_ClockConfig+0x20c>)
8003c1a: 681b ldr r3, [r3, #0]
8003c1c: 0018 movs r0, r3
8003c1e: f7fd fa21 bl 8001064 <HAL_InitTick>
8003c22: 0003 movs r3, r0
}
8003c24: 0018 movs r0, r3
8003c26: 46bd mov sp, r7
8003c28: b004 add sp, #16
8003c2a: bd80 pop {r7, pc}
8003c2c: 40022000 .word 0x40022000
8003c30: 00001388 .word 0x00001388
8003c34: 40021000 .word 0x40021000
8003c38: fffff0ff .word 0xfffff0ff
8003c3c: ffff8fff .word 0xffff8fff
8003c40: 08004b1c .word 0x08004b1c
8003c44: 20000004 .word 0x20000004
8003c48: 20000008 .word 0x20000008
08003c4c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003c4c: b580 push {r7, lr}
8003c4e: b086 sub sp, #24
8003c50: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm, hsidiv;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8003c52: 4b3c ldr r3, [pc, #240] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003c54: 689b ldr r3, [r3, #8]
8003c56: 2238 movs r2, #56 @ 0x38
8003c58: 4013 ands r3, r2
8003c5a: d10f bne.n 8003c7c <HAL_RCC_GetSysClockFreq+0x30>
{
/* HSISYS can be derived for HSI16 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
8003c5c: 4b39 ldr r3, [pc, #228] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003c5e: 681b ldr r3, [r3, #0]
8003c60: 0adb lsrs r3, r3, #11
8003c62: 2207 movs r2, #7
8003c64: 4013 ands r3, r2
8003c66: 2201 movs r2, #1
8003c68: 409a lsls r2, r3
8003c6a: 0013 movs r3, r2
8003c6c: 603b str r3, [r7, #0]
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
8003c6e: 6839 ldr r1, [r7, #0]
8003c70: 4835 ldr r0, [pc, #212] @ (8003d48 <HAL_RCC_GetSysClockFreq+0xfc>)
8003c72: f7fc fa45 bl 8000100 <__udivsi3>
8003c76: 0003 movs r3, r0
8003c78: 613b str r3, [r7, #16]
8003c7a: e05d b.n 8003d38 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8003c7c: 4b31 ldr r3, [pc, #196] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003c7e: 689b ldr r3, [r3, #8]
8003c80: 2238 movs r2, #56 @ 0x38
8003c82: 4013 ands r3, r2
8003c84: 2b08 cmp r3, #8
8003c86: d102 bne.n 8003c8e <HAL_RCC_GetSysClockFreq+0x42>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8003c88: 4b30 ldr r3, [pc, #192] @ (8003d4c <HAL_RCC_GetSysClockFreq+0x100>)
8003c8a: 613b str r3, [r7, #16]
8003c8c: e054 b.n 8003d38 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
8003c8e: 4b2d ldr r3, [pc, #180] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003c90: 689b ldr r3, [r3, #8]
8003c92: 2238 movs r2, #56 @ 0x38
8003c94: 4013 ands r3, r2
8003c96: 2b10 cmp r3, #16
8003c98: d138 bne.n 8003d0c <HAL_RCC_GetSysClockFreq+0xc0>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
8003c9a: 4b2a ldr r3, [pc, #168] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003c9c: 68db ldr r3, [r3, #12]
8003c9e: 2203 movs r2, #3
8003ca0: 4013 ands r3, r2
8003ca2: 60fb str r3, [r7, #12]
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8003ca4: 4b27 ldr r3, [pc, #156] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003ca6: 68db ldr r3, [r3, #12]
8003ca8: 091b lsrs r3, r3, #4
8003caa: 2207 movs r2, #7
8003cac: 4013 ands r3, r2
8003cae: 3301 adds r3, #1
8003cb0: 60bb str r3, [r7, #8]
switch (pllsource)
8003cb2: 68fb ldr r3, [r7, #12]
8003cb4: 2b03 cmp r3, #3
8003cb6: d10d bne.n 8003cd4 <HAL_RCC_GetSysClockFreq+0x88>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8003cb8: 68b9 ldr r1, [r7, #8]
8003cba: 4824 ldr r0, [pc, #144] @ (8003d4c <HAL_RCC_GetSysClockFreq+0x100>)
8003cbc: f7fc fa20 bl 8000100 <__udivsi3>
8003cc0: 0003 movs r3, r0
8003cc2: 0019 movs r1, r3
8003cc4: 4b1f ldr r3, [pc, #124] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003cc6: 68db ldr r3, [r3, #12]
8003cc8: 0a1b lsrs r3, r3, #8
8003cca: 227f movs r2, #127 @ 0x7f
8003ccc: 4013 ands r3, r2
8003cce: 434b muls r3, r1
8003cd0: 617b str r3, [r7, #20]
break;
8003cd2: e00d b.n 8003cf0 <HAL_RCC_GetSysClockFreq+0xa4>
case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */
default: /* HSI16 used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ;
8003cd4: 68b9 ldr r1, [r7, #8]
8003cd6: 481c ldr r0, [pc, #112] @ (8003d48 <HAL_RCC_GetSysClockFreq+0xfc>)
8003cd8: f7fc fa12 bl 8000100 <__udivsi3>
8003cdc: 0003 movs r3, r0
8003cde: 0019 movs r1, r3
8003ce0: 4b18 ldr r3, [pc, #96] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003ce2: 68db ldr r3, [r3, #12]
8003ce4: 0a1b lsrs r3, r3, #8
8003ce6: 227f movs r2, #127 @ 0x7f
8003ce8: 4013 ands r3, r2
8003cea: 434b muls r3, r1
8003cec: 617b str r3, [r7, #20]
break;
8003cee: 46c0 nop @ (mov r8, r8)
}
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
8003cf0: 4b14 ldr r3, [pc, #80] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003cf2: 68db ldr r3, [r3, #12]
8003cf4: 0f5b lsrs r3, r3, #29
8003cf6: 2207 movs r2, #7
8003cf8: 4013 ands r3, r2
8003cfa: 3301 adds r3, #1
8003cfc: 607b str r3, [r7, #4]
sysclockfreq = pllvco / pllr;
8003cfe: 6879 ldr r1, [r7, #4]
8003d00: 6978 ldr r0, [r7, #20]
8003d02: f7fc f9fd bl 8000100 <__udivsi3>
8003d06: 0003 movs r3, r0
8003d08: 613b str r3, [r7, #16]
8003d0a: e015 b.n 8003d38 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE)
8003d0c: 4b0d ldr r3, [pc, #52] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003d0e: 689b ldr r3, [r3, #8]
8003d10: 2238 movs r2, #56 @ 0x38
8003d12: 4013 ands r3, r2
8003d14: 2b20 cmp r3, #32
8003d16: d103 bne.n 8003d20 <HAL_RCC_GetSysClockFreq+0xd4>
{
/* LSE used as system clock source */
sysclockfreq = LSE_VALUE;
8003d18: 2380 movs r3, #128 @ 0x80
8003d1a: 021b lsls r3, r3, #8
8003d1c: 613b str r3, [r7, #16]
8003d1e: e00b b.n 8003d38 <HAL_RCC_GetSysClockFreq+0xec>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI)
8003d20: 4b08 ldr r3, [pc, #32] @ (8003d44 <HAL_RCC_GetSysClockFreq+0xf8>)
8003d22: 689b ldr r3, [r3, #8]
8003d24: 2238 movs r2, #56 @ 0x38
8003d26: 4013 ands r3, r2
8003d28: 2b18 cmp r3, #24
8003d2a: d103 bne.n 8003d34 <HAL_RCC_GetSysClockFreq+0xe8>
{
/* LSI used as system clock source */
sysclockfreq = LSI_VALUE;
8003d2c: 23fa movs r3, #250 @ 0xfa
8003d2e: 01db lsls r3, r3, #7
8003d30: 613b str r3, [r7, #16]
8003d32: e001 b.n 8003d38 <HAL_RCC_GetSysClockFreq+0xec>
}
else
{
sysclockfreq = 0U;
8003d34: 2300 movs r3, #0
8003d36: 613b str r3, [r7, #16]
}
return sysclockfreq;
8003d38: 693b ldr r3, [r7, #16]
}
8003d3a: 0018 movs r0, r3
8003d3c: 46bd mov sp, r7
8003d3e: b006 add sp, #24
8003d40: bd80 pop {r7, pc}
8003d42: 46c0 nop @ (mov r8, r8)
8003d44: 40021000 .word 0x40021000
8003d48: 00f42400 .word 0x00f42400
8003d4c: 007a1200 .word 0x007a1200
08003d50 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003d50: b580 push {r7, lr}
8003d52: af00 add r7, sp, #0
return SystemCoreClock;
8003d54: 4b02 ldr r3, [pc, #8] @ (8003d60 <HAL_RCC_GetHCLKFreq+0x10>)
8003d56: 681b ldr r3, [r3, #0]
}
8003d58: 0018 movs r0, r3
8003d5a: 46bd mov sp, r7
8003d5c: bd80 pop {r7, pc}
8003d5e: 46c0 nop @ (mov r8, r8)
8003d60: 20000004 .word 0x20000004
08003d64 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8003d64: b5b0 push {r4, r5, r7, lr}
8003d66: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler())));
8003d68: f7ff fff2 bl 8003d50 <HAL_RCC_GetHCLKFreq>
8003d6c: 0004 movs r4, r0
8003d6e: f7ff fb49 bl 8003404 <LL_RCC_GetAPB1Prescaler>
8003d72: 0003 movs r3, r0
8003d74: 0b1a lsrs r2, r3, #12
8003d76: 4b05 ldr r3, [pc, #20] @ (8003d8c <HAL_RCC_GetPCLK1Freq+0x28>)
8003d78: 0092 lsls r2, r2, #2
8003d7a: 58d3 ldr r3, [r2, r3]
8003d7c: 221f movs r2, #31
8003d7e: 4013 ands r3, r2
8003d80: 40dc lsrs r4, r3
8003d82: 0023 movs r3, r4
}
8003d84: 0018 movs r0, r3
8003d86: 46bd mov sp, r7
8003d88: bdb0 pop {r4, r5, r7, pc}
8003d8a: 46c0 nop @ (mov r8, r8)
8003d8c: 08004b5c .word 0x08004b5c
08003d90 <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8003d90: b580 push {r7, lr}
8003d92: b086 sub sp, #24
8003d94: af00 add r7, sp, #0
8003d96: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8003d98: 2313 movs r3, #19
8003d9a: 18fb adds r3, r7, r3
8003d9c: 2200 movs r2, #0
8003d9e: 701a strb r2, [r3, #0]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8003da0: 2312 movs r3, #18
8003da2: 18fb adds r3, r7, r3
8003da4: 2200 movs r2, #0
8003da6: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8003da8: 687b ldr r3, [r7, #4]
8003daa: 681a ldr r2, [r3, #0]
8003dac: 2380 movs r3, #128 @ 0x80
8003dae: 029b lsls r3, r3, #10
8003db0: 4013 ands r3, r2
8003db2: d100 bne.n 8003db6 <HAL_RCCEx_PeriphCLKConfig+0x26>
8003db4: e0a3 b.n 8003efe <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
FlagStatus pwrclkchanged = RESET;
8003db6: 2011 movs r0, #17
8003db8: 183b adds r3, r7, r0
8003dba: 2200 movs r2, #0
8003dbc: 701a strb r2, [r3, #0]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
8003dbe: 4b86 ldr r3, [pc, #536] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003dc0: 6bda ldr r2, [r3, #60] @ 0x3c
8003dc2: 2380 movs r3, #128 @ 0x80
8003dc4: 055b lsls r3, r3, #21
8003dc6: 4013 ands r3, r2
8003dc8: d110 bne.n 8003dec <HAL_RCCEx_PeriphCLKConfig+0x5c>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003dca: 4b83 ldr r3, [pc, #524] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003dcc: 6bda ldr r2, [r3, #60] @ 0x3c
8003dce: 4b82 ldr r3, [pc, #520] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003dd0: 2180 movs r1, #128 @ 0x80
8003dd2: 0549 lsls r1, r1, #21
8003dd4: 430a orrs r2, r1
8003dd6: 63da str r2, [r3, #60] @ 0x3c
8003dd8: 4b7f ldr r3, [pc, #508] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003dda: 6bda ldr r2, [r3, #60] @ 0x3c
8003ddc: 2380 movs r3, #128 @ 0x80
8003dde: 055b lsls r3, r3, #21
8003de0: 4013 ands r3, r2
8003de2: 60bb str r3, [r7, #8]
8003de4: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003de6: 183b adds r3, r7, r0
8003de8: 2201 movs r2, #1
8003dea: 701a strb r2, [r3, #0]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8003dec: 4b7b ldr r3, [pc, #492] @ (8003fdc <HAL_RCCEx_PeriphCLKConfig+0x24c>)
8003dee: 681a ldr r2, [r3, #0]
8003df0: 4b7a ldr r3, [pc, #488] @ (8003fdc <HAL_RCCEx_PeriphCLKConfig+0x24c>)
8003df2: 2180 movs r1, #128 @ 0x80
8003df4: 0049 lsls r1, r1, #1
8003df6: 430a orrs r2, r1
8003df8: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003dfa: f7fd f98f bl 800111c <HAL_GetTick>
8003dfe: 0003 movs r3, r0
8003e00: 60fb str r3, [r7, #12]
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
8003e02: e00b b.n 8003e1c <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003e04: f7fd f98a bl 800111c <HAL_GetTick>
8003e08: 0002 movs r2, r0
8003e0a: 68fb ldr r3, [r7, #12]
8003e0c: 1ad3 subs r3, r2, r3
8003e0e: 2b02 cmp r3, #2
8003e10: d904 bls.n 8003e1c <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
ret = HAL_TIMEOUT;
8003e12: 2313 movs r3, #19
8003e14: 18fb adds r3, r7, r3
8003e16: 2203 movs r2, #3
8003e18: 701a strb r2, [r3, #0]
break;
8003e1a: e005 b.n 8003e28 <HAL_RCCEx_PeriphCLKConfig+0x98>
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
8003e1c: 4b6f ldr r3, [pc, #444] @ (8003fdc <HAL_RCCEx_PeriphCLKConfig+0x24c>)
8003e1e: 681a ldr r2, [r3, #0]
8003e20: 2380 movs r3, #128 @ 0x80
8003e22: 005b lsls r3, r3, #1
8003e24: 4013 ands r3, r2
8003e26: d0ed beq.n 8003e04 <HAL_RCCEx_PeriphCLKConfig+0x74>
}
}
if (ret == HAL_OK)
8003e28: 2313 movs r3, #19
8003e2a: 18fb adds r3, r7, r3
8003e2c: 781b ldrb r3, [r3, #0]
8003e2e: 2b00 cmp r3, #0
8003e30: d154 bne.n 8003edc <HAL_RCCEx_PeriphCLKConfig+0x14c>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8003e32: 4b69 ldr r3, [pc, #420] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e34: 6dda ldr r2, [r3, #92] @ 0x5c
8003e36: 23c0 movs r3, #192 @ 0xc0
8003e38: 009b lsls r3, r3, #2
8003e3a: 4013 ands r3, r2
8003e3c: 617b str r3, [r7, #20]
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8003e3e: 697b ldr r3, [r7, #20]
8003e40: 2b00 cmp r3, #0
8003e42: d019 beq.n 8003e78 <HAL_RCCEx_PeriphCLKConfig+0xe8>
8003e44: 687b ldr r3, [r7, #4]
8003e46: 699b ldr r3, [r3, #24]
8003e48: 697a ldr r2, [r7, #20]
8003e4a: 429a cmp r2, r3
8003e4c: d014 beq.n 8003e78 <HAL_RCCEx_PeriphCLKConfig+0xe8>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8003e4e: 4b62 ldr r3, [pc, #392] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e50: 6ddb ldr r3, [r3, #92] @ 0x5c
8003e52: 4a63 ldr r2, [pc, #396] @ (8003fe0 <HAL_RCCEx_PeriphCLKConfig+0x250>)
8003e54: 4013 ands r3, r2
8003e56: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8003e58: 4b5f ldr r3, [pc, #380] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e5a: 6dda ldr r2, [r3, #92] @ 0x5c
8003e5c: 4b5e ldr r3, [pc, #376] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e5e: 2180 movs r1, #128 @ 0x80
8003e60: 0249 lsls r1, r1, #9
8003e62: 430a orrs r2, r1
8003e64: 65da str r2, [r3, #92] @ 0x5c
__HAL_RCC_BACKUPRESET_RELEASE();
8003e66: 4b5c ldr r3, [pc, #368] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e68: 6dda ldr r2, [r3, #92] @ 0x5c
8003e6a: 4b5b ldr r3, [pc, #364] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e6c: 495d ldr r1, [pc, #372] @ (8003fe4 <HAL_RCCEx_PeriphCLKConfig+0x254>)
8003e6e: 400a ands r2, r1
8003e70: 65da str r2, [r3, #92] @ 0x5c
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8003e72: 4b59 ldr r3, [pc, #356] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003e74: 697a ldr r2, [r7, #20]
8003e76: 65da str r2, [r3, #92] @ 0x5c
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8003e78: 697b ldr r3, [r7, #20]
8003e7a: 2201 movs r2, #1
8003e7c: 4013 ands r3, r2
8003e7e: d016 beq.n 8003eae <HAL_RCCEx_PeriphCLKConfig+0x11e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e80: f7fd f94c bl 800111c <HAL_GetTick>
8003e84: 0003 movs r3, r0
8003e86: 60fb str r3, [r7, #12]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003e88: e00c b.n 8003ea4 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003e8a: f7fd f947 bl 800111c <HAL_GetTick>
8003e8e: 0002 movs r2, r0
8003e90: 68fb ldr r3, [r7, #12]
8003e92: 1ad3 subs r3, r2, r3
8003e94: 4a54 ldr r2, [pc, #336] @ (8003fe8 <HAL_RCCEx_PeriphCLKConfig+0x258>)
8003e96: 4293 cmp r3, r2
8003e98: d904 bls.n 8003ea4 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
ret = HAL_TIMEOUT;
8003e9a: 2313 movs r3, #19
8003e9c: 18fb adds r3, r7, r3
8003e9e: 2203 movs r2, #3
8003ea0: 701a strb r2, [r3, #0]
break;
8003ea2: e004 b.n 8003eae <HAL_RCCEx_PeriphCLKConfig+0x11e>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8003ea4: 4b4c ldr r3, [pc, #304] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003ea6: 6ddb ldr r3, [r3, #92] @ 0x5c
8003ea8: 2202 movs r2, #2
8003eaa: 4013 ands r3, r2
8003eac: d0ed beq.n 8003e8a <HAL_RCCEx_PeriphCLKConfig+0xfa>
}
}
}
if (ret == HAL_OK)
8003eae: 2313 movs r3, #19
8003eb0: 18fb adds r3, r7, r3
8003eb2: 781b ldrb r3, [r3, #0]
8003eb4: 2b00 cmp r3, #0
8003eb6: d10a bne.n 8003ece <HAL_RCCEx_PeriphCLKConfig+0x13e>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003eb8: 4b47 ldr r3, [pc, #284] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003eba: 6ddb ldr r3, [r3, #92] @ 0x5c
8003ebc: 4a48 ldr r2, [pc, #288] @ (8003fe0 <HAL_RCCEx_PeriphCLKConfig+0x250>)
8003ebe: 4013 ands r3, r2
8003ec0: 0019 movs r1, r3
8003ec2: 687b ldr r3, [r7, #4]
8003ec4: 699a ldr r2, [r3, #24]
8003ec6: 4b44 ldr r3, [pc, #272] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003ec8: 430a orrs r2, r1
8003eca: 65da str r2, [r3, #92] @ 0x5c
8003ecc: e00c b.n 8003ee8 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
else
{
/* set overall return value */
status = ret;
8003ece: 2312 movs r3, #18
8003ed0: 18fb adds r3, r7, r3
8003ed2: 2213 movs r2, #19
8003ed4: 18ba adds r2, r7, r2
8003ed6: 7812 ldrb r2, [r2, #0]
8003ed8: 701a strb r2, [r3, #0]
8003eda: e005 b.n 8003ee8 <HAL_RCCEx_PeriphCLKConfig+0x158>
}
}
else
{
/* set overall return value */
status = ret;
8003edc: 2312 movs r3, #18
8003ede: 18fb adds r3, r7, r3
8003ee0: 2213 movs r2, #19
8003ee2: 18ba adds r2, r7, r2
8003ee4: 7812 ldrb r2, [r2, #0]
8003ee6: 701a strb r2, [r3, #0]
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003ee8: 2311 movs r3, #17
8003eea: 18fb adds r3, r7, r3
8003eec: 781b ldrb r3, [r3, #0]
8003eee: 2b01 cmp r3, #1
8003ef0: d105 bne.n 8003efe <HAL_RCCEx_PeriphCLKConfig+0x16e>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003ef2: 4b39 ldr r3, [pc, #228] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003ef4: 6bda ldr r2, [r3, #60] @ 0x3c
8003ef6: 4b38 ldr r3, [pc, #224] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003ef8: 493c ldr r1, [pc, #240] @ (8003fec <HAL_RCCEx_PeriphCLKConfig+0x25c>)
8003efa: 400a ands r2, r1
8003efc: 63da str r2, [r3, #60] @ 0x3c
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8003efe: 687b ldr r3, [r7, #4]
8003f00: 681b ldr r3, [r3, #0]
8003f02: 2201 movs r2, #1
8003f04: 4013 ands r3, r2
8003f06: d009 beq.n 8003f1c <HAL_RCCEx_PeriphCLKConfig+0x18c>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8003f08: 4b33 ldr r3, [pc, #204] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f0a: 6d5b ldr r3, [r3, #84] @ 0x54
8003f0c: 2203 movs r2, #3
8003f0e: 4393 bics r3, r2
8003f10: 0019 movs r1, r3
8003f12: 687b ldr r3, [r7, #4]
8003f14: 685a ldr r2, [r3, #4]
8003f16: 4b30 ldr r3, [pc, #192] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f18: 430a orrs r2, r1
8003f1a: 655a str r2, [r3, #84] @ 0x54
}
#if defined(RCC_CCIPR_USART2SEL)
/*-------------------------- USART2 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
8003f1c: 687b ldr r3, [r7, #4]
8003f1e: 681b ldr r3, [r3, #0]
8003f20: 2202 movs r2, #2
8003f22: 4013 ands r3, r2
8003f24: d009 beq.n 8003f3a <HAL_RCCEx_PeriphCLKConfig+0x1aa>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
8003f26: 4b2c ldr r3, [pc, #176] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f28: 6d5b ldr r3, [r3, #84] @ 0x54
8003f2a: 220c movs r2, #12
8003f2c: 4393 bics r3, r2
8003f2e: 0019 movs r1, r3
8003f30: 687b ldr r3, [r7, #4]
8003f32: 689a ldr r2, [r3, #8]
8003f34: 4b28 ldr r3, [pc, #160] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f36: 430a orrs r2, r1
8003f38: 655a str r2, [r3, #84] @ 0x54
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
}
#endif /* RCC_CCIPR_LPTIM2SEL */
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 681b ldr r3, [r3, #0]
8003f3e: 2220 movs r2, #32
8003f40: 4013 ands r3, r2
8003f42: d009 beq.n 8003f58 <HAL_RCCEx_PeriphCLKConfig+0x1c8>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003f44: 4b24 ldr r3, [pc, #144] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f46: 6d5b ldr r3, [r3, #84] @ 0x54
8003f48: 4a29 ldr r2, [pc, #164] @ (8003ff0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
8003f4a: 4013 ands r3, r2
8003f4c: 0019 movs r1, r3
8003f4e: 687b ldr r3, [r7, #4]
8003f50: 68da ldr r2, [r3, #12]
8003f52: 4b21 ldr r3, [pc, #132] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f54: 430a orrs r2, r1
8003f56: 655a str r2, [r3, #84] @ 0x54
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* RNG */
/*-------------------------- ADC clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003f58: 687b ldr r3, [r7, #4]
8003f5a: 681a ldr r2, [r3, #0]
8003f5c: 2380 movs r3, #128 @ 0x80
8003f5e: 01db lsls r3, r3, #7
8003f60: 4013 ands r3, r2
8003f62: d015 beq.n 8003f90 <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003f64: 4b1c ldr r3, [pc, #112] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f66: 6d5b ldr r3, [r3, #84] @ 0x54
8003f68: 009b lsls r3, r3, #2
8003f6a: 0899 lsrs r1, r3, #2
8003f6c: 687b ldr r3, [r7, #4]
8003f6e: 695a ldr r2, [r3, #20]
8003f70: 4b19 ldr r3, [pc, #100] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f72: 430a orrs r2, r1
8003f74: 655a str r2, [r3, #84] @ 0x54
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC)
8003f76: 687b ldr r3, [r7, #4]
8003f78: 695a ldr r2, [r3, #20]
8003f7a: 2380 movs r3, #128 @ 0x80
8003f7c: 05db lsls r3, r3, #23
8003f7e: 429a cmp r2, r3
8003f80: d106 bne.n 8003f90 <HAL_RCCEx_PeriphCLKConfig+0x200>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
8003f82: 4b15 ldr r3, [pc, #84] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f84: 68da ldr r2, [r3, #12]
8003f86: 4b14 ldr r3, [pc, #80] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f88: 2180 movs r1, #128 @ 0x80
8003f8a: 0249 lsls r1, r1, #9
8003f8c: 430a orrs r2, r1
8003f8e: 60da str r2, [r3, #12]
}
}
#endif /* RCC_CCIPR_TIM15SEL */
/*-------------------------- I2S1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
8003f90: 687b ldr r3, [r7, #4]
8003f92: 681a ldr r2, [r3, #0]
8003f94: 2380 movs r3, #128 @ 0x80
8003f96: 011b lsls r3, r3, #4
8003f98: 4013 ands r3, r2
8003f9a: d016 beq.n 8003fca <HAL_RCCEx_PeriphCLKConfig+0x23a>
{
/* Check the parameters */
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
/* Configure the I2S1 clock source */
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
8003f9c: 4b0e ldr r3, [pc, #56] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003f9e: 6d5b ldr r3, [r3, #84] @ 0x54
8003fa0: 4a14 ldr r2, [pc, #80] @ (8003ff4 <HAL_RCCEx_PeriphCLKConfig+0x264>)
8003fa2: 4013 ands r3, r2
8003fa4: 0019 movs r1, r3
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 691a ldr r2, [r3, #16]
8003faa: 4b0b ldr r3, [pc, #44] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003fac: 430a orrs r2, r1
8003fae: 655a str r2, [r3, #84] @ 0x54
if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL)
8003fb0: 687b ldr r3, [r7, #4]
8003fb2: 691a ldr r2, [r3, #16]
8003fb4: 2380 movs r3, #128 @ 0x80
8003fb6: 01db lsls r3, r3, #7
8003fb8: 429a cmp r2, r3
8003fba: d106 bne.n 8003fca <HAL_RCCEx_PeriphCLKConfig+0x23a>
{
/* Enable PLLPCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK);
8003fbc: 4b06 ldr r3, [pc, #24] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003fbe: 68da ldr r2, [r3, #12]
8003fc0: 4b05 ldr r3, [pc, #20] @ (8003fd8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
8003fc2: 2180 movs r1, #128 @ 0x80
8003fc4: 0249 lsls r1, r1, #9
8003fc6: 430a orrs r2, r1
8003fc8: 60da str r2, [r3, #12]
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK);
}
}
#endif /* FDCAN1 || FDCAN2 */
return status;
8003fca: 2312 movs r3, #18
8003fcc: 18fb adds r3, r7, r3
8003fce: 781b ldrb r3, [r3, #0]
}
8003fd0: 0018 movs r0, r3
8003fd2: 46bd mov sp, r7
8003fd4: b006 add sp, #24
8003fd6: bd80 pop {r7, pc}
8003fd8: 40021000 .word 0x40021000
8003fdc: 40007000 .word 0x40007000
8003fe0: fffffcff .word 0xfffffcff
8003fe4: fffeffff .word 0xfffeffff
8003fe8: 00001388 .word 0x00001388
8003fec: efffffff .word 0xefffffff
8003ff0: ffffcfff .word 0xffffcfff
8003ff4: ffff3fff .word 0xffff3fff
08003ff8 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003ff8: b580 push {r7, lr}
8003ffa: b082 sub sp, #8
8003ffc: af00 add r7, sp, #0
8003ffe: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8004000: 687b ldr r3, [r7, #4]
8004002: 2b00 cmp r3, #0
8004004: d101 bne.n 800400a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8004006: 2301 movs r3, #1
8004008: e046 b.n 8004098 <HAL_UART_Init+0xa0>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
800400a: 687b ldr r3, [r7, #4]
800400c: 2288 movs r2, #136 @ 0x88
800400e: 589b ldr r3, [r3, r2]
8004010: 2b00 cmp r3, #0
8004012: d107 bne.n 8004024 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8004014: 687b ldr r3, [r7, #4]
8004016: 2284 movs r2, #132 @ 0x84
8004018: 2100 movs r1, #0
800401a: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800401c: 687b ldr r3, [r7, #4]
800401e: 0018 movs r0, r3
8004020: f7fc ff3e bl 8000ea0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8004024: 687b ldr r3, [r7, #4]
8004026: 2288 movs r2, #136 @ 0x88
8004028: 2124 movs r1, #36 @ 0x24
800402a: 5099 str r1, [r3, r2]
__HAL_UART_DISABLE(huart);
800402c: 687b ldr r3, [r7, #4]
800402e: 681b ldr r3, [r3, #0]
8004030: 681a ldr r2, [r3, #0]
8004032: 687b ldr r3, [r7, #4]
8004034: 681b ldr r3, [r3, #0]
8004036: 2101 movs r1, #1
8004038: 438a bics r2, r1
800403a: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800403c: 687b ldr r3, [r7, #4]
800403e: 6a9b ldr r3, [r3, #40] @ 0x28
8004040: 2b00 cmp r3, #0
8004042: d003 beq.n 800404c <HAL_UART_Init+0x54>
{
UART_AdvFeatureConfig(huart);
8004044: 687b ldr r3, [r7, #4]
8004046: 0018 movs r0, r3
8004048: f000 f9d0 bl 80043ec <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
800404c: 687b ldr r3, [r7, #4]
800404e: 0018 movs r0, r3
8004050: f000 f828 bl 80040a4 <UART_SetConfig>
8004054: 0003 movs r3, r0
8004056: 2b01 cmp r3, #1
8004058: d101 bne.n 800405e <HAL_UART_Init+0x66>
{
return HAL_ERROR;
800405a: 2301 movs r3, #1
800405c: e01c b.n 8004098 <HAL_UART_Init+0xa0>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800405e: 687b ldr r3, [r7, #4]
8004060: 681b ldr r3, [r3, #0]
8004062: 685a ldr r2, [r3, #4]
8004064: 687b ldr r3, [r7, #4]
8004066: 681b ldr r3, [r3, #0]
8004068: 490d ldr r1, [pc, #52] @ (80040a0 <HAL_UART_Init+0xa8>)
800406a: 400a ands r2, r1
800406c: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800406e: 687b ldr r3, [r7, #4]
8004070: 681b ldr r3, [r3, #0]
8004072: 689a ldr r2, [r3, #8]
8004074: 687b ldr r3, [r7, #4]
8004076: 681b ldr r3, [r3, #0]
8004078: 212a movs r1, #42 @ 0x2a
800407a: 438a bics r2, r1
800407c: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800407e: 687b ldr r3, [r7, #4]
8004080: 681b ldr r3, [r3, #0]
8004082: 681a ldr r2, [r3, #0]
8004084: 687b ldr r3, [r7, #4]
8004086: 681b ldr r3, [r3, #0]
8004088: 2101 movs r1, #1
800408a: 430a orrs r2, r1
800408c: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800408e: 687b ldr r3, [r7, #4]
8004090: 0018 movs r0, r3
8004092: f000 fa5f bl 8004554 <UART_CheckIdleState>
8004096: 0003 movs r3, r0
}
8004098: 0018 movs r0, r3
800409a: 46bd mov sp, r7
800409c: b002 add sp, #8
800409e: bd80 pop {r7, pc}
80040a0: ffffb7ff .word 0xffffb7ff
080040a4 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
80040a4: b580 push {r7, lr}
80040a6: b088 sub sp, #32
80040a8: af00 add r7, sp, #0
80040aa: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
80040ac: 231a movs r3, #26
80040ae: 18fb adds r3, r7, r3
80040b0: 2200 movs r2, #0
80040b2: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80040b4: 687b ldr r3, [r7, #4]
80040b6: 689a ldr r2, [r3, #8]
80040b8: 687b ldr r3, [r7, #4]
80040ba: 691b ldr r3, [r3, #16]
80040bc: 431a orrs r2, r3
80040be: 687b ldr r3, [r7, #4]
80040c0: 695b ldr r3, [r3, #20]
80040c2: 431a orrs r2, r3
80040c4: 687b ldr r3, [r7, #4]
80040c6: 69db ldr r3, [r3, #28]
80040c8: 4313 orrs r3, r2
80040ca: 61fb str r3, [r7, #28]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80040cc: 687b ldr r3, [r7, #4]
80040ce: 681b ldr r3, [r3, #0]
80040d0: 681b ldr r3, [r3, #0]
80040d2: 4abc ldr r2, [pc, #752] @ (80043c4 <UART_SetConfig+0x320>)
80040d4: 4013 ands r3, r2
80040d6: 0019 movs r1, r3
80040d8: 687b ldr r3, [r7, #4]
80040da: 681b ldr r3, [r3, #0]
80040dc: 69fa ldr r2, [r7, #28]
80040de: 430a orrs r2, r1
80040e0: 601a str r2, [r3, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80040e2: 687b ldr r3, [r7, #4]
80040e4: 681b ldr r3, [r3, #0]
80040e6: 685b ldr r3, [r3, #4]
80040e8: 4ab7 ldr r2, [pc, #732] @ (80043c8 <UART_SetConfig+0x324>)
80040ea: 4013 ands r3, r2
80040ec: 0019 movs r1, r3
80040ee: 687b ldr r3, [r7, #4]
80040f0: 68da ldr r2, [r3, #12]
80040f2: 687b ldr r3, [r7, #4]
80040f4: 681b ldr r3, [r3, #0]
80040f6: 430a orrs r2, r1
80040f8: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80040fa: 687b ldr r3, [r7, #4]
80040fc: 699b ldr r3, [r3, #24]
80040fe: 61fb str r3, [r7, #28]
if (!(UART_INSTANCE_LOWPOWER(huart)))
{
tmpreg |= huart->Init.OneBitSampling;
8004100: 687b ldr r3, [r7, #4]
8004102: 6a1b ldr r3, [r3, #32]
8004104: 69fa ldr r2, [r7, #28]
8004106: 4313 orrs r3, r2
8004108: 61fb str r3, [r7, #28]
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
800410a: 687b ldr r3, [r7, #4]
800410c: 681b ldr r3, [r3, #0]
800410e: 689b ldr r3, [r3, #8]
8004110: 4aae ldr r2, [pc, #696] @ (80043cc <UART_SetConfig+0x328>)
8004112: 4013 ands r3, r2
8004114: 0019 movs r1, r3
8004116: 687b ldr r3, [r7, #4]
8004118: 681b ldr r3, [r3, #0]
800411a: 69fa ldr r2, [r7, #28]
800411c: 430a orrs r2, r1
800411e: 609a str r2, [r3, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004120: 687b ldr r3, [r7, #4]
8004122: 681b ldr r3, [r3, #0]
8004124: 6adb ldr r3, [r3, #44] @ 0x2c
8004126: 220f movs r2, #15
8004128: 4393 bics r3, r2
800412a: 0019 movs r1, r3
800412c: 687b ldr r3, [r7, #4]
800412e: 6a5a ldr r2, [r3, #36] @ 0x24
8004130: 687b ldr r3, [r7, #4]
8004132: 681b ldr r3, [r3, #0]
8004134: 430a orrs r2, r1
8004136: 62da str r2, [r3, #44] @ 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8004138: 687b ldr r3, [r7, #4]
800413a: 681b ldr r3, [r3, #0]
800413c: 4aa4 ldr r2, [pc, #656] @ (80043d0 <UART_SetConfig+0x32c>)
800413e: 4293 cmp r3, r2
8004140: d127 bne.n 8004192 <UART_SetConfig+0xee>
8004142: 4ba4 ldr r3, [pc, #656] @ (80043d4 <UART_SetConfig+0x330>)
8004144: 6d5b ldr r3, [r3, #84] @ 0x54
8004146: 2203 movs r2, #3
8004148: 4013 ands r3, r2
800414a: 2b03 cmp r3, #3
800414c: d017 beq.n 800417e <UART_SetConfig+0xda>
800414e: d81b bhi.n 8004188 <UART_SetConfig+0xe4>
8004150: 2b02 cmp r3, #2
8004152: d00a beq.n 800416a <UART_SetConfig+0xc6>
8004154: d818 bhi.n 8004188 <UART_SetConfig+0xe4>
8004156: 2b00 cmp r3, #0
8004158: d002 beq.n 8004160 <UART_SetConfig+0xbc>
800415a: 2b01 cmp r3, #1
800415c: d00a beq.n 8004174 <UART_SetConfig+0xd0>
800415e: e013 b.n 8004188 <UART_SetConfig+0xe4>
8004160: 231b movs r3, #27
8004162: 18fb adds r3, r7, r3
8004164: 2200 movs r2, #0
8004166: 701a strb r2, [r3, #0]
8004168: e058 b.n 800421c <UART_SetConfig+0x178>
800416a: 231b movs r3, #27
800416c: 18fb adds r3, r7, r3
800416e: 2202 movs r2, #2
8004170: 701a strb r2, [r3, #0]
8004172: e053 b.n 800421c <UART_SetConfig+0x178>
8004174: 231b movs r3, #27
8004176: 18fb adds r3, r7, r3
8004178: 2204 movs r2, #4
800417a: 701a strb r2, [r3, #0]
800417c: e04e b.n 800421c <UART_SetConfig+0x178>
800417e: 231b movs r3, #27
8004180: 18fb adds r3, r7, r3
8004182: 2208 movs r2, #8
8004184: 701a strb r2, [r3, #0]
8004186: e049 b.n 800421c <UART_SetConfig+0x178>
8004188: 231b movs r3, #27
800418a: 18fb adds r3, r7, r3
800418c: 2210 movs r2, #16
800418e: 701a strb r2, [r3, #0]
8004190: e044 b.n 800421c <UART_SetConfig+0x178>
8004192: 687b ldr r3, [r7, #4]
8004194: 681b ldr r3, [r3, #0]
8004196: 4a90 ldr r2, [pc, #576] @ (80043d8 <UART_SetConfig+0x334>)
8004198: 4293 cmp r3, r2
800419a: d127 bne.n 80041ec <UART_SetConfig+0x148>
800419c: 4b8d ldr r3, [pc, #564] @ (80043d4 <UART_SetConfig+0x330>)
800419e: 6d5b ldr r3, [r3, #84] @ 0x54
80041a0: 220c movs r2, #12
80041a2: 4013 ands r3, r2
80041a4: 2b0c cmp r3, #12
80041a6: d017 beq.n 80041d8 <UART_SetConfig+0x134>
80041a8: d81b bhi.n 80041e2 <UART_SetConfig+0x13e>
80041aa: 2b08 cmp r3, #8
80041ac: d00a beq.n 80041c4 <UART_SetConfig+0x120>
80041ae: d818 bhi.n 80041e2 <UART_SetConfig+0x13e>
80041b0: 2b00 cmp r3, #0
80041b2: d002 beq.n 80041ba <UART_SetConfig+0x116>
80041b4: 2b04 cmp r3, #4
80041b6: d00a beq.n 80041ce <UART_SetConfig+0x12a>
80041b8: e013 b.n 80041e2 <UART_SetConfig+0x13e>
80041ba: 231b movs r3, #27
80041bc: 18fb adds r3, r7, r3
80041be: 2200 movs r2, #0
80041c0: 701a strb r2, [r3, #0]
80041c2: e02b b.n 800421c <UART_SetConfig+0x178>
80041c4: 231b movs r3, #27
80041c6: 18fb adds r3, r7, r3
80041c8: 2202 movs r2, #2
80041ca: 701a strb r2, [r3, #0]
80041cc: e026 b.n 800421c <UART_SetConfig+0x178>
80041ce: 231b movs r3, #27
80041d0: 18fb adds r3, r7, r3
80041d2: 2204 movs r2, #4
80041d4: 701a strb r2, [r3, #0]
80041d6: e021 b.n 800421c <UART_SetConfig+0x178>
80041d8: 231b movs r3, #27
80041da: 18fb adds r3, r7, r3
80041dc: 2208 movs r2, #8
80041de: 701a strb r2, [r3, #0]
80041e0: e01c b.n 800421c <UART_SetConfig+0x178>
80041e2: 231b movs r3, #27
80041e4: 18fb adds r3, r7, r3
80041e6: 2210 movs r2, #16
80041e8: 701a strb r2, [r3, #0]
80041ea: e017 b.n 800421c <UART_SetConfig+0x178>
80041ec: 687b ldr r3, [r7, #4]
80041ee: 681b ldr r3, [r3, #0]
80041f0: 4a7a ldr r2, [pc, #488] @ (80043dc <UART_SetConfig+0x338>)
80041f2: 4293 cmp r3, r2
80041f4: d104 bne.n 8004200 <UART_SetConfig+0x15c>
80041f6: 231b movs r3, #27
80041f8: 18fb adds r3, r7, r3
80041fa: 2200 movs r2, #0
80041fc: 701a strb r2, [r3, #0]
80041fe: e00d b.n 800421c <UART_SetConfig+0x178>
8004200: 687b ldr r3, [r7, #4]
8004202: 681b ldr r3, [r3, #0]
8004204: 4a76 ldr r2, [pc, #472] @ (80043e0 <UART_SetConfig+0x33c>)
8004206: 4293 cmp r3, r2
8004208: d104 bne.n 8004214 <UART_SetConfig+0x170>
800420a: 231b movs r3, #27
800420c: 18fb adds r3, r7, r3
800420e: 2200 movs r2, #0
8004210: 701a strb r2, [r3, #0]
8004212: e003 b.n 800421c <UART_SetConfig+0x178>
8004214: 231b movs r3, #27
8004216: 18fb adds r3, r7, r3
8004218: 2210 movs r2, #16
800421a: 701a strb r2, [r3, #0]
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
800421c: 687b ldr r3, [r7, #4]
800421e: 69da ldr r2, [r3, #28]
8004220: 2380 movs r3, #128 @ 0x80
8004222: 021b lsls r3, r3, #8
8004224: 429a cmp r2, r3
8004226: d000 beq.n 800422a <UART_SetConfig+0x186>
8004228: e065 b.n 80042f6 <UART_SetConfig+0x252>
{
switch (clocksource)
800422a: 231b movs r3, #27
800422c: 18fb adds r3, r7, r3
800422e: 781b ldrb r3, [r3, #0]
8004230: 2b08 cmp r3, #8
8004232: d015 beq.n 8004260 <UART_SetConfig+0x1bc>
8004234: dc18 bgt.n 8004268 <UART_SetConfig+0x1c4>
8004236: 2b04 cmp r3, #4
8004238: d00d beq.n 8004256 <UART_SetConfig+0x1b2>
800423a: dc15 bgt.n 8004268 <UART_SetConfig+0x1c4>
800423c: 2b00 cmp r3, #0
800423e: d002 beq.n 8004246 <UART_SetConfig+0x1a2>
8004240: 2b02 cmp r3, #2
8004242: d005 beq.n 8004250 <UART_SetConfig+0x1ac>
8004244: e010 b.n 8004268 <UART_SetConfig+0x1c4>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004246: f7ff fd8d bl 8003d64 <HAL_RCC_GetPCLK1Freq>
800424a: 0003 movs r3, r0
800424c: 617b str r3, [r7, #20]
break;
800424e: e012 b.n 8004276 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8004250: 4b64 ldr r3, [pc, #400] @ (80043e4 <UART_SetConfig+0x340>)
8004252: 617b str r3, [r7, #20]
break;
8004254: e00f b.n 8004276 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8004256: f7ff fcf9 bl 8003c4c <HAL_RCC_GetSysClockFreq>
800425a: 0003 movs r3, r0
800425c: 617b str r3, [r7, #20]
break;
800425e: e00a b.n 8004276 <UART_SetConfig+0x1d2>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8004260: 2380 movs r3, #128 @ 0x80
8004262: 021b lsls r3, r3, #8
8004264: 617b str r3, [r7, #20]
break;
8004266: e006 b.n 8004276 <UART_SetConfig+0x1d2>
default:
pclk = 0U;
8004268: 2300 movs r3, #0
800426a: 617b str r3, [r7, #20]
ret = HAL_ERROR;
800426c: 231a movs r3, #26
800426e: 18fb adds r3, r7, r3
8004270: 2201 movs r2, #1
8004272: 701a strb r2, [r3, #0]
break;
8004274: 46c0 nop @ (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8004276: 697b ldr r3, [r7, #20]
8004278: 2b00 cmp r3, #0
800427a: d100 bne.n 800427e <UART_SetConfig+0x1da>
800427c: e08d b.n 800439a <UART_SetConfig+0x2f6>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
800427e: 687b ldr r3, [r7, #4]
8004280: 6a5a ldr r2, [r3, #36] @ 0x24
8004282: 4b59 ldr r3, [pc, #356] @ (80043e8 <UART_SetConfig+0x344>)
8004284: 0052 lsls r2, r2, #1
8004286: 5ad3 ldrh r3, [r2, r3]
8004288: 0019 movs r1, r3
800428a: 6978 ldr r0, [r7, #20]
800428c: f7fb ff38 bl 8000100 <__udivsi3>
8004290: 0003 movs r3, r0
8004292: 005a lsls r2, r3, #1
8004294: 687b ldr r3, [r7, #4]
8004296: 685b ldr r3, [r3, #4]
8004298: 085b lsrs r3, r3, #1
800429a: 18d2 adds r2, r2, r3
800429c: 687b ldr r3, [r7, #4]
800429e: 685b ldr r3, [r3, #4]
80042a0: 0019 movs r1, r3
80042a2: 0010 movs r0, r2
80042a4: f7fb ff2c bl 8000100 <__udivsi3>
80042a8: 0003 movs r3, r0
80042aa: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80042ac: 693b ldr r3, [r7, #16]
80042ae: 2b0f cmp r3, #15
80042b0: d91c bls.n 80042ec <UART_SetConfig+0x248>
80042b2: 693a ldr r2, [r7, #16]
80042b4: 2380 movs r3, #128 @ 0x80
80042b6: 025b lsls r3, r3, #9
80042b8: 429a cmp r2, r3
80042ba: d217 bcs.n 80042ec <UART_SetConfig+0x248>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
80042bc: 693b ldr r3, [r7, #16]
80042be: b29a uxth r2, r3
80042c0: 200e movs r0, #14
80042c2: 183b adds r3, r7, r0
80042c4: 210f movs r1, #15
80042c6: 438a bics r2, r1
80042c8: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
80042ca: 693b ldr r3, [r7, #16]
80042cc: 085b lsrs r3, r3, #1
80042ce: b29b uxth r3, r3
80042d0: 2207 movs r2, #7
80042d2: 4013 ands r3, r2
80042d4: b299 uxth r1, r3
80042d6: 183b adds r3, r7, r0
80042d8: 183a adds r2, r7, r0
80042da: 8812 ldrh r2, [r2, #0]
80042dc: 430a orrs r2, r1
80042de: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
80042e0: 687b ldr r3, [r7, #4]
80042e2: 681b ldr r3, [r3, #0]
80042e4: 183a adds r2, r7, r0
80042e6: 8812 ldrh r2, [r2, #0]
80042e8: 60da str r2, [r3, #12]
80042ea: e056 b.n 800439a <UART_SetConfig+0x2f6>
}
else
{
ret = HAL_ERROR;
80042ec: 231a movs r3, #26
80042ee: 18fb adds r3, r7, r3
80042f0: 2201 movs r2, #1
80042f2: 701a strb r2, [r3, #0]
80042f4: e051 b.n 800439a <UART_SetConfig+0x2f6>
}
}
}
else
{
switch (clocksource)
80042f6: 231b movs r3, #27
80042f8: 18fb adds r3, r7, r3
80042fa: 781b ldrb r3, [r3, #0]
80042fc: 2b08 cmp r3, #8
80042fe: d015 beq.n 800432c <UART_SetConfig+0x288>
8004300: dc18 bgt.n 8004334 <UART_SetConfig+0x290>
8004302: 2b04 cmp r3, #4
8004304: d00d beq.n 8004322 <UART_SetConfig+0x27e>
8004306: dc15 bgt.n 8004334 <UART_SetConfig+0x290>
8004308: 2b00 cmp r3, #0
800430a: d002 beq.n 8004312 <UART_SetConfig+0x26e>
800430c: 2b02 cmp r3, #2
800430e: d005 beq.n 800431c <UART_SetConfig+0x278>
8004310: e010 b.n 8004334 <UART_SetConfig+0x290>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8004312: f7ff fd27 bl 8003d64 <HAL_RCC_GetPCLK1Freq>
8004316: 0003 movs r3, r0
8004318: 617b str r3, [r7, #20]
break;
800431a: e012 b.n 8004342 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800431c: 4b31 ldr r3, [pc, #196] @ (80043e4 <UART_SetConfig+0x340>)
800431e: 617b str r3, [r7, #20]
break;
8004320: e00f b.n 8004342 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8004322: f7ff fc93 bl 8003c4c <HAL_RCC_GetSysClockFreq>
8004326: 0003 movs r3, r0
8004328: 617b str r3, [r7, #20]
break;
800432a: e00a b.n 8004342 <UART_SetConfig+0x29e>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800432c: 2380 movs r3, #128 @ 0x80
800432e: 021b lsls r3, r3, #8
8004330: 617b str r3, [r7, #20]
break;
8004332: e006 b.n 8004342 <UART_SetConfig+0x29e>
default:
pclk = 0U;
8004334: 2300 movs r3, #0
8004336: 617b str r3, [r7, #20]
ret = HAL_ERROR;
8004338: 231a movs r3, #26
800433a: 18fb adds r3, r7, r3
800433c: 2201 movs r2, #1
800433e: 701a strb r2, [r3, #0]
break;
8004340: 46c0 nop @ (mov r8, r8)
}
if (pclk != 0U)
8004342: 697b ldr r3, [r7, #20]
8004344: 2b00 cmp r3, #0
8004346: d028 beq.n 800439a <UART_SetConfig+0x2f6>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004348: 687b ldr r3, [r7, #4]
800434a: 6a5a ldr r2, [r3, #36] @ 0x24
800434c: 4b26 ldr r3, [pc, #152] @ (80043e8 <UART_SetConfig+0x344>)
800434e: 0052 lsls r2, r2, #1
8004350: 5ad3 ldrh r3, [r2, r3]
8004352: 0019 movs r1, r3
8004354: 6978 ldr r0, [r7, #20]
8004356: f7fb fed3 bl 8000100 <__udivsi3>
800435a: 0003 movs r3, r0
800435c: 001a movs r2, r3
800435e: 687b ldr r3, [r7, #4]
8004360: 685b ldr r3, [r3, #4]
8004362: 085b lsrs r3, r3, #1
8004364: 18d2 adds r2, r2, r3
8004366: 687b ldr r3, [r7, #4]
8004368: 685b ldr r3, [r3, #4]
800436a: 0019 movs r1, r3
800436c: 0010 movs r0, r2
800436e: f7fb fec7 bl 8000100 <__udivsi3>
8004372: 0003 movs r3, r0
8004374: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004376: 693b ldr r3, [r7, #16]
8004378: 2b0f cmp r3, #15
800437a: d90a bls.n 8004392 <UART_SetConfig+0x2ee>
800437c: 693a ldr r2, [r7, #16]
800437e: 2380 movs r3, #128 @ 0x80
8004380: 025b lsls r3, r3, #9
8004382: 429a cmp r2, r3
8004384: d205 bcs.n 8004392 <UART_SetConfig+0x2ee>
{
huart->Instance->BRR = (uint16_t)usartdiv;
8004386: 693b ldr r3, [r7, #16]
8004388: b29a uxth r2, r3
800438a: 687b ldr r3, [r7, #4]
800438c: 681b ldr r3, [r3, #0]
800438e: 60da str r2, [r3, #12]
8004390: e003 b.n 800439a <UART_SetConfig+0x2f6>
}
else
{
ret = HAL_ERROR;
8004392: 231a movs r3, #26
8004394: 18fb adds r3, r7, r3
8004396: 2201 movs r2, #1
8004398: 701a strb r2, [r3, #0]
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
800439a: 687b ldr r3, [r7, #4]
800439c: 226a movs r2, #106 @ 0x6a
800439e: 2101 movs r1, #1
80043a0: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = 1;
80043a2: 687b ldr r3, [r7, #4]
80043a4: 2268 movs r2, #104 @ 0x68
80043a6: 2101 movs r1, #1
80043a8: 5299 strh r1, [r3, r2]
/* Clear ISR function pointers */
huart->RxISR = NULL;
80043aa: 687b ldr r3, [r7, #4]
80043ac: 2200 movs r2, #0
80043ae: 675a str r2, [r3, #116] @ 0x74
huart->TxISR = NULL;
80043b0: 687b ldr r3, [r7, #4]
80043b2: 2200 movs r2, #0
80043b4: 679a str r2, [r3, #120] @ 0x78
return ret;
80043b6: 231a movs r3, #26
80043b8: 18fb adds r3, r7, r3
80043ba: 781b ldrb r3, [r3, #0]
}
80043bc: 0018 movs r0, r3
80043be: 46bd mov sp, r7
80043c0: b008 add sp, #32
80043c2: bd80 pop {r7, pc}
80043c4: cfff69f3 .word 0xcfff69f3
80043c8: ffffcfff .word 0xffffcfff
80043cc: 11fff4ff .word 0x11fff4ff
80043d0: 40013800 .word 0x40013800
80043d4: 40021000 .word 0x40021000
80043d8: 40004400 .word 0x40004400
80043dc: 40004800 .word 0x40004800
80043e0: 40004c00 .word 0x40004c00
80043e4: 00f42400 .word 0x00f42400
80043e8: 08004b7c .word 0x08004b7c
080043ec <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
80043ec: b580 push {r7, lr}
80043ee: b082 sub sp, #8
80043f0: af00 add r7, sp, #0
80043f2: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
80043f4: 687b ldr r3, [r7, #4]
80043f6: 6a9b ldr r3, [r3, #40] @ 0x28
80043f8: 2208 movs r2, #8
80043fa: 4013 ands r3, r2
80043fc: d00b beq.n 8004416 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
80043fe: 687b ldr r3, [r7, #4]
8004400: 681b ldr r3, [r3, #0]
8004402: 685b ldr r3, [r3, #4]
8004404: 4a4a ldr r2, [pc, #296] @ (8004530 <UART_AdvFeatureConfig+0x144>)
8004406: 4013 ands r3, r2
8004408: 0019 movs r1, r3
800440a: 687b ldr r3, [r7, #4]
800440c: 6b9a ldr r2, [r3, #56] @ 0x38
800440e: 687b ldr r3, [r7, #4]
8004410: 681b ldr r3, [r3, #0]
8004412: 430a orrs r2, r1
8004414: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8004416: 687b ldr r3, [r7, #4]
8004418: 6a9b ldr r3, [r3, #40] @ 0x28
800441a: 2201 movs r2, #1
800441c: 4013 ands r3, r2
800441e: d00b beq.n 8004438 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8004420: 687b ldr r3, [r7, #4]
8004422: 681b ldr r3, [r3, #0]
8004424: 685b ldr r3, [r3, #4]
8004426: 4a43 ldr r2, [pc, #268] @ (8004534 <UART_AdvFeatureConfig+0x148>)
8004428: 4013 ands r3, r2
800442a: 0019 movs r1, r3
800442c: 687b ldr r3, [r7, #4]
800442e: 6ada ldr r2, [r3, #44] @ 0x2c
8004430: 687b ldr r3, [r7, #4]
8004432: 681b ldr r3, [r3, #0]
8004434: 430a orrs r2, r1
8004436: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8004438: 687b ldr r3, [r7, #4]
800443a: 6a9b ldr r3, [r3, #40] @ 0x28
800443c: 2202 movs r2, #2
800443e: 4013 ands r3, r2
8004440: d00b beq.n 800445a <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8004442: 687b ldr r3, [r7, #4]
8004444: 681b ldr r3, [r3, #0]
8004446: 685b ldr r3, [r3, #4]
8004448: 4a3b ldr r2, [pc, #236] @ (8004538 <UART_AdvFeatureConfig+0x14c>)
800444a: 4013 ands r3, r2
800444c: 0019 movs r1, r3
800444e: 687b ldr r3, [r7, #4]
8004450: 6b1a ldr r2, [r3, #48] @ 0x30
8004452: 687b ldr r3, [r7, #4]
8004454: 681b ldr r3, [r3, #0]
8004456: 430a orrs r2, r1
8004458: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
800445a: 687b ldr r3, [r7, #4]
800445c: 6a9b ldr r3, [r3, #40] @ 0x28
800445e: 2204 movs r2, #4
8004460: 4013 ands r3, r2
8004462: d00b beq.n 800447c <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8004464: 687b ldr r3, [r7, #4]
8004466: 681b ldr r3, [r3, #0]
8004468: 685b ldr r3, [r3, #4]
800446a: 4a34 ldr r2, [pc, #208] @ (800453c <UART_AdvFeatureConfig+0x150>)
800446c: 4013 ands r3, r2
800446e: 0019 movs r1, r3
8004470: 687b ldr r3, [r7, #4]
8004472: 6b5a ldr r2, [r3, #52] @ 0x34
8004474: 687b ldr r3, [r7, #4]
8004476: 681b ldr r3, [r3, #0]
8004478: 430a orrs r2, r1
800447a: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
800447c: 687b ldr r3, [r7, #4]
800447e: 6a9b ldr r3, [r3, #40] @ 0x28
8004480: 2210 movs r2, #16
8004482: 4013 ands r3, r2
8004484: d00b beq.n 800449e <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8004486: 687b ldr r3, [r7, #4]
8004488: 681b ldr r3, [r3, #0]
800448a: 689b ldr r3, [r3, #8]
800448c: 4a2c ldr r2, [pc, #176] @ (8004540 <UART_AdvFeatureConfig+0x154>)
800448e: 4013 ands r3, r2
8004490: 0019 movs r1, r3
8004492: 687b ldr r3, [r7, #4]
8004494: 6bda ldr r2, [r3, #60] @ 0x3c
8004496: 687b ldr r3, [r7, #4]
8004498: 681b ldr r3, [r3, #0]
800449a: 430a orrs r2, r1
800449c: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
800449e: 687b ldr r3, [r7, #4]
80044a0: 6a9b ldr r3, [r3, #40] @ 0x28
80044a2: 2220 movs r2, #32
80044a4: 4013 ands r3, r2
80044a6: d00b beq.n 80044c0 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80044a8: 687b ldr r3, [r7, #4]
80044aa: 681b ldr r3, [r3, #0]
80044ac: 689b ldr r3, [r3, #8]
80044ae: 4a25 ldr r2, [pc, #148] @ (8004544 <UART_AdvFeatureConfig+0x158>)
80044b0: 4013 ands r3, r2
80044b2: 0019 movs r1, r3
80044b4: 687b ldr r3, [r7, #4]
80044b6: 6c1a ldr r2, [r3, #64] @ 0x40
80044b8: 687b ldr r3, [r7, #4]
80044ba: 681b ldr r3, [r3, #0]
80044bc: 430a orrs r2, r1
80044be: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80044c0: 687b ldr r3, [r7, #4]
80044c2: 6a9b ldr r3, [r3, #40] @ 0x28
80044c4: 2240 movs r2, #64 @ 0x40
80044c6: 4013 ands r3, r2
80044c8: d01d beq.n 8004506 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80044ca: 687b ldr r3, [r7, #4]
80044cc: 681b ldr r3, [r3, #0]
80044ce: 685b ldr r3, [r3, #4]
80044d0: 4a1d ldr r2, [pc, #116] @ (8004548 <UART_AdvFeatureConfig+0x15c>)
80044d2: 4013 ands r3, r2
80044d4: 0019 movs r1, r3
80044d6: 687b ldr r3, [r7, #4]
80044d8: 6c5a ldr r2, [r3, #68] @ 0x44
80044da: 687b ldr r3, [r7, #4]
80044dc: 681b ldr r3, [r3, #0]
80044de: 430a orrs r2, r1
80044e0: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
80044e2: 687b ldr r3, [r7, #4]
80044e4: 6c5a ldr r2, [r3, #68] @ 0x44
80044e6: 2380 movs r3, #128 @ 0x80
80044e8: 035b lsls r3, r3, #13
80044ea: 429a cmp r2, r3
80044ec: d10b bne.n 8004506 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
80044ee: 687b ldr r3, [r7, #4]
80044f0: 681b ldr r3, [r3, #0]
80044f2: 685b ldr r3, [r3, #4]
80044f4: 4a15 ldr r2, [pc, #84] @ (800454c <UART_AdvFeatureConfig+0x160>)
80044f6: 4013 ands r3, r2
80044f8: 0019 movs r1, r3
80044fa: 687b ldr r3, [r7, #4]
80044fc: 6c9a ldr r2, [r3, #72] @ 0x48
80044fe: 687b ldr r3, [r7, #4]
8004500: 681b ldr r3, [r3, #0]
8004502: 430a orrs r2, r1
8004504: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004506: 687b ldr r3, [r7, #4]
8004508: 6a9b ldr r3, [r3, #40] @ 0x28
800450a: 2280 movs r2, #128 @ 0x80
800450c: 4013 ands r3, r2
800450e: d00b beq.n 8004528 <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8004510: 687b ldr r3, [r7, #4]
8004512: 681b ldr r3, [r3, #0]
8004514: 685b ldr r3, [r3, #4]
8004516: 4a0e ldr r2, [pc, #56] @ (8004550 <UART_AdvFeatureConfig+0x164>)
8004518: 4013 ands r3, r2
800451a: 0019 movs r1, r3
800451c: 687b ldr r3, [r7, #4]
800451e: 6cda ldr r2, [r3, #76] @ 0x4c
8004520: 687b ldr r3, [r7, #4]
8004522: 681b ldr r3, [r3, #0]
8004524: 430a orrs r2, r1
8004526: 605a str r2, [r3, #4]
}
}
8004528: 46c0 nop @ (mov r8, r8)
800452a: 46bd mov sp, r7
800452c: b002 add sp, #8
800452e: bd80 pop {r7, pc}
8004530: ffff7fff .word 0xffff7fff
8004534: fffdffff .word 0xfffdffff
8004538: fffeffff .word 0xfffeffff
800453c: fffbffff .word 0xfffbffff
8004540: ffffefff .word 0xffffefff
8004544: ffffdfff .word 0xffffdfff
8004548: ffefffff .word 0xffefffff
800454c: ff9fffff .word 0xff9fffff
8004550: fff7ffff .word 0xfff7ffff
08004554 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8004554: b580 push {r7, lr}
8004556: b092 sub sp, #72 @ 0x48
8004558: af02 add r7, sp, #8
800455a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800455c: 687b ldr r3, [r7, #4]
800455e: 2290 movs r2, #144 @ 0x90
8004560: 2100 movs r1, #0
8004562: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8004564: f7fc fdda bl 800111c <HAL_GetTick>
8004568: 0003 movs r3, r0
800456a: 63fb str r3, [r7, #60] @ 0x3c
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800456c: 687b ldr r3, [r7, #4]
800456e: 681b ldr r3, [r3, #0]
8004570: 681b ldr r3, [r3, #0]
8004572: 2208 movs r2, #8
8004574: 4013 ands r3, r2
8004576: 2b08 cmp r3, #8
8004578: d12d bne.n 80045d6 <UART_CheckIdleState+0x82>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
800457a: 6bfb ldr r3, [r7, #60] @ 0x3c
800457c: 2280 movs r2, #128 @ 0x80
800457e: 0391 lsls r1, r2, #14
8004580: 6878 ldr r0, [r7, #4]
8004582: 4a47 ldr r2, [pc, #284] @ (80046a0 <UART_CheckIdleState+0x14c>)
8004584: 9200 str r2, [sp, #0]
8004586: 2200 movs r2, #0
8004588: f000 f88e bl 80046a8 <UART_WaitOnFlagUntilTimeout>
800458c: 1e03 subs r3, r0, #0
800458e: d022 beq.n 80045d6 <UART_CheckIdleState+0x82>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8004590: f3ef 8310 mrs r3, PRIMASK
8004594: 627b str r3, [r7, #36] @ 0x24
return(result);
8004596: 6a7b ldr r3, [r7, #36] @ 0x24
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
8004598: 63bb str r3, [r7, #56] @ 0x38
800459a: 2301 movs r3, #1
800459c: 62bb str r3, [r7, #40] @ 0x28
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800459e: 6abb ldr r3, [r7, #40] @ 0x28
80045a0: f383 8810 msr PRIMASK, r3
}
80045a4: 46c0 nop @ (mov r8, r8)
80045a6: 687b ldr r3, [r7, #4]
80045a8: 681b ldr r3, [r3, #0]
80045aa: 681a ldr r2, [r3, #0]
80045ac: 687b ldr r3, [r7, #4]
80045ae: 681b ldr r3, [r3, #0]
80045b0: 2180 movs r1, #128 @ 0x80
80045b2: 438a bics r2, r1
80045b4: 601a str r2, [r3, #0]
80045b6: 6bbb ldr r3, [r7, #56] @ 0x38
80045b8: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80045ba: 6afb ldr r3, [r7, #44] @ 0x2c
80045bc: f383 8810 msr PRIMASK, r3
}
80045c0: 46c0 nop @ (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
80045c2: 687b ldr r3, [r7, #4]
80045c4: 2288 movs r2, #136 @ 0x88
80045c6: 2120 movs r1, #32
80045c8: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
80045ca: 687b ldr r3, [r7, #4]
80045cc: 2284 movs r2, #132 @ 0x84
80045ce: 2100 movs r1, #0
80045d0: 5499 strb r1, [r3, r2]
/* Timeout occurred */
return HAL_TIMEOUT;
80045d2: 2303 movs r3, #3
80045d4: e060 b.n 8004698 <UART_CheckIdleState+0x144>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80045d6: 687b ldr r3, [r7, #4]
80045d8: 681b ldr r3, [r3, #0]
80045da: 681b ldr r3, [r3, #0]
80045dc: 2204 movs r2, #4
80045de: 4013 ands r3, r2
80045e0: 2b04 cmp r3, #4
80045e2: d146 bne.n 8004672 <UART_CheckIdleState+0x11e>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80045e4: 6bfb ldr r3, [r7, #60] @ 0x3c
80045e6: 2280 movs r2, #128 @ 0x80
80045e8: 03d1 lsls r1, r2, #15
80045ea: 6878 ldr r0, [r7, #4]
80045ec: 4a2c ldr r2, [pc, #176] @ (80046a0 <UART_CheckIdleState+0x14c>)
80045ee: 9200 str r2, [sp, #0]
80045f0: 2200 movs r2, #0
80045f2: f000 f859 bl 80046a8 <UART_WaitOnFlagUntilTimeout>
80045f6: 1e03 subs r3, r0, #0
80045f8: d03b beq.n 8004672 <UART_CheckIdleState+0x11e>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80045fa: f3ef 8310 mrs r3, PRIMASK
80045fe: 60fb str r3, [r7, #12]
return(result);
8004600: 68fb ldr r3, [r7, #12]
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8004602: 637b str r3, [r7, #52] @ 0x34
8004604: 2301 movs r3, #1
8004606: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004608: 693b ldr r3, [r7, #16]
800460a: f383 8810 msr PRIMASK, r3
}
800460e: 46c0 nop @ (mov r8, r8)
8004610: 687b ldr r3, [r7, #4]
8004612: 681b ldr r3, [r3, #0]
8004614: 681a ldr r2, [r3, #0]
8004616: 687b ldr r3, [r7, #4]
8004618: 681b ldr r3, [r3, #0]
800461a: 4922 ldr r1, [pc, #136] @ (80046a4 <UART_CheckIdleState+0x150>)
800461c: 400a ands r2, r1
800461e: 601a str r2, [r3, #0]
8004620: 6b7b ldr r3, [r7, #52] @ 0x34
8004622: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004624: 697b ldr r3, [r7, #20]
8004626: f383 8810 msr PRIMASK, r3
}
800462a: 46c0 nop @ (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
800462c: f3ef 8310 mrs r3, PRIMASK
8004630: 61bb str r3, [r7, #24]
return(result);
8004632: 69bb ldr r3, [r7, #24]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004634: 633b str r3, [r7, #48] @ 0x30
8004636: 2301 movs r3, #1
8004638: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800463a: 69fb ldr r3, [r7, #28]
800463c: f383 8810 msr PRIMASK, r3
}
8004640: 46c0 nop @ (mov r8, r8)
8004642: 687b ldr r3, [r7, #4]
8004644: 681b ldr r3, [r3, #0]
8004646: 689a ldr r2, [r3, #8]
8004648: 687b ldr r3, [r7, #4]
800464a: 681b ldr r3, [r3, #0]
800464c: 2101 movs r1, #1
800464e: 438a bics r2, r1
8004650: 609a str r2, [r3, #8]
8004652: 6b3b ldr r3, [r7, #48] @ 0x30
8004654: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004656: 6a3b ldr r3, [r7, #32]
8004658: f383 8810 msr PRIMASK, r3
}
800465c: 46c0 nop @ (mov r8, r8)
huart->RxState = HAL_UART_STATE_READY;
800465e: 687b ldr r3, [r7, #4]
8004660: 228c movs r2, #140 @ 0x8c
8004662: 2120 movs r1, #32
8004664: 5099 str r1, [r3, r2]
__HAL_UNLOCK(huart);
8004666: 687b ldr r3, [r7, #4]
8004668: 2284 movs r2, #132 @ 0x84
800466a: 2100 movs r1, #0
800466c: 5499 strb r1, [r3, r2]
/* Timeout occurred */
return HAL_TIMEOUT;
800466e: 2303 movs r3, #3
8004670: e012 b.n 8004698 <UART_CheckIdleState+0x144>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
8004672: 687b ldr r3, [r7, #4]
8004674: 2288 movs r2, #136 @ 0x88
8004676: 2120 movs r1, #32
8004678: 5099 str r1, [r3, r2]
huart->RxState = HAL_UART_STATE_READY;
800467a: 687b ldr r3, [r7, #4]
800467c: 228c movs r2, #140 @ 0x8c
800467e: 2120 movs r1, #32
8004680: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004682: 687b ldr r3, [r7, #4]
8004684: 2200 movs r2, #0
8004686: 66da str r2, [r3, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004688: 687b ldr r3, [r7, #4]
800468a: 2200 movs r2, #0
800468c: 671a str r2, [r3, #112] @ 0x70
__HAL_UNLOCK(huart);
800468e: 687b ldr r3, [r7, #4]
8004690: 2284 movs r2, #132 @ 0x84
8004692: 2100 movs r1, #0
8004694: 5499 strb r1, [r3, r2]
return HAL_OK;
8004696: 2300 movs r3, #0
}
8004698: 0018 movs r0, r3
800469a: 46bd mov sp, r7
800469c: b010 add sp, #64 @ 0x40
800469e: bd80 pop {r7, pc}
80046a0: 01ffffff .word 0x01ffffff
80046a4: fffffedf .word 0xfffffedf
080046a8 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80046a8: b580 push {r7, lr}
80046aa: b084 sub sp, #16
80046ac: af00 add r7, sp, #0
80046ae: 60f8 str r0, [r7, #12]
80046b0: 60b9 str r1, [r7, #8]
80046b2: 603b str r3, [r7, #0]
80046b4: 1dfb adds r3, r7, #7
80046b6: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80046b8: e051 b.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80046ba: 69bb ldr r3, [r7, #24]
80046bc: 3301 adds r3, #1
80046be: d04e beq.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80046c0: f7fc fd2c bl 800111c <HAL_GetTick>
80046c4: 0002 movs r2, r0
80046c6: 683b ldr r3, [r7, #0]
80046c8: 1ad3 subs r3, r2, r3
80046ca: 69ba ldr r2, [r7, #24]
80046cc: 429a cmp r2, r3
80046ce: d302 bcc.n 80046d6 <UART_WaitOnFlagUntilTimeout+0x2e>
80046d0: 69bb ldr r3, [r7, #24]
80046d2: 2b00 cmp r3, #0
80046d4: d101 bne.n 80046da <UART_WaitOnFlagUntilTimeout+0x32>
{
return HAL_TIMEOUT;
80046d6: 2303 movs r3, #3
80046d8: e051 b.n 800477e <UART_WaitOnFlagUntilTimeout+0xd6>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80046da: 68fb ldr r3, [r7, #12]
80046dc: 681b ldr r3, [r3, #0]
80046de: 681b ldr r3, [r3, #0]
80046e0: 2204 movs r2, #4
80046e2: 4013 ands r3, r2
80046e4: d03b beq.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
80046e6: 68bb ldr r3, [r7, #8]
80046e8: 2b80 cmp r3, #128 @ 0x80
80046ea: d038 beq.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
80046ec: 68bb ldr r3, [r7, #8]
80046ee: 2b40 cmp r3, #64 @ 0x40
80046f0: d035 beq.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
80046f2: 68fb ldr r3, [r7, #12]
80046f4: 681b ldr r3, [r3, #0]
80046f6: 69db ldr r3, [r3, #28]
80046f8: 2208 movs r2, #8
80046fa: 4013 ands r3, r2
80046fc: 2b08 cmp r3, #8
80046fe: d111 bne.n 8004724 <UART_WaitOnFlagUntilTimeout+0x7c>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004700: 68fb ldr r3, [r7, #12]
8004702: 681b ldr r3, [r3, #0]
8004704: 2208 movs r2, #8
8004706: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004708: 68fb ldr r3, [r7, #12]
800470a: 0018 movs r0, r3
800470c: f000 f83c bl 8004788 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8004710: 68fb ldr r3, [r7, #12]
8004712: 2290 movs r2, #144 @ 0x90
8004714: 2108 movs r1, #8
8004716: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004718: 68fb ldr r3, [r7, #12]
800471a: 2284 movs r2, #132 @ 0x84
800471c: 2100 movs r1, #0
800471e: 5499 strb r1, [r3, r2]
return HAL_ERROR;
8004720: 2301 movs r3, #1
8004722: e02c b.n 800477e <UART_WaitOnFlagUntilTimeout+0xd6>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8004724: 68fb ldr r3, [r7, #12]
8004726: 681b ldr r3, [r3, #0]
8004728: 69da ldr r2, [r3, #28]
800472a: 2380 movs r3, #128 @ 0x80
800472c: 011b lsls r3, r3, #4
800472e: 401a ands r2, r3
8004730: 2380 movs r3, #128 @ 0x80
8004732: 011b lsls r3, r3, #4
8004734: 429a cmp r2, r3
8004736: d112 bne.n 800475e <UART_WaitOnFlagUntilTimeout+0xb6>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8004738: 68fb ldr r3, [r7, #12]
800473a: 681b ldr r3, [r3, #0]
800473c: 2280 movs r2, #128 @ 0x80
800473e: 0112 lsls r2, r2, #4
8004740: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8004742: 68fb ldr r3, [r7, #12]
8004744: 0018 movs r0, r3
8004746: f000 f81f bl 8004788 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
800474a: 68fb ldr r3, [r7, #12]
800474c: 2290 movs r2, #144 @ 0x90
800474e: 2120 movs r1, #32
8004750: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004752: 68fb ldr r3, [r7, #12]
8004754: 2284 movs r2, #132 @ 0x84
8004756: 2100 movs r1, #0
8004758: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
800475a: 2303 movs r3, #3
800475c: e00f b.n 800477e <UART_WaitOnFlagUntilTimeout+0xd6>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800475e: 68fb ldr r3, [r7, #12]
8004760: 681b ldr r3, [r3, #0]
8004762: 69db ldr r3, [r3, #28]
8004764: 68ba ldr r2, [r7, #8]
8004766: 4013 ands r3, r2
8004768: 68ba ldr r2, [r7, #8]
800476a: 1ad3 subs r3, r2, r3
800476c: 425a negs r2, r3
800476e: 4153 adcs r3, r2
8004770: b2db uxtb r3, r3
8004772: 001a movs r2, r3
8004774: 1dfb adds r3, r7, #7
8004776: 781b ldrb r3, [r3, #0]
8004778: 429a cmp r2, r3
800477a: d09e beq.n 80046ba <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
800477c: 2300 movs r3, #0
}
800477e: 0018 movs r0, r3
8004780: 46bd mov sp, r7
8004782: b004 add sp, #16
8004784: bd80 pop {r7, pc}
...
08004788 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004788: b580 push {r7, lr}
800478a: b08e sub sp, #56 @ 0x38
800478c: af00 add r7, sp, #0
800478e: 6078 str r0, [r7, #4]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
8004790: f3ef 8310 mrs r3, PRIMASK
8004794: 617b str r3, [r7, #20]
return(result);
8004796: 697b ldr r3, [r7, #20]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8004798: 637b str r3, [r7, #52] @ 0x34
800479a: 2301 movs r3, #1
800479c: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800479e: 69bb ldr r3, [r7, #24]
80047a0: f383 8810 msr PRIMASK, r3
}
80047a4: 46c0 nop @ (mov r8, r8)
80047a6: 687b ldr r3, [r7, #4]
80047a8: 681b ldr r3, [r3, #0]
80047aa: 681a ldr r2, [r3, #0]
80047ac: 687b ldr r3, [r7, #4]
80047ae: 681b ldr r3, [r3, #0]
80047b0: 4926 ldr r1, [pc, #152] @ (800484c <UART_EndRxTransfer+0xc4>)
80047b2: 400a ands r2, r1
80047b4: 601a str r2, [r3, #0]
80047b6: 6b7b ldr r3, [r7, #52] @ 0x34
80047b8: 61fb str r3, [r7, #28]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80047ba: 69fb ldr r3, [r7, #28]
80047bc: f383 8810 msr PRIMASK, r3
}
80047c0: 46c0 nop @ (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80047c2: f3ef 8310 mrs r3, PRIMASK
80047c6: 623b str r3, [r7, #32]
return(result);
80047c8: 6a3b ldr r3, [r7, #32]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80047ca: 633b str r3, [r7, #48] @ 0x30
80047cc: 2301 movs r3, #1
80047ce: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80047d0: 6a7b ldr r3, [r7, #36] @ 0x24
80047d2: f383 8810 msr PRIMASK, r3
}
80047d6: 46c0 nop @ (mov r8, r8)
80047d8: 687b ldr r3, [r7, #4]
80047da: 681b ldr r3, [r3, #0]
80047dc: 689a ldr r2, [r3, #8]
80047de: 687b ldr r3, [r7, #4]
80047e0: 681b ldr r3, [r3, #0]
80047e2: 491b ldr r1, [pc, #108] @ (8004850 <UART_EndRxTransfer+0xc8>)
80047e4: 400a ands r2, r1
80047e6: 609a str r2, [r3, #8]
80047e8: 6b3b ldr r3, [r7, #48] @ 0x30
80047ea: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80047ec: 6abb ldr r3, [r7, #40] @ 0x28
80047ee: f383 8810 msr PRIMASK, r3
}
80047f2: 46c0 nop @ (mov r8, r8)
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80047f4: 687b ldr r3, [r7, #4]
80047f6: 6edb ldr r3, [r3, #108] @ 0x6c
80047f8: 2b01 cmp r3, #1
80047fa: d118 bne.n 800482e <UART_EndRxTransfer+0xa6>
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
80047fc: f3ef 8310 mrs r3, PRIMASK
8004800: 60bb str r3, [r7, #8]
return(result);
8004802: 68bb ldr r3, [r7, #8]
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004804: 62fb str r3, [r7, #44] @ 0x2c
8004806: 2301 movs r3, #1
8004808: 60fb str r3, [r7, #12]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800480a: 68fb ldr r3, [r7, #12]
800480c: f383 8810 msr PRIMASK, r3
}
8004810: 46c0 nop @ (mov r8, r8)
8004812: 687b ldr r3, [r7, #4]
8004814: 681b ldr r3, [r3, #0]
8004816: 681a ldr r2, [r3, #0]
8004818: 687b ldr r3, [r7, #4]
800481a: 681b ldr r3, [r3, #0]
800481c: 2110 movs r1, #16
800481e: 438a bics r2, r1
8004820: 601a str r2, [r3, #0]
8004822: 6afb ldr r3, [r7, #44] @ 0x2c
8004824: 613b str r3, [r7, #16]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004826: 693b ldr r3, [r7, #16]
8004828: f383 8810 msr PRIMASK, r3
}
800482c: 46c0 nop @ (mov r8, r8)
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800482e: 687b ldr r3, [r7, #4]
8004830: 228c movs r2, #140 @ 0x8c
8004832: 2120 movs r1, #32
8004834: 5099 str r1, [r3, r2]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004836: 687b ldr r3, [r7, #4]
8004838: 2200 movs r2, #0
800483a: 66da str r2, [r3, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
800483c: 687b ldr r3, [r7, #4]
800483e: 2200 movs r2, #0
8004840: 675a str r2, [r3, #116] @ 0x74
}
8004842: 46c0 nop @ (mov r8, r8)
8004844: 46bd mov sp, r7
8004846: b00e add sp, #56 @ 0x38
8004848: bd80 pop {r7, pc}
800484a: 46c0 nop @ (mov r8, r8)
800484c: fffffedf .word 0xfffffedf
8004850: effffffe .word 0xeffffffe
08004854 <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
8004854: b580 push {r7, lr}
8004856: b084 sub sp, #16
8004858: af00 add r7, sp, #0
800485a: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
800485c: 687b ldr r3, [r7, #4]
800485e: 2284 movs r2, #132 @ 0x84
8004860: 5c9b ldrb r3, [r3, r2]
8004862: 2b01 cmp r3, #1
8004864: d101 bne.n 800486a <HAL_UARTEx_DisableFifoMode+0x16>
8004866: 2302 movs r3, #2
8004868: e027 b.n 80048ba <HAL_UARTEx_DisableFifoMode+0x66>
800486a: 687b ldr r3, [r7, #4]
800486c: 2284 movs r2, #132 @ 0x84
800486e: 2101 movs r1, #1
8004870: 5499 strb r1, [r3, r2]
huart->gState = HAL_UART_STATE_BUSY;
8004872: 687b ldr r3, [r7, #4]
8004874: 2288 movs r2, #136 @ 0x88
8004876: 2124 movs r1, #36 @ 0x24
8004878: 5099 str r1, [r3, r2]
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
800487a: 687b ldr r3, [r7, #4]
800487c: 681b ldr r3, [r3, #0]
800487e: 681b ldr r3, [r3, #0]
8004880: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8004882: 687b ldr r3, [r7, #4]
8004884: 681b ldr r3, [r3, #0]
8004886: 681a ldr r2, [r3, #0]
8004888: 687b ldr r3, [r7, #4]
800488a: 681b ldr r3, [r3, #0]
800488c: 2101 movs r1, #1
800488e: 438a bics r2, r1
8004890: 601a str r2, [r3, #0]
/* Enable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8004892: 68fb ldr r3, [r7, #12]
8004894: 4a0b ldr r2, [pc, #44] @ (80048c4 <HAL_UARTEx_DisableFifoMode+0x70>)
8004896: 4013 ands r3, r2
8004898: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
800489a: 687b ldr r3, [r7, #4]
800489c: 2200 movs r2, #0
800489e: 665a str r2, [r3, #100] @ 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
80048a0: 687b ldr r3, [r7, #4]
80048a2: 681b ldr r3, [r3, #0]
80048a4: 68fa ldr r2, [r7, #12]
80048a6: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
80048a8: 687b ldr r3, [r7, #4]
80048aa: 2288 movs r2, #136 @ 0x88
80048ac: 2120 movs r1, #32
80048ae: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
80048b0: 687b ldr r3, [r7, #4]
80048b2: 2284 movs r2, #132 @ 0x84
80048b4: 2100 movs r1, #0
80048b6: 5499 strb r1, [r3, r2]
return HAL_OK;
80048b8: 2300 movs r3, #0
}
80048ba: 0018 movs r0, r3
80048bc: 46bd mov sp, r7
80048be: b004 add sp, #16
80048c0: bd80 pop {r7, pc}
80048c2: 46c0 nop @ (mov r8, r8)
80048c4: dfffffff .word 0xdfffffff
080048c8 <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
80048c8: b580 push {r7, lr}
80048ca: b084 sub sp, #16
80048cc: af00 add r7, sp, #0
80048ce: 6078 str r0, [r7, #4]
80048d0: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
80048d2: 687b ldr r3, [r7, #4]
80048d4: 2284 movs r2, #132 @ 0x84
80048d6: 5c9b ldrb r3, [r3, r2]
80048d8: 2b01 cmp r3, #1
80048da: d101 bne.n 80048e0 <HAL_UARTEx_SetTxFifoThreshold+0x18>
80048dc: 2302 movs r3, #2
80048de: e02e b.n 800493e <HAL_UARTEx_SetTxFifoThreshold+0x76>
80048e0: 687b ldr r3, [r7, #4]
80048e2: 2284 movs r2, #132 @ 0x84
80048e4: 2101 movs r1, #1
80048e6: 5499 strb r1, [r3, r2]
huart->gState = HAL_UART_STATE_BUSY;
80048e8: 687b ldr r3, [r7, #4]
80048ea: 2288 movs r2, #136 @ 0x88
80048ec: 2124 movs r1, #36 @ 0x24
80048ee: 5099 str r1, [r3, r2]
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80048f0: 687b ldr r3, [r7, #4]
80048f2: 681b ldr r3, [r3, #0]
80048f4: 681b ldr r3, [r3, #0]
80048f6: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80048f8: 687b ldr r3, [r7, #4]
80048fa: 681b ldr r3, [r3, #0]
80048fc: 681a ldr r2, [r3, #0]
80048fe: 687b ldr r3, [r7, #4]
8004900: 681b ldr r3, [r3, #0]
8004902: 2101 movs r1, #1
8004904: 438a bics r2, r1
8004906: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
8004908: 687b ldr r3, [r7, #4]
800490a: 681b ldr r3, [r3, #0]
800490c: 689b ldr r3, [r3, #8]
800490e: 00db lsls r3, r3, #3
8004910: 08d9 lsrs r1, r3, #3
8004912: 687b ldr r3, [r7, #4]
8004914: 681b ldr r3, [r3, #0]
8004916: 683a ldr r2, [r7, #0]
8004918: 430a orrs r2, r1
800491a: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
800491c: 687b ldr r3, [r7, #4]
800491e: 0018 movs r0, r3
8004920: f000 f854 bl 80049cc <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8004924: 687b ldr r3, [r7, #4]
8004926: 681b ldr r3, [r3, #0]
8004928: 68fa ldr r2, [r7, #12]
800492a: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
800492c: 687b ldr r3, [r7, #4]
800492e: 2288 movs r2, #136 @ 0x88
8004930: 2120 movs r1, #32
8004932: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004934: 687b ldr r3, [r7, #4]
8004936: 2284 movs r2, #132 @ 0x84
8004938: 2100 movs r1, #0
800493a: 5499 strb r1, [r3, r2]
return HAL_OK;
800493c: 2300 movs r3, #0
}
800493e: 0018 movs r0, r3
8004940: 46bd mov sp, r7
8004942: b004 add sp, #16
8004944: bd80 pop {r7, pc}
...
08004948 <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
8004948: b580 push {r7, lr}
800494a: b084 sub sp, #16
800494c: af00 add r7, sp, #0
800494e: 6078 str r0, [r7, #4]
8004950: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8004952: 687b ldr r3, [r7, #4]
8004954: 2284 movs r2, #132 @ 0x84
8004956: 5c9b ldrb r3, [r3, r2]
8004958: 2b01 cmp r3, #1
800495a: d101 bne.n 8004960 <HAL_UARTEx_SetRxFifoThreshold+0x18>
800495c: 2302 movs r3, #2
800495e: e02f b.n 80049c0 <HAL_UARTEx_SetRxFifoThreshold+0x78>
8004960: 687b ldr r3, [r7, #4]
8004962: 2284 movs r2, #132 @ 0x84
8004964: 2101 movs r1, #1
8004966: 5499 strb r1, [r3, r2]
huart->gState = HAL_UART_STATE_BUSY;
8004968: 687b ldr r3, [r7, #4]
800496a: 2288 movs r2, #136 @ 0x88
800496c: 2124 movs r1, #36 @ 0x24
800496e: 5099 str r1, [r3, r2]
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8004970: 687b ldr r3, [r7, #4]
8004972: 681b ldr r3, [r3, #0]
8004974: 681b ldr r3, [r3, #0]
8004976: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
8004978: 687b ldr r3, [r7, #4]
800497a: 681b ldr r3, [r3, #0]
800497c: 681a ldr r2, [r3, #0]
800497e: 687b ldr r3, [r7, #4]
8004980: 681b ldr r3, [r3, #0]
8004982: 2101 movs r1, #1
8004984: 438a bics r2, r1
8004986: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
8004988: 687b ldr r3, [r7, #4]
800498a: 681b ldr r3, [r3, #0]
800498c: 689b ldr r3, [r3, #8]
800498e: 4a0e ldr r2, [pc, #56] @ (80049c8 <HAL_UARTEx_SetRxFifoThreshold+0x80>)
8004990: 4013 ands r3, r2
8004992: 0019 movs r1, r3
8004994: 687b ldr r3, [r7, #4]
8004996: 681b ldr r3, [r3, #0]
8004998: 683a ldr r2, [r7, #0]
800499a: 430a orrs r2, r1
800499c: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
800499e: 687b ldr r3, [r7, #4]
80049a0: 0018 movs r0, r3
80049a2: f000 f813 bl 80049cc <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
80049a6: 687b ldr r3, [r7, #4]
80049a8: 681b ldr r3, [r3, #0]
80049aa: 68fa ldr r2, [r7, #12]
80049ac: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
80049ae: 687b ldr r3, [r7, #4]
80049b0: 2288 movs r2, #136 @ 0x88
80049b2: 2120 movs r1, #32
80049b4: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
80049b6: 687b ldr r3, [r7, #4]
80049b8: 2284 movs r2, #132 @ 0x84
80049ba: 2100 movs r1, #0
80049bc: 5499 strb r1, [r3, r2]
return HAL_OK;
80049be: 2300 movs r3, #0
}
80049c0: 0018 movs r0, r3
80049c2: 46bd mov sp, r7
80049c4: b004 add sp, #16
80049c6: bd80 pop {r7, pc}
80049c8: f1ffffff .word 0xf1ffffff
080049cc <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
80049cc: b5f0 push {r4, r5, r6, r7, lr}
80049ce: b085 sub sp, #20
80049d0: af00 add r7, sp, #0
80049d2: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
80049d4: 687b ldr r3, [r7, #4]
80049d6: 6e5b ldr r3, [r3, #100] @ 0x64
80049d8: 2b00 cmp r3, #0
80049da: d108 bne.n 80049ee <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
80049dc: 687b ldr r3, [r7, #4]
80049de: 226a movs r2, #106 @ 0x6a
80049e0: 2101 movs r1, #1
80049e2: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = 1U;
80049e4: 687b ldr r3, [r7, #4]
80049e6: 2268 movs r2, #104 @ 0x68
80049e8: 2101 movs r1, #1
80049ea: 5299 strh r1, [r3, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
80049ec: e043 b.n 8004a76 <UARTEx_SetNbDataToProcess+0xaa>
rx_fifo_depth = RX_FIFO_DEPTH;
80049ee: 260f movs r6, #15
80049f0: 19bb adds r3, r7, r6
80049f2: 2208 movs r2, #8
80049f4: 701a strb r2, [r3, #0]
tx_fifo_depth = TX_FIFO_DEPTH;
80049f6: 200e movs r0, #14
80049f8: 183b adds r3, r7, r0
80049fa: 2208 movs r2, #8
80049fc: 701a strb r2, [r3, #0]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
80049fe: 687b ldr r3, [r7, #4]
8004a00: 681b ldr r3, [r3, #0]
8004a02: 689b ldr r3, [r3, #8]
8004a04: 0e5b lsrs r3, r3, #25
8004a06: b2da uxtb r2, r3
8004a08: 240d movs r4, #13
8004a0a: 193b adds r3, r7, r4
8004a0c: 2107 movs r1, #7
8004a0e: 400a ands r2, r1
8004a10: 701a strb r2, [r3, #0]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8004a12: 687b ldr r3, [r7, #4]
8004a14: 681b ldr r3, [r3, #0]
8004a16: 689b ldr r3, [r3, #8]
8004a18: 0f5b lsrs r3, r3, #29
8004a1a: b2da uxtb r2, r3
8004a1c: 250c movs r5, #12
8004a1e: 197b adds r3, r7, r5
8004a20: 2107 movs r1, #7
8004a22: 400a ands r2, r1
8004a24: 701a strb r2, [r3, #0]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004a26: 183b adds r3, r7, r0
8004a28: 781b ldrb r3, [r3, #0]
8004a2a: 197a adds r2, r7, r5
8004a2c: 7812 ldrb r2, [r2, #0]
8004a2e: 4914 ldr r1, [pc, #80] @ (8004a80 <UARTEx_SetNbDataToProcess+0xb4>)
8004a30: 5c8a ldrb r2, [r1, r2]
8004a32: 435a muls r2, r3
8004a34: 0010 movs r0, r2
(uint16_t)denominator[tx_fifo_threshold];
8004a36: 197b adds r3, r7, r5
8004a38: 781b ldrb r3, [r3, #0]
8004a3a: 4a12 ldr r2, [pc, #72] @ (8004a84 <UARTEx_SetNbDataToProcess+0xb8>)
8004a3c: 5cd3 ldrb r3, [r2, r3]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004a3e: 0019 movs r1, r3
8004a40: f7fb fbe8 bl 8000214 <__divsi3>
8004a44: 0003 movs r3, r0
8004a46: b299 uxth r1, r3
8004a48: 687b ldr r3, [r7, #4]
8004a4a: 226a movs r2, #106 @ 0x6a
8004a4c: 5299 strh r1, [r3, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8004a4e: 19bb adds r3, r7, r6
8004a50: 781b ldrb r3, [r3, #0]
8004a52: 193a adds r2, r7, r4
8004a54: 7812 ldrb r2, [r2, #0]
8004a56: 490a ldr r1, [pc, #40] @ (8004a80 <UARTEx_SetNbDataToProcess+0xb4>)
8004a58: 5c8a ldrb r2, [r1, r2]
8004a5a: 435a muls r2, r3
8004a5c: 0010 movs r0, r2
(uint16_t)denominator[rx_fifo_threshold];
8004a5e: 193b adds r3, r7, r4
8004a60: 781b ldrb r3, [r3, #0]
8004a62: 4a08 ldr r2, [pc, #32] @ (8004a84 <UARTEx_SetNbDataToProcess+0xb8>)
8004a64: 5cd3 ldrb r3, [r2, r3]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8004a66: 0019 movs r1, r3
8004a68: f7fb fbd4 bl 8000214 <__divsi3>
8004a6c: 0003 movs r3, r0
8004a6e: b299 uxth r1, r3
8004a70: 687b ldr r3, [r7, #4]
8004a72: 2268 movs r2, #104 @ 0x68
8004a74: 5299 strh r1, [r3, r2]
}
8004a76: 46c0 nop @ (mov r8, r8)
8004a78: 46bd mov sp, r7
8004a7a: b005 add sp, #20
8004a7c: bdf0 pop {r4, r5, r6, r7, pc}
8004a7e: 46c0 nop @ (mov r8, r8)
8004a80: 08004b94 .word 0x08004b94
8004a84: 08004b9c .word 0x08004b9c
08004a88 <memset>:
8004a88: 0003 movs r3, r0
8004a8a: 1882 adds r2, r0, r2
8004a8c: 4293 cmp r3, r2
8004a8e: d100 bne.n 8004a92 <memset+0xa>
8004a90: 4770 bx lr
8004a92: 7019 strb r1, [r3, #0]
8004a94: 3301 adds r3, #1
8004a96: e7f9 b.n 8004a8c <memset+0x4>
08004a98 <__libc_init_array>:
8004a98: b570 push {r4, r5, r6, lr}
8004a9a: 2600 movs r6, #0
8004a9c: 4c0c ldr r4, [pc, #48] @ (8004ad0 <__libc_init_array+0x38>)
8004a9e: 4d0d ldr r5, [pc, #52] @ (8004ad4 <__libc_init_array+0x3c>)
8004aa0: 1b64 subs r4, r4, r5
8004aa2: 10a4 asrs r4, r4, #2
8004aa4: 42a6 cmp r6, r4
8004aa6: d109 bne.n 8004abc <__libc_init_array+0x24>
8004aa8: 2600 movs r6, #0
8004aaa: f000 f819 bl 8004ae0 <_init>
8004aae: 4c0a ldr r4, [pc, #40] @ (8004ad8 <__libc_init_array+0x40>)
8004ab0: 4d0a ldr r5, [pc, #40] @ (8004adc <__libc_init_array+0x44>)
8004ab2: 1b64 subs r4, r4, r5
8004ab4: 10a4 asrs r4, r4, #2
8004ab6: 42a6 cmp r6, r4
8004ab8: d105 bne.n 8004ac6 <__libc_init_array+0x2e>
8004aba: bd70 pop {r4, r5, r6, pc}
8004abc: 00b3 lsls r3, r6, #2
8004abe: 58eb ldr r3, [r5, r3]
8004ac0: 4798 blx r3
8004ac2: 3601 adds r6, #1
8004ac4: e7ee b.n 8004aa4 <__libc_init_array+0xc>
8004ac6: 00b3 lsls r3, r6, #2
8004ac8: 58eb ldr r3, [r5, r3]
8004aca: 4798 blx r3
8004acc: 3601 adds r6, #1
8004ace: e7f2 b.n 8004ab6 <__libc_init_array+0x1e>
8004ad0: 08004ba4 .word 0x08004ba4
8004ad4: 08004ba4 .word 0x08004ba4
8004ad8: 08004ba8 .word 0x08004ba8
8004adc: 08004ba4 .word 0x08004ba4
08004ae0 <_init>:
8004ae0: b5f8 push {r3, r4, r5, r6, r7, lr}
8004ae2: 46c0 nop @ (mov r8, r8)
8004ae4: bcf8 pop {r3, r4, r5, r6, r7}
8004ae6: bc08 pop {r3}
8004ae8: 469e mov lr, r3
8004aea: 4770 bx lr
08004aec <_fini>:
8004aec: b5f8 push {r3, r4, r5, r6, r7, lr}
8004aee: 46c0 nop @ (mov r8, r8)
8004af0: bcf8 pop {r3, r4, r5, r6, r7}
8004af2: bc08 pop {r3}
8004af4: 469e mov lr, r3
8004af6: 4770 bx lr
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